JP2000183298A - Semiconductor storage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage that can improve the yield of a conforming article, together with increase a memory cell capacity. SOLUTION: A semiconductor storage is provided with a semiconductor substrate where a first diffusion layer 3a, a second diffusion layer 6a, and a channel formation region are formed, a plurality of word lines that are arranged on the channel formation region, a plurality of bit lines that are connected to the second diffusion layer 6a, a plurality of capacity contacts 1a that are in a square shape whose one-side is equal to a design standard dimension F in terms of top view and are arranged in a lattice shape with the interval F in parallel with the word line, a plurality of capacity electrodes 2a that has a T-shape, where a band-shaped margin part 5a is provided selectively from its end part at both long side parts of a rectangle whose short side is equal to F in terms of top view, and a capacity plate electrode that opposes the capacity electrode 2a. The capacity contact 1a is arranged at a region where the margin part 5a is provided in terms of top view, and a region where no margin part 5a is formed is arranged with the interval F in a direction that is in parallel with the word line.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device capable of improving the yield of non-defective products and increasing the memory cell capacity.

[0002]

2. Description of the Related Art One type of semiconductor memory device is a dynamic random access memory (DRAM).
ess Memory). 4 and 5 are schematic plan views showing capacitor electrode patterns of a memory cell array of a conventional semiconductor memory device (DRAM).

As shown in FIG. 4, in a conventional memory cell array of a first semiconductor memory device, a plurality of memory cells 104a are arranged in a substantially lattice shape.
The memory cell 104a is provided with a rectangular capacitor in plan view as a cell capacitor. This capacitor is formed by laminating a capacitor electrode 102a, a capacitor insulating film, and a capacitor plate electrode (all not shown) in the thickness direction from the bottom. The capacitance plate electrode is formed on one surface.

[0004] Assuming that the long side direction of the capacitor electrode 102a is X and the orthogonal direction is Y direction, the length of the short side of the capacitor electrode 102a and the distance between adjacent capacitor electrodes 102a in the Y direction are both resolutions during lithography. The design standard dimension (minimum dimension) F is close to the limit. Note that the capacitance electrode 102
The length of the long side of “a” is about three times (3 × F) the short side.

A capacitor contact (cell node contact) 101a is formed below the capacitor electrode 102a of the capacitor. The capacitance contact 101a is located at the center of the capacitance electrode 102a in plan view, that is, the capacitance contact 10a.
The capacitor electrode 102a is disposed so as to be point-symmetric with respect to the center of 1a.

Further, a MOS transistor is provided below the capacitor contact 101a, and a first diffusion layer 103a serving as a source or drain region is formed below the capacitor contact 101a. Also, a second diffusion layer 106a corresponding to the first diffusion layer 103a is formed, and the second diffusion layer 106a is shared by two memory cells 104a adjacent in the X direction. That is, the transistor shares the second diffusion layer 106a disposed between the two memory cells 104a as a source or drain region.

A word line (not shown) serves as a gate electrode on a channel forming region formed between the first diffusion layer 103a and the second diffusion layer 106a via a gate insulating film (not shown). They are provided so as to extend in parallel. Further, bit lines (not shown) are arranged at regular intervals so as to extend perpendicular to the word lines, and are electrically connected to the second diffusion layer 106a.

As described above, each memory cell 104a is formed on a semiconductor substrate. In this memory cell 104a, the pitch in the Y direction is １ ／ of the pitch in the X direction with respect to the center of the capacitance electrode 102a. Thus, the memory cell array is arranged in a lattice pattern. That is, it is a memory cell of 1/2 pitch.
At this time, the capacitance contacts 101a are arranged in a lattice.

In the memory cell 104a of the first conventional semiconductor memory device thus configured, the capacitance electrode 1
Since the length of the short side of 02a and the length of one side of the capacitor contact are both equal to the design reference dimension F, if a misalignment occurs during patterning for forming the capacitor electrode 102a, the capacitor electrode 102a is formed. At the time of etching, a part of the capacity contact 101a is exposed, and a part of the capacity contact 101a is removed. At this time, if the capacitor contact 101a is removed until reaching the diffusion layer 103a formed below the capacitor contact 101a, a leak current is generated. Therefore, there is a disadvantage that the yield of non-defective products of the semiconductor memory device is reduced.

On the other hand, in order to solve the above-mentioned disadvantage of the memory cell 104a, there is a memory cell in which a dimensional margin is provided in a portion where a capacitance contact is formed in a capacitor.

As shown in FIG. 5, in the memory cell 104b of the second conventional semiconductor memory device, a capacitor is provided as a cell capacitance section. This capacitor has a substantially cross shape in plan view, that is, the length of the short side is the design standard dimension F,
It has a rectangular shape whose long side is about three times as long as the short side, and a shape in which a margin portion 105b having a width c is selectively provided at the center of both long sides. This capacitor is formed by laminating a capacitor electrode 102b, a capacitor insulating film, and a capacitor plate electrode (all not shown) in the thickness direction from below. The capacitance plate electrode is formed on one surface.

Assuming that the long side direction of the capacitor electrode 102b is X and the orthogonal direction is Y direction, the adjacent capacitor electrode 102b
The interval in the Y direction of the portion where the margin portion 105b is not formed is the design reference dimension F, and the interval in the Y direction of the portion where the margin portion 105b is formed is a (=
F−2 × c <F).

Similarly to the memory cell 104a, a square-shaped capacitor contact 101 whose one side has a design standard dimension F in plan view is provided under the capacitor electrode 102b of the capacitor.
a is formed. The capacitance contact 101a is arranged such that the capacitance electrode 102b is point-symmetric with respect to the center of the capacitance electrode 102b in plan view, that is, the center of the capacitance contact 101a.

Further, similarly to the memory cell 104a, a first diffusion layer 103a, a second diffusion layer 106a, a gate electrode (word line: not shown) and the like of a MOS transistor are provided below the capacitance contact 101a. I have.

As described above, each memory cell 104b is formed on the semiconductor substrate, and in this memory cell 104b, the pitch in the Y direction with respect to the pitch in the X direction is ２ with respect to the center of the capacitance electrode 102b. Thus, the memory cell array is arranged in a lattice pattern. That is, it is a memory cell of 1/2 pitch.
At this time, the capacitance contacts 101a are arranged in a lattice.

In the memory cell 104b of the second conventional semiconductor memory device configured as described above, the capacitance electrode 1
Since the margin portion 105b is formed in the portion of the capacitor 02b where the capacitor contact 101a is formed, even if misalignment or the like occurs during patterning for forming the capacitor electrode 102b, the margin portion 105b is used to form the capacitor electrode 102b. Exposure of part of the capacitance contact 101a during etching can be reduced. Therefore, there is a process margin for removing a part of the capacitor contact 101a. For this reason, generation of a leakage current can be reduced, and a decrease in the yield of non-defective semiconductor storage devices due to the generation of the leakage current can be prevented.

[0017]

However, as described above, the memory cell 10 of the second conventional semiconductor memory device is used.
4b, the interval in the Y direction of the portion where the margin portion 105b of the adjacent capacitor electrode 102b is formed is a (= F
−2 × c <F), which is shorter than the design reference dimension F. Accordingly, it becomes difficult to perform good patterning during lithography for forming the capacitor electrode 102b, so that the photoresist is likely to remain in the space G in the Y direction at the portion where the margin portion 105b of the adjacent capacitor electrode 102b is formed. For this reason, the conductive film formed on the entire surface of the wafer for forming the capacitor electrode remains in the space G, and a short circuit between the adjacent capacitor electrodes 102b is likely to occur, thereby lowering the yield of non-defective semiconductor memory devices. There is a problem. Further, as described above, when the margin portion is provided, a problem occurs, and the margin portion cannot be provided. Therefore, the area of the capacitor electrode cannot be increased, and the memory cell capacity cannot be increased. .

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a semiconductor memory device that can improve the yield of non-defective products and increase the memory cell capacity.

[0019]

In a semiconductor memory device according to the present invention, memory cells each including a transistor and a capacitor are arranged in an array, and a capacitor electrode pattern of the capacitor is connected to the transistor. In the semiconductor memory device in which the capacitance contacts are arranged in a lattice, the capacitance contacts are arranged to be shifted from the center of the capacitance electrode pattern of the capacitance portion.

Further, in the capacitance electrode pattern, a portion where the capacitance contact is arranged is wider than other portions, and each capacitance electrode pattern has the same direction of displacement between the capacitance contact and the capacitance electrode pattern. They can be arranged in a grid.

Furthermore, the capacitor contacts and the capacitor electrode patterns can be arranged so that the direction of the shift is alternately opposite for each row of the memory cell array.

In this case, in the capacitance electrode pattern, a portion where the capacitance contact is arranged can be wider than other portions.

The semiconductor memory device according to the present invention has a first diffusion layer for all memory cells, a second diffusion layer shared by two adjacent memory cells, and the first diffusion layer and the second diffusion layer. A channel forming region disposed between the second diffusion layer and the first diffusion layer is formed between the first and second diffusion layers.
A plurality of word lines disposed on a channel forming region of the semiconductor substrate via a gate insulating film so as to extend in parallel with each other; A plurality of bit lines connected to the second diffusion layer and arranged at regular intervals so as to extend orthogonally to the word lines; and one bit line formed on the first diffusion layer and viewed in plan. A plurality of capacitor contacts having a square shape with a side length equal to the design reference size and arranged in a lattice shape at intervals equal to the design reference size in a direction parallel to the word line, The rectangular shape whose length is the design reference dimension has a T-shape in which a band-shaped margin portion is selectively provided from both ends of the rectangular long side portion, and the long side direction is parallel to the bit line. Placed in the corresponding container A plurality of first capacitance electrode patterns connected to the first diffusion layer via a contact, and the first capacitance electrode pattern adjacent to the first capacitance electrode pattern and having the same shape and corresponding to the first capacitance electrode pattern; A plurality of second capacitor electrode patterns connected to the diffusion layer, wherein the capacitor contacts are arranged with respect to a pitch in a direction parallel to the bit line between adjacent capacitor contacts with reference to the center in plan view. The pitch in the direction parallel to the word line is ２, and is disposed in a region where a margin portion of the first and second capacitor electrode patterns is provided. The region where the margin part is not formed is arranged at an interval equal to the design reference dimension in a direction parallel to the word line.

Further, in the semiconductor memory device according to the present invention, the first diffusion layer is provided in all memory cells, the second diffusion layer is shared by two adjacent memory cells, and the first diffusion layer and the A channel formation region disposed between the first diffusion layer and the second diffusion layer, and two adjacent first diffusion layers are respectively disposed on both sides of the common second diffusion layer; A plurality of word lines arranged on a channel forming region of the substrate via a gate insulating film so as to extend in parallel with each other, and a certain number of word lines on the semiconductor substrate extending perpendicular to the word lines. A plurality of bit lines arranged at an interval and connected to the second diffusion layer, and a square shape formed on the first diffusion layer and having a side length equal to a design reference dimension in plan view. The design reference dimension in a direction parallel to the word line A plurality of capacitive contacts arranged in a grid with an equal interval to the rectangular shape in which a strip-shaped margin portion is provided over both long side portions of a rectangle whose short side is the design reference dimension in plan view. A plurality of first capacitor electrode patterns which are arranged such that their long sides are parallel to the bit lines and are connected to the first diffusion layer via the corresponding capacitor contacts; A plurality of second capacitor electrode patterns which are adjacent to and have the same shape as the capacitor electrode patterns and are connected to the first diffusion layer via the corresponding capacitor contacts, wherein the capacitor contacts are viewed in plan. The pitch in the direction parallel to the word line is １ ／ of the pitch in the direction parallel to the bit line between adjacent capacitor contacts with respect to the center thereof, and the first and second capacitor electrode patterns Characterized in that it is arranged in a region other than the center.

The first and second capacitor electrode patterns arranged in a direction parallel to the bit lines are provided so as to have the same arrangement in plan view with respect to the corresponding capacitor contacts. can do. Further, the first and second capacitor electrode patterns are respectively arranged along a direction parallel to the adjacent bit lines, and are arranged so as to be alternately opposite in a direction parallel to the word lines. be able to.

In the present invention, the space near the capacitor contact between adjacent capacitor electrode patterns has a cross shape in which the lines are orthogonal or a T shape in which the lines intersect. For this reason, the light intensity in the space near the capacitor contact is relatively large in the lithography process, and the photoresist is more susceptible to reaction than in the case where the space near the capacitor contact is linear as in the prior art. That is,
Residual photoresist is less likely to occur. Therefore, the conductive film formed on the entire surface of the wafer for forming the capacitor electrode pattern does not remain in the space near the capacitor contact, and it is possible to prevent the occurrence of a short circuit between the adjacent capacitor electrode patterns. . Further, the space can be reduced and the area of the capacitor electrode pattern can be increased instead. Therefore, the yield of non-defective semiconductor memory devices can be improved, and the memory cell capacity can be increased.

Further, even if the space in the direction parallel to the word line at the portion where the margin portion of the adjacent capacitor electrode pattern is provided is smaller than the design reference dimension,
The photoresist is resolved, and good patterning can be performed. Further, since the margin portion can be provided, the area of the capacitor electrode pattern can be increased. Therefore, the yield of non-defective semiconductor memory devices can be improved, and the memory cell capacity can be increased.

Further, in the present invention, the area of the margin portion can be further increased, and the area of the capacitor electrode pattern can be further increased. Thereby, the memory cell capacity can be further increased.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor memory device according to an embodiment of the present invention will be specifically described below with reference to the accompanying drawings. FIG. 1 is a schematic plan view showing a capacitor electrode pattern of a memory cell array of a semiconductor memory device according to a first embodiment of the present invention.

As shown in FIG. 1, in the memory cell array of the semiconductor memory device according to the first embodiment of the present invention, a plurality of memory cells 4a are arranged in a substantially lattice shape. The memory cell 4a is provided with a capacitor as a cell capacitance section. This capacitor is substantially T-shaped in a plan view, that is, a rectangle whose short side length is a design reference dimension (minimum dimension) F that is close to the resolution limit at the time of lithography, and whose long side is about three times the short side. In addition, a margin portion 5a having a width of c is provided at an end portion of both long sides thereof with a length of b from the end portion. This capacitor is formed by laminating a capacitor electrode 2a, a capacitor insulating film, and a capacitor plate electrode (all not shown) in the thickness direction from the bottom. The capacitance plate electrode is formed on one surface.

Assuming that the long side direction of the capacitor electrode 2a is X and the orthogonal direction is Y direction, the distance in the Y direction between the adjacent capacitor electrodes 2a where the margin 5a is not formed is the design standard dimension F. Similarly, the interval in the Y direction of the portion where the margin portion 5a is formed is a (= F−2 × c <F).

A capacitor contact (cell node contact) 1a is formed below the portion of the capacitor electrode 2a of the capacitor in which the margin portion 5a is formed. Have been. The capacitance contacts 1a are arranged with a margin of width c in the Y direction in plan view. The capacitance contacts 1a are arranged in a lattice. That is, the memory cell 4 of the present embodiment
In a, unlike the memory cell 104b of the conventional second semiconductor memory device, the capacitor electrode 2a is not arranged so as to be point-symmetric with respect to the center of the capacitor contact 1a.

Further, an MO is provided below the capacitor contact 1a.
An S-type transistor is provided, and a first diffusion layer 3a serving as a source or drain region is provided with a capacitor contact 1a.
Is formed at the bottom. Further, a second diffusion layer 6a corresponding to the first diffusion layer 3a is formed, and this second diffusion layer 6a is shared by two memory cells 4a adjacent in the X direction. That is, the transistor is composed of two memory cells 4
The second diffusion layer 6a disposed between the first and second a is shared as a source or drain region.

A word line (not shown) serves as a gate electrode on a channel forming region formed between the first diffusion layer 3a and the second diffusion layer 6a via a gate insulating film (not shown). They are provided so as to extend in parallel. Further, bit lines (not shown) are arranged at regular intervals so as to extend perpendicular to the word lines, and are electrically connected to the second diffusion layer 6a.

As described above, each memory cell 4a is formed on the semiconductor substrate. In this memory cell 4a, the pitch in the Y direction is 1/2 of the pitch in the X direction with respect to the center of the capacitor electrode 2a. Thus, the memory cell array is arranged in a lattice pattern. That is, 1
/ 2 pitch memory cells.

In the memory cell 4a of the semiconductor memory device according to the first embodiment of the present invention thus configured, the space near the capacitor contact 1a (near the interval a) in a plan view between the adjacent capacitor electrodes 2a. A is not a line shape as in the related art, but a cross shape in which lines are orthogonal. For this reason, the light intensity in the space A portion is relatively large in the lithography process, and the photoresist is liable to react, as compared with the case where the space near the capacitance contact is linear as in the prior art. That is, the photoresist hardly remains. Therefore, even if the interval in the Y direction of the portion where the margin portion 5a of the adjacent capacitor electrode 2a is formed is set to the interval a smaller than the design reference dimension F as in the present embodiment, the photoresist can be dissolved. An image can be formed and good patterning can be performed.

Therefore, the conductive film formed on the entire surface of the wafer for forming the capacitor electrode pattern does not remain in the space A, and the occurrence of a short circuit between adjacent capacitor electrode patterns can be prevented. . Also, the margin part 5
Since a can be provided, the area of the capacitor electrode pattern can be increased. Thereby, the yield of non-defective products of the semiconductor memory device can be improved, and the memory cell capacity can be increased.

FIG. 2 is a schematic plan view showing a capacitor electrode pattern of a memory cell array of a semiconductor memory device according to a second embodiment of the present invention. As shown in FIG. 2, in a memory cell array of a semiconductor memory device according to a second embodiment of the present invention, a plurality of memory cells 4b are arranged in a substantially lattice shape. The memory cell 4b is provided with a capacitor as a cell capacitance section. This memory cell 4b
Has the same configuration as the memory cell 4a of the first embodiment,
Assuming that the long side direction of the capacitor electrode 2a is X and the orthogonal direction is Y direction, the memory cells 4b are arranged so that the directions of the memory cells 4b are alternately reversed in the Y direction, thereby forming a memory cell array. Except for the arrangement of the memory cells 4b, the configuration is the same as that of the first embodiment, and the description is omitted.

In the memory cell 4b of the semiconductor memory device according to the second embodiment of the present invention thus configured, the space near the capacitor contact 1a (near the interval a) in a plan view between the adjacent capacitor electrodes 2a. B has a shape in which lines intersect in a T-shape, not a line shape as in the related art. For this reason, as in the first embodiment, in the lithography process, the light intensity in the space portion is relatively large, and the photoresist easily reacts. That is, the photoresist hardly remains.

Therefore, as in the first embodiment, the conductive film formed on the entire surface of the wafer for forming the capacitor electrode pattern does not remain in the space B, and a short circuit between adjacent capacitor electrode patterns occurs. Can be prevented. Further, the area of the capacitor electrode pattern can be increased. Thereby, the yield of non-defective products of the semiconductor memory device can be improved, and the memory cell capacity can be increased.

FIG. 3 is a schematic plan view showing a capacitor electrode pattern of a memory cell array of a semiconductor memory device according to a third embodiment of the present invention. As shown in FIG. 3, in the memory cell array of the semiconductor memory device according to the third embodiment of the present invention, a plurality of memory cells 4c are arranged in a substantially lattice shape. The memory cell 4c is provided with a capacitor as a cell capacitance section. The capacitance electrode 2c of this capacitor has a short side length (F + 2 × c) in plan view,
The length of the long side is the same as in the second embodiment. That is, as compared with the capacitor electrode 2a of the second embodiment, the margin portion 5c is formed not only at the end but also over the entire long side. That is,
The length of the margin portion 5c is longer than b. Also,
Except for the shape of the capacitor, it is the same as the second embodiment, and the description is omitted.

In the memory cell 4c of the semiconductor memory device according to the third embodiment of the present invention thus configured, the space near the capacitor contact 1a (near the interval a) in a plan view between the adjacent capacitor electrodes 2c. C has a shape in which lines intersect in a T-shape, instead of a line shape as in the related art. For this reason, as in the second embodiment, in the lithography process, the light intensity in the space portion is relatively large, and the photoresist easily reacts. That is, the photoresist hardly remains.

Therefore, as in the second embodiment, the conductive film formed on the entire surface of the wafer for forming the capacitor electrode pattern does not remain in the space C, and a short circuit between adjacent capacitor electrode patterns occurs. Can be prevented. Further, the area of the capacitor electrode pattern can be further increased. As a result, the yield of non-defective products of the semiconductor memory device can be improved, and the memory cell capacity can be further increased.

[0044]

As described in detail above, according to the present invention,
The conductive film formed on the entire surface of the wafer for forming the capacitor electrode pattern does not remain in the space near the capacitor contact, and the occurrence of a short circuit between adjacent capacitor electrode patterns can be prevented. Further, the space can be reduced and the area of the capacitor electrode pattern can be increased instead. Therefore, the yield of non-defective semiconductor memory devices can be improved, and the memory cell capacity can be increased.

Further, even if the space in the direction parallel to the word line in the portion where the margin portion of the adjacent capacitor electrode pattern is provided is smaller than the design reference dimension,
The photoresist is resolved, and good patterning can be performed. Further, since the margin portion can be provided, the area of the capacitor electrode pattern can be increased. Therefore, the yield of non-defective semiconductor memory devices can be improved, and the memory cell capacity can be increased.

[Brief description of the drawings]

FIG. 1 is a schematic plan view showing a capacitor electrode pattern of a memory cell array of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a schematic plan view showing a capacitor electrode pattern of a memory cell array of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 3 is a schematic plan view showing a capacitor electrode pattern of a memory cell array of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 4 is a schematic plan view showing a capacitor electrode pattern of a memory cell array of a conventional semiconductor memory device (DRAM).

FIG. 5 is a schematic plan view showing a capacitor electrode pattern of a memory cell array of a conventional semiconductor memory device (DRAM).

[Explanation of symbols]

 1a, 101a; capacitance contacts 2a, 2c, 102a, 102b; capacitance electrodes 3a, 103a; first diffusion layers 4a, 4b, 4c, 104a, 104b; memory cells 5a, 5c, 105b; margin portions 6a, 106a; Diffusion layer

Claims (8)

[Claims] 1. A semiconductor memory device in which memory cells each including a transistor and a capacitor are arranged in an array, and capacitor contacts connecting the capacitor electrode pattern of the capacitor and the transistor are arranged in a lattice. At
2. The semiconductor memory device according to claim 1, wherein the capacitance contact is arranged at a position shifted from the center of the capacitance electrode pattern of the capacitance portion. 2. The capacitor electrode pattern is wider at a portion where the capacitor contact is disposed than at other portions, and each capacitor electrode pattern has the same direction of displacement between the capacitor contact and the capacitor electrode pattern. 2. The semiconductor memory device according to claim 1, wherein said semiconductor memory device is arranged in a lattice. 3. The semiconductor memory device according to claim 1, wherein the direction of displacement between the capacitance contact and the capacitance electrode pattern is alternately reversed for each row of the memory cell array. 4. The semiconductor memory device according to claim 3, wherein said capacitor electrode pattern is wider at a portion where said capacitor contact is arranged than at other portions. 5. A first diffusion layer for all memory cells, a second diffusion layer shared by two adjacent memory cells, and disposed between the first diffusion layer and the second diffusion layer. And two adjacent first diffusion layers, each of which is formed with a common second diffusion layer interposed therebetween, and a gate insulating region formed on the channel formation region of the semiconductor substrate. A plurality of word lines arranged via a film and formed so as to extend in parallel with each other, and the second diffusion layer arranged on the semiconductor substrate at a constant interval so as to extend orthogonal to the word lines. A plurality of bit lines connected to a layer, a square shape formed on the first diffusion layer and having a side length equal to a design reference dimension in a plan view and parallel to the word line; Arranged in a grid with an interval equal to the design standard size A plurality of capacitor contacts and a T-shape in which a short margin is selectively provided at both long sides of the rectangle whose short side length is the design reference dimension in plan view from an end thereof. A plurality of first capacitor electrode patterns which are arranged so that their long sides are parallel to the bit lines and are connected to the first diffusion layer via the corresponding capacitor contacts; A plurality of second capacitor electrode patterns which are adjacent to and have the same shape as the capacitor electrode patterns and are connected to the first diffusion layer via the corresponding capacitor contacts, wherein the capacitor contacts are in plan view. The pitch in the direction parallel to the word line is １ ／ of the pitch in the direction parallel to the bit line between adjacent capacitor contacts based on the center thereof, and the first and second capacitor electrode patterns Margin is provided And a region where a margin portion of the first and second capacitor electrode patterns is not formed is disposed at an interval equal to the design reference dimension in a direction parallel to the word line. Semiconductor storage device. 6. A first diffusion layer for all memory cells, a second diffusion layer shared by two adjacent memory cells, and disposed between the first diffusion layer and the second diffusion layer. And two adjacent first diffusion layers, each of which is formed with a common second diffusion layer interposed therebetween, and a gate insulating region formed on the channel formation region of the semiconductor substrate. A plurality of word lines arranged via a film and formed so as to extend in parallel with each other, and the second diffusion layer arranged on the semiconductor substrate at a constant interval so as to extend orthogonal to the word lines. A plurality of bit lines connected to a layer, a square shape formed on the first diffusion layer and having a side length equal to a design reference dimension in a plan view and parallel to the word line; Arranged in a grid with an interval equal to the design standard size A plurality of capacitor contacts, and a rectangular shape in which the length of the short side in plan view is the design reference dimension, and a strip-shaped margin portion is provided over both long side portions of the rectangle. A plurality of first capacitance electrode patterns arranged parallel to the bit lines and connected to the first diffusion layer through the corresponding capacitance contacts, and adjacent to and identical to the first capacitance electrode patterns; And a plurality of second capacitance electrode patterns connected to the first diffusion layer via the corresponding capacitance contacts, wherein the capacitance contacts are adjacent to each other with reference to the center thereof in plan view. The pitch between the capacitor contacts in the direction parallel to the word lines is １ ／ of the pitch in the direction parallel to the bit lines, and is arranged in a region other than the center of the first and second capacitor electrode patterns. That The semiconductor memory device according to claim. 7. The first and second capacitance electrode patterns arranged in a direction parallel to the bit line are provided so as to be identical to the corresponding capacitance contacts in plan view. 7. The semiconductor memory device according to claim 5, wherein: 8. The first and second capacitor electrode patterns are respectively arranged along a direction parallel to the adjacent bit lines, and are arranged so as to be alternately opposite in a direction parallel to the word lines. 8. The semiconductor memory device according to claim 7, wherein: