JP2012216860A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which minimizes a dead space in arrangement of capacitors and maximizes a shape of individual capacitor.SOLUTION: A semiconductor device comprises: a first and a second transfer gates 2 linearly extending in parallel and adjacent to each other; a first and a second storage node contacts 9 arranged in a gap between the transfer gates and composed of rod-like conductors extending upward, respectively; a first capacitor 14 in which a first electrode and a second electrode are arranged to face each other via an insulation film; and a second capacitor 14 in which a third electrode and a fourth electrode are arranged to face each other via an insulation film. When viewed from above, a top face of the first storage node contact 9 is connected to only a part of the first electrode on the first transfer gate side, and a top face of the second storage node contact 9 is connected to only a part of the third electrode on the second transfer gate side.

Description

  The present invention relates to a semiconductor device. In particular, the present invention relates to an array of capacitors formed above a transfer gate in a memory cell portion.

  A conventional semiconductor device will be described with reference to FIGS. FIG. 11 is a plan view of the memory cell portion of this semiconductor device. However, in order to explain the positional relationship between the respective parts, it is shown that the interlayer insulating film that originally fills the gaps between the respective parts is assumed to be transparent. FIG. 12 shows a cross-sectional view taken along the center line of the bit line 6 in FIG. 11, that is, a cross-sectional view taken along the line XII-XII. FIG. 13 shows a cross-sectional view taken along the center line of the capacitor 14 in FIG. 11, that is, a cross-sectional view taken along the line XIII-XIII. A plurality of transfer gates 2 are linearly formed in parallel to each other so as to rise on the main surface of the semiconductor substrate 1 such as a silicon wafer. In the gaps of these transfer gates 2, lower contact 4a made of a conductor is formed in a substantially elliptical shape having a major axis parallel to the longitudinal direction of the transfer gate 2 so as to be connected to each bit line 6 at a constant interval. Has been. As shown in FIG. 12, the lower layer contact 4 a is electrically connected to the main surface of the semiconductor substrate 1. The upper side of the transfer gate 2 is covered with an interlayer insulating film 3.

  As shown in FIG. 12, the bit line contact 7 is electrically connected to the lower layer contact 4a from above. The bit line contact 7 is for electrically connecting the bit line 6 which is a conductor extending in the horizontal direction above the transfer gate 2 and the lower layer contact 4a. The lower portion of the bit line 6 on the upper side of the lower layer contact 4 a is filled with the interlayer insulating film 5. The upper part of the bit line 6 is filled with an interlayer insulating film 8.

  On the other hand, as shown in FIG. 13, a plurality of capacitors 14 arranged above the transfer gate 2 are so-called concave capacitors. That is, it is a cup-type capacitor having a bottom surface at the lower end and an opening at the upper end. As shown in FIG. 11, the cross-sectional shape when cut along the horizontal plane is a shape in which two semicircles facing each other at some distance are connected by parallel sides. A capacitor is configured by contacting two conductor portions of the storage node 11 and the cell plate cylindrical portion 12 through an insulating film (not shown) along the cup shape. The storage node 11 covers the outside of the cup shape, and is electrically connected by a storage node contact 9 to a lower layer contact 4 b formed in the gap of the transfer gate 2. That is, there are two types of lower layer contacts: a lower layer contact 4a to which the bit line contact 7 is connected and a lower layer contact 4b to which the storage node contact 9 is connected. A portion where the capacitor 14 is not present above the storage node contact 9 is filled with the interlayer insulating film 10. The upper surface of the interlayer insulating film 10 is covered with a cell plate upper surface portion 13 which is a conductor. The cell plate upper surface portion 13 is connected to the cell plate cylindrical portion 12. An insulating film (not shown) is interposed between the cell plate upper surface portion 13 and the storage node 11 to be insulated.

  The capacitor 14 is a capacitor, and it is desirable to increase the capacity. In the case where the thickness (distance in the vertical direction in FIG. 13) is constant, it is desired to increase the cross-sectional shape of the capacitor 14 in order to increase the capacitance. In the case of a concave capacitor, if the aspect ratio as a value obtained by dividing the depth by the width becomes too large, there is a problem in that an embedding failure of the electrode material in the capacitor 14 occurs or the etching shape deteriorates. From this point of view, it is desirable to increase the cross-sectional shape.

  By the way, the arrangement of the conventional capacitors 14 is arranged so that the center of the storage node contact 9 and the center of the capacitor 14 coincide with each other directly above the storage node contact 9 as shown in FIG. As a result, the result was an array of squares. FIG. 14 shows only the capacitor 14 array extracted.

  Enlarging the cross-sectional shape of the capacitor 14 will be described with reference to dimensions a, b, c, and d in FIG. When it is intended to increase the size of each capacitor 14 while the arrangement of the capacitors 14 itself is constant, it is theoretically possible to increase the two parameters a and b. However, if only a is lengthened and a / b becomes extremely large, it is difficult to process the capacitor 14. Therefore, when the shape of the capacitor 14 is increased, both a and b need to be increased.

  On the other hand, the thickness of the interlayer insulating film 10 separating the adjacent capacitors 14 must be a certain value or more so that the adjacent capacitors 14 do not affect each other as capacitors. When both a and b are increased, the thickness of the interlayer insulating film 10 becomes a problem first, not d but d. Since the distance of d must be kept to a certain extent, there is a limit to the range in which a can be expanded. Eventually, a dead space 15 is formed at a position surrounded by the four capacitors 14 as shown in FIG.

  Accordingly, an object of the present invention is to provide a semiconductor device that can reduce the dead space in the capacitor arrangement as much as possible and expand the shape of each capacitor as much as possible.

  In order to achieve the above object, a semiconductor device according to the present invention includes a semiconductor substrate having a main surface, and a first transfer gate and a second transfer gate formed on the main surface and extending linearly adjacent to each other. And a first storage node contact and a first storage node contact each of which is arranged in a gap between the first transfer gate and the second transfer gate and is electrically connected to the main surface and extending upward. A second storage node contact; a first electrode connected to an upper surface of the first storage node contact; and a second electrode disposed opposite to the first electrode with an insulating film interposed therebetween. 1 capacitor, a third electrode connected to the upper surface of the second storage node contact, and an insulating film for the third electrode And a second capacitor composed of a fourth electrode disposed opposite to the first storage node contact in a part of the first electrode on the first transfer gate side in plan view. The upper surface is connected, and the upper surface of the second storage node contact is connected to only a part of the third electrode on the second transfer gate side.

It is a top view of the memory cell part of the semiconductor device in Embodiment 1 based on this invention. It is arrow sectional drawing regarding the II-II line | wire in FIG. It is explanatory drawing of the arrangement | sequence of the capacitor of the semiconductor device in Embodiment 1 based on this invention. It is sectional drawing of the memory cell part of the semiconductor device in Embodiment 2 based on this invention. It is explanatory drawing of the 1st process of the manufacturing method of the semiconductor device in Embodiment 3 based on this invention. It is explanatory drawing of the 2nd process of the manufacturing method of the semiconductor device in Embodiment 3 based on this invention. It is explanatory drawing of the 3rd process of the manufacturing method of the semiconductor device in Embodiment 3 based on this invention. It is explanatory drawing of the plate-making mask pattern used with the manufacturing method of the semiconductor device in Embodiment 3 based on this invention. It is explanatory drawing of the 4th process of the manufacturing method of the semiconductor device in Embodiment 3 based on this invention. It is explanatory drawing of the 5th process of the manufacturing method of the semiconductor device in Embodiment 3 based on this invention. It is a top view of the memory cell part of the semiconductor device based on a prior art. It is arrow sectional drawing regarding the XII-XII line | wire in FIG. It is arrow sectional drawing regarding the XIII-XIII line | wire in FIG. It is explanatory drawing of the arrangement | sequence of the capacitor of the semiconductor device based on a prior art.

(Embodiment 1)
(Constitution)
A semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a plan view of a memory cell portion of this semiconductor device. However, in order to explain the positional relationship between the respective parts, it is shown that the interlayer insulating film that originally fills the gaps between the respective parts is assumed to be transparent. FIG. 2 shows a cross-sectional view taken along the center line of the capacitor 14 in FIG. 1, that is, a cross-sectional view taken along the line II-II. The configuration of the semiconductor substrate 1, the transfer gate 2, the interlayer insulating films 3, 5, 8, the lower layer contact 4b, and the storage node contact 9 is the same as the corresponding part of the conventional semiconductor device described with reference to FIG. A cross-sectional view taken along the center line of the bit line 6 in FIG. 1 is the same as that shown in FIG.

  The structure of each capacitor 14 is also a concave capacitor and is the same as that described for the conventional semiconductor device, and therefore description thereof will not be repeated. The same is true in that the storage node 11 is electrically connected to the lower layer contact 4b by the storage node contact 9.

  However, as can be seen from a comparison between FIGS. 1 and 11, this semiconductor device is different from the conventional semiconductor device in terms of the cross-sectional shape of each capacitor 14 and the positional relationship between the capacitor 14 and the storage node contact 9. ing.

  In the semiconductor device according to the present embodiment, the cross-sectional shape of the capacitor 14 is not substantially the shape shown in FIG. The major axis of the substantially elliptical shape is a direction perpendicular to the longitudinal direction of the transfer gate 2.

  Further, in this semiconductor device, the capacitors 14 are arranged in a substantially elliptical long axis direction (left and right direction in FIG. 1) with a plurality of capacitors 14 having a width corresponding to one transfer gate 2 and the transfer gates. Capacitor rows arranged at equal intervals are formed at a pitch substantially equivalent to twice the sum of the widths of one gap formed by each other. When any one capacitor row is focused on as the first capacitor row, the second capacitor row, which is the other capacitor row, is arranged adjacently in parallel, and the first capacitor row, the second capacitor row, Then, the phase in which the capacitors 14 are arranged is shifted by a distance substantially corresponding to the sum of the width of one transfer gate 2 and the width of one gap formed between the transfer gates 2. Even if the capacitor 14 is arranged in this way, the arrangement of the storage node contacts 9 is the same as the conventional one. As a result, as shown in FIGS. 1 and 2, the center of the storage node contact 9 and the center of the capacitor 14 are shifted in the major axis direction of a substantially elliptical shape. In addition, when the capacitor rows are viewed in order along the longitudinal direction of the transfer gate 2 (vertical direction in FIG. 1), the center of the capacitor 14 is alternately shifted in the opposite direction. It has become.

  Therefore, when attention is paid to the storage node contacts 9 that are electrically connected to the upper surfaces of the respective lower layer contacts 4b arranged in any one gap sandwiched between the transfer gates 2, the storage node contacts 9 are alternately opposed to each other when viewed from above. It can be said that the capacitor 14 is overlapped so that the center of the substantially elliptical shape is shifted to the side.

  FIG. 3 shows only the capacitor 14 array extracted from FIG. Capacitor 14 is substantially elliptical as described above, and is arranged in such a manner that it is alternately shifted by one column as described above. Therefore, when any one capacitor is noted as a specific capacitor, It can be said that the capacitor adjacent to the major axis in the diagonal direction is closest to the specific capacitor. That is, L is the closest point to C and D in FIG.

(Action / Effect)
When the ellipse is to be enlarged by arranging the capacitors 14 not in a simple square shape but shifted by one column as described above, it is assumed that the major axis and minor axis of the ellipse are extended simultaneously. However, the portion where the short axis extends corresponds to the gap between the capacitors in the adjacent capacitor rows. Therefore, the short axis can be extended and a large ellipse can be secured. In this case, the distance between the capacitors adjacent in the oblique direction, that is, the distance L in FIG. 3, need not be less than the minimum value of the interlayer insulating film necessary between the capacitors. According to this, it is possible to obtain a capacitor having a larger cross-sectional shape than the conventional one. In addition, the dead space can be further reduced as compared with the conventional case.

  In general, there are a COB (Capacitor On Bit-Line) system and a CUB (Capacitor Under Bit-Line) system in the arrangement relationship between capacitors and bit lines. In the semiconductor device according to the present embodiment, a COB method in which the capacitor 14 is stacked on the bit line 6 is employed. Conversely, in the case of the CUB method in which the bit line is stacked above the capacitor, the bit line contact to be connected from the bit line to the lower layer contact passes through the gap of the capacitor and is connected to the lower layer contact. There was a need. In the case of capacitors arranged in a square pattern as in the prior art, the gap between the capacitors was wide, so it was easy to design the bit line contact to pass between the capacitors using the CUB method. In the semiconductor device of this embodiment, the gap between the capacitors becomes narrow, which is disadvantageous when the CUB method is adopted. However, in the COB method, there is no such problem, and the arrangement of capacitors can be determined. Therefore, it is more preferable to adopt the present invention in the COB method.

(Embodiment 2)
(Constitution)
A semiconductor device according to the second embodiment of the present invention will be described. In the semiconductor device of the first embodiment, the capacitor 14 is a concave capacitor. On the other hand, in the semiconductor device according to the present embodiment, the capacitor 14a is a convex capacitor. The plan view is the same as FIG. FIG. 4 shows a cross-sectional view taken along a cross-section corresponding to FIG. The capacitor 14a has a substantially elliptical cross-sectional shape when cut along a horizontal plane, and has a solid substantially elliptical column shape. The interior is filled with a conductor and serves as a storage node 11a. The outer surface of the storage node 11a is covered with a cell plate cylindrical portion 12a via an insulating film (not shown). The storage node 11a and the cell plate cylindrical portion 12a thus face each other through the insulating film to constitute a capacitor. The cell plate cylindrical portion 12 a is connected to the cell plate upper surface portion 13. The storage node 11a and the storage node contact 9 are electrically connected. The cell plate cylindrical portion 12a and the storage node contact 9 are insulated.

  The constituent elements other than that the capacitor is changed from the concave capacitor to the convex capacitor are the same as those in the first embodiment.

(Action / Effect)
Also in the present embodiment, the same effect as in the first embodiment can be obtained.

(Embodiment 3)
(Production method)
A method for manufacturing a semiconductor device according to the third embodiment of the present invention will be described. This semiconductor device manufacturing method is a method for manufacturing the semiconductor device described in the first embodiment. First, the structure shown in FIG. 5 is formed by a known technique. An interlayer insulating film 10 is laminated on this upper surface to obtain the structure shown in FIG. As shown in FIG. 7, a resist 16 is applied to the entire upper surface, and photolithography is performed using a plate-making mask pattern. At this time, as the plate-making mask pattern, an elliptical array pattern as shown in FIG. 3 is used. However, when it is difficult to create an elliptical shape corresponding to each capacitor as a plate-making mask pattern, a cross shape as shown in FIG. 8 may be used instead of the elliptical shape. When setting the cross shape, the parameters p, q, r, and s shown in FIG. 8 are optimized and set appropriately by simulation or the like. Plate making is performed using such a plate making mask pattern to form a resist pattern 18 from the resist 16. This state is shown in FIG. Using the resist pattern 18 as a mask, the interlayer insulating film 10 is etched to reach the state shown in FIG. Thereafter, the resist pattern 18 is removed, and further, the storage node 11, the insulating film, and the cell plate cylindrical portion 12 are sequentially laminated on the inner surface of the concave portion of the interlayer insulating film 10, thereby completing the capacitor 14. FIG. The semiconductor device shown can be obtained.

(Action / Effect)
As described above, the semiconductor device described in the first embodiment based on the present invention can be manufactured only by changing the plate-making mask pattern as compared with the case of manufacturing a conventional semiconductor device. In addition, the cross-sectional shape of each capacitor is aimed to be a substantially elliptical shape, but the shape provided in the plate-making mask pattern is not necessarily an elliptical shape, even if it is a cross-shaped shape, A substantially elliptical resist pattern can be formed by blurring of exposure during photoengraving. Therefore, even if a plate-making mask pattern of a curved figure cannot be created, the plate-making mask pattern can be configured with only straight lines.

  In addition, the said embodiment disclosed this time is an illustration in all the points, Comprising: It is not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and includes all modifications within the scope and meaning equivalent to the terms of the claims.

  DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 2 Transfer gate, 3 1st interlayer insulation film, 4a, 4b Lower layer contact, 5 2nd interlayer insulation film, 6 bit line, 7 bit line contact, 8 3rd interlayer insulation film, 9 Storage node Contact, 10th interlayer insulating film, 11, 11a storage node, 12, 12a cell plate cylindrical portion, 13 cell plate upper surface portion, 14 capacitor, 15 dead space, 16 resist, 18 resist pattern.

Claims (5)

A semiconductor substrate having a main surface;
A first transfer gate and a second transfer gate formed on the main surface and extending linearly adjacent to each other;
A first storage node contact and a second storage which are arranged in a gap between the first transfer gate and the second transfer gate and are electrically connected to the main surface and are each formed of a rod-shaped conductor extending upward. Node contacts,
A first capacitor comprising a first electrode connected to an upper surface of the first storage node contact and a second electrode disposed opposite to the first electrode with an insulating film interposed therebetween;
A second capacitor comprising a third electrode connected to the upper surface of the second storage node contact and a fourth electrode disposed opposite to the third electrode with an insulating film interposed therebetween;
In plan view, the upper surface of the first storage node contact is connected to only a part of the first electrode on the first transfer gate side, and only a part of the third electrode on the second transfer gate side is A semiconductor device to which an upper surface of a second storage node contact is connected.   2. The planar storage device according to claim 1, wherein the first storage node contact and the second storage node contact adjacent to the first storage node contact are arranged in a direction in which the first transfer gate extends. Semiconductor device. A gap between the first transfer gate and the second transfer gate, further comprising a third storage node contact made of a rod-shaped conductor electrically connected to the main surface and extending upward;
3. The semiconductor according to claim 1, wherein the first storage node contact, the second storage node contact, and the third storage node contact are arranged side by side in an extending direction of the first transfer gate in a plan view. apparatus. A third capacitor comprising a fifth electrode connected to an upper surface of the third storage node contact and a sixth electrode disposed opposite to the fifth electrode with an insulating film interposed therebetween;
4. The semiconductor device according to claim 3, wherein an upper surface of the third storage node contact is connected to only a part of the fifth electrode on the first transfer gate side in a plan view.   Conductive so as to be electrically connected to the main surface in the gap between the first transfer gate and the second transfer gate, respectively connected to the lower surfaces of the first storage node contact and the second storage node contact. The semiconductor device according to claim 1, further comprising a first lower layer contact and a second lower layer contact each formed of a body.

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