KR101087777B1 - Capacitor of semiconductor device and manufacturing method of the same - Google Patents

Abstract

In the capacitor of the semiconductor device according to the embodiment of the present invention, each storage node is formed in a multilayer structure having a different cross-sectional area, but adjacent storage nodes are formed so that their shapes are opposite to each other, so that the capacitance of the capacitor and the integration degree of the semiconductor device are the same. Maintaining sufficient distance between capacitors while maintaining them increases process margins.

Description

Capacitor of semiconductor device and manufacturing method therefor {Capacitor of semiconductor device and manufacturing method of the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor of a semiconductor device, and more particularly, to a capacitor having a storage electrode having a stacked type of electrode material layers having different sizes, and a method of manufacturing the same.

BACKGROUND With the continuous development of semiconductor manufacturing process technology, semiconductor devices are shrinking in size and density of semiconductor devices integrated per unit area is increasing. Accordingly, the area occupied by the cell capacitor for storing data in the DRAM is gradually reduced, and various techniques for obtaining a high capacity capacitor have been proposed.

The capacitor is a structure in which a dielectric film is interposed between capacitor electrodes, called storage nodes and plate electrodes, whose capacitance is proportional to the surface area of the electrode and the dielectric constant of the dielectric film and inversely proportional to the spacing between the electrodes. Therefore, in order to obtain a high capacity capacitor, it is essential to use a dielectric film having a high dielectric constant, to enlarge the surface area of the electrode, or to reduce the distance between the electrodes.

However, since it is limited to reduce the distance between electrodes, that is, the thickness of the dielectric film, researches for manufacturing a high capacity capacitor have been conducted by using a dielectric film having a high dielectric constant or increasing the surface area of the electrode.

As a method of increasing the surface area of an electrode, a method of forming a cell capacitor in a three-dimensional structure rather than a conventional planar capacitor is used. As a three-dimensional structure capacitor, a trench capacitor and a stack are formed. Stacked capacitors are mainly used.

However, in the case of a three-dimensional capacitor, as the area occupied by the capacitor is gradually reduced, the pitch between the capacitors is gradually reduced, which makes it difficult to secure a process margin.

1A and 1B are plan and cross-sectional views, respectively, of stacked cell capacitors formed in a conventional cell array region.

In stackable capacitor structure, capacitance is advantageous as the storage node's diameter (section area) (①) increases, and the distance between storage nodes is increased in order to increase the stability of the process such as node separation, upper electrode formation, and improved solution by removing peaks. The larger (②) is, the better.

However, as semiconductor devices are highly integrated, it is difficult to secure margins for the diameters of the storage nodes and the distances between the storage nodes, which causes short circuits between adjacent capacitors.

The present invention is to improve the structure of the capacitor to secure a sufficient distance between the capacitors to increase the process margin to prevent short between adjacent capacitors.

A capacitor of a semiconductor device according to an embodiment of the present invention includes a storage node in which a plurality of pillar-shaped electrode material layers having different sizes are stacked, a dielectric layer formed on the storage node, and a plate electrode formed on the dielectric layer. It may include.

In this case, the storage node has a lower storage node having a first cross-sectional area and a second cross-sectional area, and includes an upper storage node integrally stacked on the lower storage node, and the lower storage node and the upper storage node have different heights. It can have

A capacitor of a semiconductor device according to another embodiment of the present invention may include a first storage node in which a first lower storage node having a first size and a first upper storage node having a second size are stacked and adjacent to the first storage node. A second storage node in which the second lower storage node having the second size and the second upper storage node having the first size are stacked, a dielectric film formed on the first storage node and the second storage node, and the dielectric It may include a plate electrode formed on the film.

In this case, the first lower storage node and the second lower storage node may be formed on the same layer and have different cross-sectional areas and heights. The first lower storage node and the second upper storage node may have the same cross-sectional area and height, and the first upper storage node and the second lower storage node may have the same cross-sectional area and height.

As such, in the present invention, each storage node is formed in a multi-layered structure having a different cross-sectional area, but adjacent storage nodes have opposite shapes, thereby increasing the distance between the capacitors while maintaining the capacitance and the density of each capacitor the same. You can.

In a method of manufacturing a capacitor of a semiconductor device according to an embodiment of the present invention, a first step of forming a lower storage node having a first size on a storage node contact plug, and an upper storage node having a second size on the lower storage node The method may include forming a dielectric film on the lower storage node and the upper storage node, and forming a plate electrode on the dielectric film.

In this case, the first step may include forming a first sacrificial insulating layer on the storage node contact plug, and selectively etching the first sacrificial insulating layer until the storage node contact plug is exposed to lower storage node contacts having a first cross-sectional area. The method may include forming a hole and forming a lower electrode material layer to fill the lower storage node contact hole.

The second step may include forming a second sacrificial insulating layer on the lower storage node, and selectively etching the second sacrificial insulating layer until the lower storage node is exposed, thereby forming an upper storage node contact hole having a second cross-sectional area. And forming an upper electrode material layer to fill the upper storage node contact hole.

The lower storage node contact hole and the upper storage node contact hole may be formed at different depths.

According to another aspect of the present invention, there is provided a method of manufacturing a capacitor of a semiconductor device, the method comprising: forming a first lower storage node having a first size and a second lower storage node having a second size on a storage node contact plug; A second step of forming a first upper storage node having the second size on the first lower storage node and a second upper storage node having the first size on the second lower storage node, the first lower storage And a third step of forming a dielectric film on the node, the second lower storage node, the first upper storage node, and the second upper storage node, and a fourth step of forming a plate electrode on the dielectric film. .

The first step may include forming a first sacrificial insulating layer on the storage node contact plug, and selectively etching the first sacrificial insulating layer until the storage node contact plug is exposed to form a first lower storage node contact having a first cross-sectional area. Forming a second lower storage node contact hole having a hole and a second cross-sectional area, forming a lower electrode material layer to fill the first lower storage node contact hole and the second lower storage node contact hole; And etching the lower electrode material layer such that the first lower storage node and the second lower storage node have different heights. In this case, the lower electrode material layer may be formed through an ALD method and may be etched through an etchback method.

The second step includes forming a second sacrificial insulating layer on the first lower storage node and the second lower storage node, and the second sacrificial layer until the first lower storage node and the second lower storage node are exposed. The insulating layer is selectively etched to form a first upper storage node contact hole having the second cross-sectional area on the first lower storage node, and to form a second upper storage node contact hole having the first cross-sectional area on the second lower storage node. And forming an upper electrode material layer to fill the first upper storage node contact hole and the second upper storage node contact hole. In this case, the first upper storage node contact hole may be etched by the height of the second lower storage node, and the second upper storage node contact hole may be etched by the height of the first lower storage node.

The present invention improves the structure of the capacitors arranged in the cell region, thereby increasing the process margin by further increasing the distance between the capacitors while maintaining the same capacitance and density of the capacitors.

1A and 1B are plan and cross-sectional views, respectively, of stacked cell capacitors formed in a conventional cell array region.
2 is a view illustrating a structure of a capacitor according to an embodiment of the present invention.
3 to 10 are cross-sectional views illustrating a method of manufacturing the capacitor of FIG. 2 according to the present embodiment.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

2 is a view showing the structure of a capacitor according to an embodiment of the invention, Figure 2a is a cross-sectional view taken along the line A-B of Figure 2b and A'-B 'of FIG.

The storage nodes 110 and 120 of the stacked structure are formed on the storage node contact plugs (not shown), and the dielectric layer 130 and the plate electrode 140 are formed thereon.

In this case, the storage nodes 110 and 120 in the present embodiment are not formed in a single columnar shape having the same cross-sectional area as a whole, and a plurality of electrodes (two in this embodiment) in the form of a column having different cross-sectional areas and heights. The material layers are formed in a multilayer structure in which they are integrally stacked. That is, as shown in FIG. 2A, the storage nodes 110 and 120 of each capacitor have a structure in which lower storage nodes 110a and 120a and upper storage nodes 110b and 120b having different sizes are stacked. do.

Furthermore, in the present embodiment, the cross-sectional areas of the adjacent storage nodes are differently formed in the storage nodes formed on the same layer to secure the distance between adjacent capacitors, that is, the process margin. That is, as shown in FIG. 2B, the cross-sectional area of the lower storage node 110a and the lower storage nodes 120a adjacent thereto are different from each other, and likewise, the upper storage node 120a and the upper storage nodes adjacent thereto as shown in FIG. 2C. The cross-sectional areas of the 120b are formed differently. At this time, the size of the adjacent storage nodes in each layer has the same technology as in the conventional (FIG. 1), and the distance between adjacent capacitors is increased as much as possible compared to the conventional one while the capacitance of each capacitor (surface area of each storage node) remains the same as before. It can be adjusted appropriately within the range that can be made.

In addition, in the present embodiment, the lower storage nodes 110a and 120a and the upper storage nodes 110b and 120b contact each other by forming different heights of adjacent lower storage nodes 110a and 120a, that is, storage nodes having different cross-sectional areas. The adjacent capacitors are prevented from shorting to each other at the portion where they are made. At this time, the lower storage node 120a having a smaller size is formed higher than the lower storage node 110a having a large size.

Furthermore, in the present embodiment, the lower storage node 110a and the upper storage node 120b have the same size, and the lower storage node 110b and the upper storage node 120a have the same size, thereby contiguous storage nodes 110, The surface area of 120 is formed so that the capacitances of adjacent capacitors are substantially the same.

As such, the present invention forms each storage node in a multi-layered structure having a different cross-sectional area, but the adjacent storage nodes are inverted so that their shapes are opposite to each other, so that the capacitance and the density of each capacitor are kept the same, while maintaining the same capacitance between the capacitors. It is possible to increase the distance of. In addition, since the storage node is formed by dividing it in the height direction, higher capacitors can be manufactured.

3 to 10 are process cross-sectional views illustrating a method of manufacturing the capacitor of FIG. 2 according to the present embodiment.

Referring to FIG. 3, an interlayer insulating layer 103 including a storage node contact plug 101 is formed on a semiconductor substrate on which a junction region (not shown) is formed.

Subsequently, a first sacrificial insulating film 105 is formed on the interlayer insulating film 103. In this case, the first sacrificial insulating layer 105 is formed by the height of the lower storage node 120a having a small cross-sectional area.

An etch stop film (not shown) may be formed between the interlayer insulating film 103 and the first sacrificial insulating film 105.

Next, referring to FIG. 4, after forming a photoresist film (not shown) on the first sacrificial insulating film 105, the upper portion of the first sacrificial insulating film 105 is formed through a lithography process using a first mask defining a lower storage node region. A lower storage node pattern (not shown) is formed on the substrate.

Subsequently, the lower storage node contact holes 107a and 107b are formed by etching the first sacrificial insulating layer 105 until the storage node contact plug 101 is exposed using the lower storage node pattern as an etching mask. In this case, the cross-sectional areas of the adjacent contact holes 107a and 107b are formed differently within the range in which the distance between the adjacent contact holes 107a and 107b can be sufficiently secured.

Next, referring to FIG. 5, a lower electrode material layer 109 is formed on the first sacrificial insulating layer 105 to fill the contact holes 107a and 107b. At this time, the lower electrode material layer 109 is, for example, polysilicon, Pt, Ru, Ir, PtO ₂ , IrO ₂ , (Sr, Ru) O, (Ba, Sr, Ru) O, (La, Sr) Co and these It can be formed of any one of the combinations.

In the present exemplary embodiment, the lower electrode material layer 109 is formed by an automatic layer deposition (ALD) method. Therefore, the gap fill in the small contact hole 107b proceeds faster than the gap fill in the large contact hole 107a, so that the gap fill rises over the contact hole 107b as shown in FIG. The amount of the lower electrode material coming up is increased while the amount of the lower electrode material coming up over the contact hole 107a becomes small.

Next, referring to FIG. 6, the lower storage nodes 110a and 120a are formed by performing etchback on the lower electrode material layer 109 in a bent state as shown in FIG. 5.

When the etch back process is performed, the electrode material layer of the contact hole 107a is deeply etched by the bending of the lower electrode material layer 109, so that the heights of the lower storage nodes 110a and 120a are different from each other. That is, the lower storage node 120a formed in the small contact hole 107b is formed higher than the lower storage node 110a formed in the large contact hole 107a.

The reason for differently forming the heights of the lower storage nodes 110a and 120a is that the distance between the lower storage node and the contact portion of the upper storage node between adjacent storage nodes 110 and 120 when forming the upper storage node in a subsequent process is different. This is to ensure sufficient.

Next, referring to FIG. 7, a second sacrificial insulating layer 121 is formed on the first sacrificial insulating layer 105 and the lower storage nodes 110a and 120a. In this case, the height of the second sacrificial insulating layer 121 is formed such that the heights of the upper storage node contact holes 123a and 123b to be formed in a subsequent process are equal to the lower storage nodes 120a and 110a, respectively.

Next, referring to FIG. 8, after forming a photoresist film (not shown) on the second sacrificial insulating film 121, the upper portion of the second sacrificial insulating film 121 is formed through a lithography process using a second mask defining an upper storage node region. An upper storage node pattern (not shown) is formed.

Next, the upper storage node contact holes 123a and 123b are formed by selectively etching the second sacrificial insulating layer 121 until the lower storage nodes 110a and 12a are exposed using the upper storage node pattern as an etching mask. In this case, the cross-sectional areas of the adjacent contact holes 123a and 123b may be formed differently within a range in which a distance between the adjacent contact holes 123a and 123b can be sufficiently secured. In the present exemplary embodiment, the cross-sectional area of the contact hole 123a formed in the upper portion of the lower storage node 110a having a large cross-sectional area is formed to be small, and conversely, the contact hole formed in the upper portion of the lower storage node 120a having a small cross-sectional area ( The cross-sectional area of 123b) is large. In this case, the cross-sectional area of the upper storage node contact hole 123a may be formed to be the same as that of the lower storage node contact hole 107b, and the cross-sectional area of the upper storage node contact hole 123b may be the lower storage node contact hole 107a. It can be formed equal to the cross-sectional area of.

Next, referring to FIG. 9, an upper electrode material layer (not shown) is formed on the second sacrificial insulating layer 121 to fill the upper storage node contact holes 123a and 123b. Subsequently, the upper storage material layers 110b and 120b which are integrally connected to the lower storage nodes 110a and 120a are formed by planarizing the upper electrode material layer (eg, CMP) until the second sacrificial insulating layer 121 is exposed. In this case, since the lower storage node 110a is formed lower than the lower storage node 120a in FIG. 6, the upper storage node 110b formed on the lower storage node 110a is disposed on the lower storage node 120a. It is formed longer than the formed upper storage node (120b), the length is formed to be the same as the lower storage node (120a). That is, the upper storage node 110b is formed at the same height as the lower storage node 120a and the upper storage node 120b is formed at the same height as the lower storage node 110a. Thus, the surface areas of adjacent storage nodes 110 and 120 become substantially the same, so that the capacitance of the finally formed capacitors is uniform.

The upper electrode material layer may be formed of the same material as the lower electrode material layer 109.

Next, referring to FIG. 10, the second sacrificial insulating film 121 and the first sacrificial insulating film 105 are performed by performing a dip out process on the first sacrificial insulating film 105 and the second sacrificial insulating film 121. Remove sequentially.

Subsequently, a capacitor is formed by forming the dielectric film 130 on the storage nodes 110 and 120 and the plate electrode 140 on the dielectric film 130. In this case, the process of forming the dielectric film 130 and the plate electrode 140 on the storage nodes 110 and 120 is performed in the same manner as in the prior art.

Embodiment of the present invention described above is for the purpose of illustration, those skilled in the art will be capable of various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

For example, in the above-described embodiment, only a case of forming a storage node having a two-stage structure has been described. However, the storage node may be divided into three or more tiers according to the height of the storage node. At this time, it is easy for those skilled in the art that such a manufacturing process can be performed by selectively repeating the above-described process, so a description thereof is omitted.

101: storage node contact plug 103: interlayer insulating film
105: first sacrificial insulating films 107a and 107b: lower storage node contact holes
109: lower electrode material layer 110a, 120a: lower storage node
110b and 120b: upper storage node 121: second sacrificial insulating layer
123a, 123b: Upper Storage Node Contact Hole
130 dielectric film 140 plate electrode

Claims (20)

delete delete delete delete A first storage node stacked with a first lower storage node having a first size and a first upper storage node having a second size;
A second storage node adjacent to the first storage node, wherein a second lower storage node having the second size and a second upper storage node having the first size are stacked;
A dielectric film formed on the first storage node and the second storage node; And
And a plate electrode formed on the dielectric film. Claim 6 was abandoned when the registration fee was paid. 6. The method of claim 5,
And the first lower storage node and the second lower storage node are formed on the same layer and have different cross-sectional areas and heights. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 5, wherein the first lower storage node
And the same cross-sectional area and height as the second upper storage node. Claim 8 was abandoned when the registration fee was paid. The method of claim 5, wherein the first upper storage node
And the same cross-sectional area and height as the second lower storage node. delete delete delete delete delete Forming a first lower storage node having a first size and a second lower storage node having a second size on the storage node contact plug;
Forming a first upper storage node having the second size on the first lower storage node, and forming a second upper storage node having the first size on the second lower storage node;
Forming a dielectric layer on the first lower storage node, the second lower storage node, the first upper storage node, and the second upper storage node; And
And forming a plate electrode on the dielectric film. Claim 15 was abandoned upon payment of a registration fee. 15. The method of claim 14, wherein the first step is
Forming a first sacrificial insulating layer on the storage node contact plug;
Selectively etching the first sacrificial insulating layer until the storage node contact plug is exposed to form a first lower storage node contact hole having a first cross-sectional area and a second lower storage node contact hole having a second cross-sectional area;
Forming a lower electrode material layer to fill the first lower storage node contact hole and the second lower storage node contact hole; And
And etching the lower electrode material layer so that the first lower storage node and the second lower storage node have different heights. Claim 16 was abandoned upon payment of a setup registration fee. The method of claim 15, wherein the forming of the lower electrode material layer is performed.
Monolayer deposition (ALD: Automatic Layer Deposition) is a method for manufacturing a capacitor of a semiconductor device, characterized in that used. Claim 17 has been abandoned due to the setting registration fee. The method of claim 16, wherein etching the lower electrode material layer comprises:
A method for manufacturing a capacitor of a semiconductor device, characterized by using an etchback method. Claim 18 was abandoned upon payment of a set-up fee. The method of claim 15 wherein the second step is
Forming a second sacrificial insulating layer on the first lower storage node and the second lower storage node;
Selectively etching the second sacrificial insulating layer until the first lower storage node and the second lower storage node are exposed to form a first upper storage node contact hole having the second cross-sectional area on the first lower storage node; Forming a second upper storage node contact hole having the first cross-sectional area on the second lower storage node; And
And forming an upper electrode material layer to fill the first upper storage node contact hole and the second upper storage node contact hole. Claim 19 was abandoned upon payment of a registration fee. 19. The method of claim 18, wherein the first upper storage node contact hole is
And etching the substrate by the height of the second lower storage node. Claim 20 was abandoned upon payment of a registration fee. 19. The method of claim 18, wherein the second upper storage node contact hole is
And etching the substrate by the height of the first lower storage node.

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