KR20010003628A - Semiconductor memory cell structure and method of fabricating the same - Google Patents

Abstract

PURPOSE: A semiconductor memory cell structure and a method for manufacturing the same are to arrange a bit line contact and a capacitor contact on an active region of a memory cell by inclining the active region in a slash type. CONSTITUTION: A slash type active regions(1) is arranged in the same interval on a semiconductor substrate. A device isolation region surrounds the active region. A word line(2) crosses the active region and the device isolation region in turn. A first interlayer dielectric is formed on the whole surface of the semiconductor substrate including the word line. A bit line contacts(3) is arranged between the word lines, and is formed on the first interlayer dielectric to expose the center of the active region. A bit lines(4) is electrically connected to the active region via the bit line contact, and is arranged in the direction perpendicular to the word line. A second interlayer dielectric is formed on the whole surface of the semiconductor substrate including the bit line. A storage contact(5) is arranged between the word line and the bit line, and is formed on the first and second interlayer dielectrics to exposure the active region.

Description

Semiconductor memory cell structure and method of fabricating the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory cell structure and a method of manufacturing the same, and more particularly, to a semiconductor memory cell structure in which the bit line contact and the capacitor contact are disposed on the active area by tilting the active area of the memory cell in a slash type. It relates to a manufacturing method thereof.

DRAM memory cell structure design is the basis for determining the density, operation method, process method, and order of DRAM, and is one of the most important factors in DRAM fabrication.

The memory cell structure of a DRAM can be classified into two types, an open bit line type and a folded bit line type, according to an operation method. In the case of the open bit line type, the cell density is high, but since a bit line bar signal must be pulled from another cell block, there is a high possibility of malfunction due to the coupling noise difference between word lines. In the case of the folded bit line type, the degree of integration decreases slightly, but since the bit line bar signal can be used in the same cell block, the coupling noise with the word line is received to the same degree, and thus there is little possibility of malfunction. Therefore, a folded bit line type in which a cell operates stably is mainly used as a memory cell structure of a DRAM.

The general form of the folded bit line type memory cell structure which has been mainly used in the related art is shown in FIG. Looking at the schematic manufacturing method with reference to Figure 1 as follows. First, by using a lithography and etching process, the active area 1 of a rectangular type (bar type) is regularly patterned parallel to the bottom and side surfaces as shown in FIG. 1 to expose the surface of the silicon substrate. At this time, all around the active area is insulated with an oxide film.

Next, word line manufacturing is performed to form a word line 2 in a straight line in the direction perpendicular to the long axis of the rectangular active region 1. At this time, one active region and two word lines intersect, and two word lines alternately intersect with the active region and are arranged as shown in FIG. 1 repeatedly. Therefore, all active regions are divided into three parts by two word lines. The left and right sides are the source regions, and the storage node is connected to the capacitor, and the center portion is the common drain region for writing or reading signals to both sources. The bit line contact 3 is positioned.

Next, the space between the formed word lines is filled with an oxide film or the like to be planarized to form a straight bit line 4. At this time, the bit line is perpendicular to the word line 2 and must form a contact with the drain portion of the active region. However, since the direction of the major axis of the active region and the direction of the bit line are parallel to each other, when a bit line contact is made directly on the active region and a bit line is formed thereon, a space for forming a storage node in the source region cannot be secured. Therefore, in order to make a bit line and at the same time to secure a space for a storage node, as shown in FIG. In this case, a series of processes including a separate mask step is required to extend the bit line contact to the bottom of the active region, which is called a plugging process. Therefore, in order to form a bit line, a plug is formed outside the active region, and then a bit line contact is formed on the plug to form a bit line according to the contact position.

Finally, the space between the formed bit lines is filled with an oxide film or the like, and then planarized, a storage node contact 5 is formed in the source region, and a storage node is formed at the contact position to manufacture a capacitor.

The folded bit line type cell, which is mainly used today, has the advantage of good transistor characteristics because of its symmetrical structure. However, as can be seen in the above-described manufacturing method, since the active region is located parallel to the bit line and neither the bit line contact nor the storage node contact can be directly connected to the active region, the bit line contact region is connected to the non-active region through the plugging process. There is a disadvantage that must be secured separately.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and a semiconductor memory cell structure capable of inclining an active region of a memory cell in a slash type so that both a bit line contact and a capacitor contact are disposed on the active region, and fabrication thereof Its purpose is to provide a method.

The semiconductor memory cell structure of the present invention for achieving the above object is a semiconductor substrate, the diagonal active region of the shape arranged at equal intervals on the semiconductor substrate, the device isolation region surrounding the active region, the active region and device isolation A word line of a transistor alternately over an area, a first interlayer insulating film formed on the front surface of the semiconductor substrate including the word line, and positioned between the word lines and exposing a central region of the active region; A second interlayer insulating layer formed on the front surface of the semiconductor substrate including the bit line contact, a bit line electrically connected to the active region through the bit line contact, and disposed in a direction perpendicular to the word line; A neck disposed between the word line and the bit line to expose the active area; With the first and second storage node contacts are formed in the interlayer insulating film, and is electrically connected to the active region via the storage node contact it is configured to include a capacitor arranged at equal intervals on the second interlayer insulating film. In the arrangement of the word line and the bit line, the word line and the bit line are intersected and uncrossed with the active region in pairs of two word lines when viewed on the one bit line line, and the two bit lines are viewed on one word line line. Repeat the intersection and non-crossing with the active area in pairs.

The semiconductor memory cell manufacturing method of the present invention for achieving the above object is to define a slanted diagonal active region disposed on the semiconductor substrate at equal intervals and the device isolation region surrounding it, and the active region and device isolation Forming a word line in a predetermined region on the region, forming an impurity region in a predetermined portion of the active region, forming a primary interlayer insulating film on the entire surface of the semiconductor substrate including the word line, and performing a photolithography process Forming a bit line contact on a predetermined portion of the first interlayer insulating film, forming a bit line electrically connected to the impurity region through the bit line contact, and forming a bit line contact on the entire surface of the semiconductor substrate including the bit line Forming a portion of the first and second interlayer dielectric layers through a photolithography process; Forming a de contact, and through the storage node contacts and forming a capacitor electrically connected to the impurity region.

1 is a schematic diagram of a conventional rectangular memory cell;

2 is a schematic diagram of an oblique memory cell according to the present invention;

3 is a view for explaining a folded bit line operation principle for a diagonal memory cell;

4A and 4B are diagrams illustrating unit cell sizes of a conventional rectangular memory cell and an oblique memory cell according to the present invention;

* Description of the symbols for the main parts of the drawings *

1.Active Area 2.Wordline

3.Bitline contact 4.Bitline

5.Storage Node Contact 6.Sense Amplifier

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

The diagonal memory cell structure according to the present invention is simplified and shown in FIG. 2. Since the manufacturing method of this cell structure is the same except for the plugging process in the conventional cell manufacturing method, the description thereof will be omitted. This means that the plugging process can be omitted. Specifically, the plugging process will be described with reference to FIG. 2.

First of all, the arrangement of each cell component is divided into three active regions by two word lines (2) passing through one diagonal active region (1). The node contact 5 is located. The central portion is a common drain region where the bit line contacts 3 for connecting with the bit lines are located. Compared with the conventional rectangular cell shown in FIG. 1, since the bitline contact and the storage node contact cannot be placed together in the active area, the bitline contact must be pulled out separately through the plug process to the area below the active area. However, it can be seen that the diagonal cell of the present invention can be directly contacted without a plugging process.

The manner in which the diagonal cell operates in the folded bit line type will be described with reference to FIG. 3. First, when looking at the contact types of the active region 1, the word line 2, the bit line 4, the word lines and the bit lines are alternately alternately crossed and uncrossed in the active region on the same line. Can be. Therefore, when the transistors are turned on when a signal is input to one word line as shown in FIG. 3, the signal is transmitted in the direction of the arrow on the active region, and the signal is alternately outputted and not outputted by two bit lines as indicated by the arrow on the bit line. By constructing the bit line bar, the sense amplifier 6 can be manufactured. Therefore, this cell structure satisfies the folded bit line format.

In the diagonal memory cell structure, the angle of the active region can be changed by changing the distance between the word line and the bit line, and the angle is preferably inclined by about 20 ° to 30 °. In addition, both ends of the active region may be rounded, or the area of the center portion may be made larger.

The word line and the bit line may also be formed in an uneven shape or a wave shape.

In FIG. 4, an oblique cell of the present invention is compared with an existing cell in terms of integration degree. 4A shows an existing cell, FIG. 4B shows a diagonal cell of the present invention, A represents an active region, and B represents an isolation region. In the calculation, the unit cell area of the repeating active region pattern was obtained using a minimum feature size as a. In this case, since both the existing cells and the diagonal cells have the same area as 16a ² , it can be seen that there is no loss in the degree of integration even when the cells are changed to the diagonal cells. On the other hand, in terms of the area ratio occupied by the active area to the unit cell size, it can be seen that the diagonal cell (44%) is 8% higher than the conventional cell (36%), which is excellent in the active area utilization. .

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

When the oblique cell of the present invention is applied to an actual process, the cell size and folded bit line format are satisfied compared to the existing cell design structure, and thus there is no performance deterioration in terms of density and reliability. Since the contact can be made, the process of making a contact in a region other than the active region can be omitted. As a result, it is possible to reduce a single mask process and a series of related processes in comparison with a conventional cell, thereby greatly reducing manufacturing costs.

Claims (14)

Semiconductor substrate, Diagonal active regions of a shape disposed on the semiconductor substrate at equal intervals; An isolation region surrounding the active region, A word line of the transistor alternately over the active region and the isolation region; A primary interlayer insulating film formed on the entire surface of the semiconductor substrate including the word line; A bit line contact disposed between the word lines and formed in the primary interlayer dielectric layer to expose a central region of the active region; A bit line electrically connected to the active region through the bit line contact and disposed in a direction perpendicular to the word line; A second interlayer insulating film formed on the entire surface of the semiconductor substrate including the bit line; A storage node contact disposed between the word line and the bit line and formed in the first and second interlayer dielectric layers for exposing the active region; And a capacitor electrically connected to the active region through the storage node contact and disposed at equal intervals on the secondary interlayer insulating layer. When viewed on the one bit line, two word lines intersect with and do not cross the active area in pairs. When viewed on one word line, the two bit lines intersect with the active area and do not cross. Repeated semiconductor memory cell structure. The method of claim 1, And an angle of the active region is changed by changing a distance between the word line and the bit line. The method of claim 1, A semiconductor memory cell structure in which the active region is inclined about 20 ° to 30 °. The method of claim 1, A semiconductor memory cell structure in which the active region is rounded at both ends. The method of claim 1, A semiconductor memory cell structure having a relatively large area of the central portion of the active region. The method of claim 1, A semiconductor memory cell structure in which the word line and the bit line have a concave-convex shape. The method of claim 1, A semiconductor memory cell structure in which the word line and the bit line have a wave shape. Defining an inclined diagonal active region arranged at equal intervals on the semiconductor substrate and an isolation region surrounding the same; Forming a word line in a predetermined region on the active region and the isolation region; Forming an impurity region in a predetermined portion of the active region, Forming a primary interlayer insulating film on the entire surface of the semiconductor substrate including the word line; Forming a bit line contact on a predetermined portion of the primary interlayer insulating film through a photolithography process; Forming a bit line electrically connected to the impurity region through the bit line contact; Forming a secondary interlayer insulating film on the entire surface of the semiconductor substrate including the bit line; Forming a storage node contact on a predetermined portion of the first and second interlayer insulating layers through a photolithography process; and Forming a capacitor electrically connected to the impurity region through the storage node contact. The method of claim 8, A method of manufacturing a semiconductor memory cell, wherein the active region is formed to be inclined by about 20 ° to 30 °. The method of claim 8, And forming the word line alternately over the active region and the device isolation region. The method of claim 8, And forming the bit line contact in a central region of an active region located between the word lines. The method of claim 8, And forming the bit line in a direction perpendicular to the word line. The method of claim 8, And forming the storage node contact in a portion of an active region located between the word line and the bit line. The method of claim 8, When viewed on the one bit line line, it crosses and crosses the active area in pairs of two word lines, and when viewed on one word line line, it crosses and does not cross the active area in pairs of two bit lines. A semiconductor memory cell manufacturing method for forming a bit line and a word line to repeat.