JPH08288471A - Dynamic semiconductor storage device - Google Patents

Abstract

PURPOSE: To provide a dynamic semiconductor storage device, which is applicable to the stacked cell provided by previously forming the bit lines, capable of increasing cell capacity and applicable to a high dielectric film, even two cells are arranged at the three intersections of word lines, improve the cell freeness, and permit the device to be applicable to the cell provided by forming the bit line later and to the trench cell. CONSTITUTION: A DRAM is composed of a memory cell array, which is formed by arranging two memory cells on every three intersections among the 18 intersections of a plurality of word lines 14 and a plurality of bit lines 18 in the work line direction and the bit line direction. The bit line 18 is arranged by inclining it from the direction that orthogonally intersects with the work line 14, and an active area 13 that connects the bit line contacts 15 and 17 of the memory cell with the storage node(SN) contact 19 is arranged by inclining the area 13 from the direction that orthogonally intersects with the word line 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic semiconductor memory device (DRAM), and more particularly, two memory cells are arranged at three intersections of a plurality of word lines and a plurality of bit lines. The DRAM.

[0002]

2. Description of the Related Art In recent years, DRAMs having a memory cell structure of 1 transistor / 1 capacitor have been highly integrated due to improvements in the memory cell structure and advances in fine processing technology. , Transistor design rules are also shrinking. As a sense amplifier system in this DRAM, an open bit line system (Open Bit Line: hereinafter referred to as an open BL system) is used up to 16K bits, and a folded bit line is used in the generations from 16K bits to the present 64M bits. At present, a method (Folded Bit Line: hereinafter referred to as a folded BL method) is used.

By the way, the open BL system has a problem that although the memory cell area is small, the sense amplifier design rules are very strict and it is difficult to arrange the sense amplifiers, and noise is large. On the other hand, the folded BL method is
Although the sense amplifier design rule can be greatly relaxed, there is a problem that the memory cell area is large and the chip size is large.

Therefore, the present inventor has already proposed a DRAM having the following new structure (Japanese Patent Laid-Open No. 6-18777).
No. 8). This is because by mixing the folded BL and the open BL in one cell array, the memory cell area can be reduced as compared with the folded BL method, and the design rule of the sense amplifier is relaxed as compared with the open BL method. Is something that can be done. Then, it is possible to simultaneously achieve the two demands of reducing the memory cell area and relaxing the sense amplifier design rule.
Furthermore, it is possible to reduce noise between bit lines.

A typical circuit example is shown in FIG. 24 (a), and an equivalent circuit at the time of its operation is shown in FIGS. 24 (b) and (c). Of the intersections of the word lines (WL0 to WL2) and the bit lines, two memory cells are arranged at three intersections when viewed from the word line direction, and two memory cells are arranged at three intersections when viewed from the bit line direction. ing. This allows one folded B at every two intersections.
The cell size can be reduced to 3/4 of L (FIG. 24A). The pitch of the sense amplifiers (SA0 to SA5) is shown in FIG.
As shown in (a), the number of bit lines is one for every three bit lines, and it can be reduced to 150% compared to one open BL for every two bit lines.

There is a switch between the cell array and the sense amplifier, and depending on the selected word line, FIG.
It changes like (c). (B) shows word line WL0,
When WL1 is selected, (c) is when WL2 is selected. As a set of three bit lines, for example, a bit line BL0 from which a memory cell is read and a bit line B from which a memory cell is not read when WL0 is selected.
L2 is amplified as a folded BL pair by the left sense amplifier. Further, the bit line BL1 from which the memory cell is read and the bit line of the right cell array are combined to form an open BL, and the open sense BL is used for amplification.

Such a cell arrangement also corresponds to the example shown in FIG. In this example, reading is performed by using one set of three folded BLs and a pair of folded BL pairs that share the reference bit line of the folded BL pair, and writing is performed as shown in FIG. Like this with open BL and folded BL pair. FIG. 29 shows FIG.
8 shows an operation example.

In the example of FIG. 24, since the open BL is sandwiched by the folded BL pair, it is resistant to δ ₂ noise generated during the operation of the sense amplifier, and the reference BL of the open BL pair has (1/2) Vcc of the adjacent BL. Since it is fixed to, it is strong against noise due to the shield effect. Further, since the open BL is inserted between the folded BL pair, the potential difference between the BL pair of the folded BL does not change even when receiving the common-mode noise, and is resistant to the BL noise. In addition, since the method of FIG. 29 is a folded BL read, there is no noise unique to open BL, and it is resistant to noise. Furthermore, it is possible to twist the bit lines, and noise can be reduced even if the density is increased.

As described above, the methods of FIGS. 24 and 29 are resistant to noise, have a small cell size, and can relax the design rule of the sense amplifier. However, this type of DRAM has a problem that there are many restrictions on the cell shape. The problem will be described below.

The conventional DR described above with reference to FIGS.
A layout plan view and a sectional view of a memory cell in the AM are shown, and FIG. 26 is a schematic view of FIG. Vertical words (WL0c to WL5c) and horizontal bit lines (BL0c to BL)
Two cells are placed at the three intersections of 5c). Bit line (BL) contact in one cell (indicated by ◇ in the figure)
Since it is shared with the adjacent BL contact, there is a transistor at the intersection of WL and the active area from the half of the BL contact, and there is a storage (SN) node contact (indicated by x in the figure) next to the transistor and it is connected to the storage node. . There is a passing word line next to the storage node, which shares half the adjacent cells. After all, regarding the cell size, if the line and the space of the wiring are F, respectively, the vertical direction (WL direction) is 2F, and the horizontal direction (bit line direction) is 3F, which is 3 × 2 = 6F ² cells.

FIG. 25B shows an example of a bit line post-fabricated stack cell for forming a bit line after the storage node is formed. This 6F ² stack cell is made after bit line.
Fits in a cell. However, firstly, when the bit line is formed after fabrication, a high dielectric constant film such as a tantalum oxide film (TaO ₂ ) or a strontium titanate film (Ti ₂ O ₃ ) is formed in the capacitor.
Sr) is hard to make. That is, there is a problem in that it is difficult to form a bit line or the like that requires high temperature heat treatment after forming the capacitor insulating film. Secondly, as shown in FIG. 25 (b), when the storage node has a BL contact and a space F between adjacent storage nodes, the capacitor size becomes F ^{2 and} becomes small.

On the other hand, when the bit line is first formed in the 6F ² cell, that is, the capacitor is formed after the bit line is formed, the heat treatment at the time of forming the bit line becomes irrelevant at the time of forming the capacitor, and the size of the capacitor can be made 2F ² .
However, there are the following problems in forming this bit line prefabricated stack cell with this 6F ² cell.

In the cell arrangement shown in FIG. 25A, since the BL comes over the SN contact, the storage node (SN) on the BL and the active area cannot be connected by the SN contact. Therefore, as shown in FIG. 27 (a), the active area is extended to a place between BL and SN there.
Need to make contact. And after forming BL, S
N is formed and a plate electrode is formed. This way, the SN does not have to keep a distance from the BL radish,
Only the SN-SN distance F becomes F in the vertical direction and 2 in the horizontal direction.
The cell capacitor size can be increased up to 2 × 1 = 2F ^{2 of} F, and a large cell capacity can be secured. However, FIG.
As shown in (b), the separation of the n-type diffusion interlayer greatly violates the rule, resulting in severe element isolation.

Further, in the cell arrangement shown in FIG. 25, the active area (diffusion layer + channel region) is formed so closely that the degree of freedom in forming other trench cells is small. Further, if the degree of freedom is small, firstly, the shape cannot be changed even if a defect occurs due to a cell layout problem.

From the standpoint of optical lithography, when using a phase shift mask such as Levenson or Herbtone,
If this arrangement does not match the other 8F ² cells for folded BL, etc., the cell size is difficult to shrink after all.

[0016]

As described above, in the conventional memory cell arrangement in which two memory cells are arranged at three intersections of word and bit lines, the cell capacity can be increased and a high dielectric film can be formed. There is a problem in that it is not suitable for a bit line prefabricated stack cell that can be formed, and there is no degree of freedom in cell arrangement with respect to other trench cells and the like.

The present invention has been made in consideration of the above circumstances. The object of the present invention is to arrange two cells at three intersections of a word line and a bit line, but to set a bit line destination. The present invention provides a cell suitable for a fabrication stack cell, capable of increasing the cell capacity and supporting a high-dielectric film, and having a large degree of cell freedom, and suitable for a fabrication cell after a bit line and a trench cell.

[0018]

In order to solve the above problems, the present invention employs the following configurations. That is, according to the present invention (claim 1), two memory cells are provided at a ratio of two to three in the word line direction and the bit line direction among the intersections of the plurality of word lines and the plurality of bit lines. In a dynamic semiconductor memory device including arranged memory cell arrays, the bit lines are arranged so as to be inclined from a direction orthogonal to the word lines, and an active region connecting a bit line contact of the memory cell and a storage node (SN) contact. Are inclined with respect to the direction orthogonal to the word line.

Further, according to the present invention (claim 2), in the intersections of the plurality of word lines and the plurality of bit lines, two in three in the word line direction and two in the bit line direction. In a dynamic semiconductor memory device including a memory cell array in which memory cells are arranged, the bit lines are arranged at an acute angle with respect to one word line direction, and bit line contacts and storage node (SN) contacts of the memory cells are arranged. It is characterized in that an active area connecting the two is arranged at an acute angle with respect to one direction of the word line direction.

According to the present invention (claim 9), two out of three intersections of a plurality of word lines and a plurality of bit lines in the word line direction and in the bit line direction are provided. In a dynamic semiconductor memory device including a memory cell array in which memory cells are arranged, the bit lines are arranged so as to be inclined from a direction orthogonal to the word lines.

According to the present invention (claim 10), two out of three intersections of a plurality of word lines and a plurality of bit lines in the word line direction and the bit line direction are two in three. In a dynamic semiconductor memory device including a memory cell array in which memory cells are arranged, an active region connecting a bit line contact of the memory cell and a storage node (SN) contact is arranged to be inclined from a direction orthogonal to the word line. It is characterized by

Here, the following are preferred embodiments of the present invention. (1) The memory cell has a stack type capacitor that forms a storage node below the bit line. (2) The shape of the storage node is elongated in an acute angle with respect to one word line direction. (3) The bit line contact is divided into first and second bit line contacts, the first bit line contact on the active region is connected to the upper pad layer, and the second bit line contact is formed on the pad. Formed and connected to the bit line,
The direction connecting the first bit line contact and the second bit line contact should be an obtuse angle with respect to one word line direction. (4) The memory cell has a stacked capacitor that forms a storage node on the bit line. (5) The memory cell has a trench type capacitor in which a storage node is formed in a trench provided in a semiconductor substrate. (6) The direction connecting the trenches of the two memory cells sharing the bit line contact is more acute than the direction of the active region. (7) The memory cell has a plate electrode formed in the substrate. (8) Bit line contacts of adjacent bit lines are arranged in a direction perpendicular to one word line direction. (9) The straight line connecting the closest bit line contacts of bit lines adjacent to each other at a right angle should be an obtuse angle with respect to one word line direction.

[0023]

According to the present invention, the active region and the bit line wiring, which are conventionally perpendicular to the word line direction and whose position cannot be changed spatially, can be arranged at an arbitrary angle. It is possible to freely set the line contact, the storage node (SN) daikon-SN daikon, the bit line contact-SN daikon, the trench-trench position, the storage node daikon-bit line distance, and the like.

Therefore, it becomes possible to loosen the places where the rules are strict and shorten the places where the rules are loose. Further, the relative position between the active regions connected to the adjacent bit lines was also restricted only by shifting the repeat pitch by 1/3, but in the present invention, the degree of freedom is about 1/4 and about 1/2. Going up
It can be designed at the optimum relative position that can be miniaturized, such as when using a phase shift such as Levenson.

Further, by arranging the bit lines and the active area, it is possible to select an arrangement having few defects. further,
When the relative position of the active area is about 1/2, the degree of freedom of the bit line radish increases, and a stack cell for forming a capacitor after forming the bit line can be easily formed.

As described above, the present invention realizes the reduction of the memory cell size, secures a large cell capacity, and relaxes the rules of the memory cell section, and further relaxes the sense amplifier section rule and the array noise. D that achieves both reduction
It becomes possible to realize a RAM.

[0027]

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 shows a D according to the first embodiment of the present invention.
It is a layout diagram showing a memory cell arrangement of a RAM. In order to facilitate understanding of the cell layout, FIG. 2 shows a drawing in which the bit line layer, the active area layer and the word line layer are extracted, and FIG. 3 shows the active area, SN contact,
First pad poly BL radish, second pad poly BL
FIG. 4 shows a drawing in which the Japanese radish is extracted, and FIG. 4 shows a drawing in which an active area, a bit line, an SN Japanese radish and a new storage node (SN) are added. Furthermore, in FIG.
The position where the memory cell is arranged is schematically shown.

As shown in FIGS. 1 and 2, the word line (WL)
14 are arranged in the vertical direction of the paper surface, and the bit line (B
L) 18 and the active area (diffusion layer) 13 are inclined and arranged. As shown in FIGS. 1 and 3, a first BL contact 15 is provided in the central portion of the active area 13, the BL contact 15 is connected to an upper pad layer 16, and a second BL contact is provided on the pad layer 16. 17 is provided and connected to the bit line 18.

SN contacts 19 are provided at both ends of the active area 13.
9 is connected to the storage node 20 as shown in FIG. Then, as shown in FIG. 5, the word line (W
Of the intersections of L) 14 and bit line (BL) 18, two to three memory cells are arranged in each of the word line direction and the bit line direction.

Assuming that the bit line 18 and the active area 13 are inclined at an acute angle with respect to one word line direction, the shape of the storage node 20 is elongated in an acute angle with respect to one word line direction. ing. Also,
The direction connecting the BL contacts 15 and 17 is an obtuse angle with respect to one word line direction.

FIG. 6 shows a stack cell applied to FIGS. 1 to 5 in which a storage node and a plate electrode are formed after forming a bit line. In the figure, 11 is a p-well and 12 is SiO
Element isolation insulating film such as ₂ ; 13 a diffusion layer to be an active area; 14 a word line WL; 15 a first BL contact; 16 a pad layer; 17 a second BL contact;
18 is a bit line, 19 is an SN contact, 20 is a storage node, and 21 is a plate electrode.

As shown in FIG. 6, the first BL contact 15 is dropped on one diffusion layer 13 of the cell transistor, and the pad layer 16 is formed on the first BL contact 15, and the position is deviated from the first BL contact 15. Then, the second BL contact 17 is dropped and the bit line 18 is formed thereon. FIG.
As shown in FIG. 7, the BL contacts 15 and 17 are offset from each other in the direction perpendicular to the above-described direction.

The deviation of the pitch in the surface direction of the active areas 13 connected to the adjacent bit lines 18 has been deviated by 1/3 in the conventional layout. It is shifted by about 1/2. As a result, a gap is formed at a position shown in FIG. 2A, and a space for arranging the second BL contact 17 in a staggered manner as shown in FIG. 3 is formed.

Bit line 1 on the displaced BL contact 17
When 8 is obliquely arranged, a place where the SN contact 19 is dropped is provided between BL and BL, and a capacitor composed of a storage node (SN) and a plate can be easily formed after the bit line 18 is formed. A large storage node area such as 4 is secured. Further, there may be a heat step at the time of forming the bit line, and a high dielectric film or the like can be easily formed. Even if the bit line 18 is bent obliquely, the sense amplifier circuit can be easily connected by bending it in the middle of the cell array as shown in FIG.

As described above, according to this embodiment, the active area and the bit line wiring, which are perpendicular to the word line direction and whose position cannot be changed spatially, can be arranged at an arbitrary angle. Bit line contact-bit line contact, storage node (SN) radish-SN radish, bit line contact-SN radish, trench-trench position, storage node radish-bit line distance, etc. can be freely set. Therefore, it is possible to loosen places where the rules are strict and shorten places where the rules are loose.

Conventionally, the relative position between the active areas connected to the adjacent bit lines has been conventionally restricted only by shifting the repeating pitch by 1/3, but in the present invention, it is about 1/4.
The degree of freedom is increased to about 1/2, and it is possible to design at an optimum relative position that enables miniaturization such as when using a phase shift such as Levenson. Also, an arrangement with few defects can be selected. Furthermore, when the relative position of the active area is about 1/2, the degree of freedom of the bit line radish increases, and a stack cell for forming a capacitor after forming the bit line can be easily formed. (Embodiment 2) FIG. 8 shows the D according to the second embodiment of the present invention.
FIG. 9 is a layout diagram showing a memory cell arrangement of RAM,
FIG. 10 shows a part of the extracted layers. Figure 11
Shows a sectional view of a memory cell corresponding to FIG. The difference from FIG. 1 and FIG. 6 is that the first and second BL contacts 15,
17 and the pad layer 16 are stopped, and one BL contact 1
The diffusion layer 13 and the bit line 18 are connected at 5.

Although not shown here, the first and second B
It may be formed by overlapping the L contacts. Figure 9
As shown in FIG. 1, if the diffusion layer 13 (the active area is the diffusion layer and the channel are added) is extended to the place B where the space is present and the BL radish is dropped as it is,
Similar to FIG. 6, a stack cell in which a capacitor is formed after BL formation can be formed.

Even with such a structure, the same effect as that of the first embodiment can be obtained. (Embodiments 3 and 4) FIG. 12 is a layout diagram showing a memory cell arrangement of a DRAM according to a third embodiment of the present invention, and FIG. 13 shows a memory cell arrangement of a DRAM according to the fourth embodiment of the present invention. It is a layout diagram shown.

12 and 13, the bit line 18,
Both the active areas 13 are obliquely arranged in the same direction with respect to the word lines 14. The bit line 16 and the active area 13 overlap each other, which is suitable for a stack cell for forming a bit line after forming a capacitor as shown in FIG. 15 and a trench cell as shown in FIG. 16 (a). Is also suitable. This trench cell is a memory cell having a substrate as a plate.

In contrast to FIG. 12, FIG. 13 shows a trench or S
An example in which the N radish is shifted in the word line direction is shown. By doing so, it is easy to connect the diffusion layer and the storage node by filling the strap poly across the trench and the diffusion layer as shown in FIG.

FIG. 14 shows an example in which the layers of FIG. 12 are partially extracted. Also in FIGS. 12 and 13, the deviation of the active area is about 1/2, and when the 1/3 pitch is difficult to be reduced due to defects such as lithography, according to this embodiment, the degree of freedom in selection is increased, and appropriate cell selection can be performed. . (Embodiments 5 and 6) FIG. 17 is a layout diagram showing a memory cell arrangement of a DRAM according to the fifth embodiment of the present invention, and FIG. 18 shows a memory cell arrangement of the DRAM according to the sixth embodiment of the present invention. It is a layout diagram shown.

In these embodiments, the diagonal direction of the bit line is opposite to that of FIGS. In FIG. 18, the position of the storage node contact or the trench is displaced from that of FIG. (Embodiments 7 and 8) FIG. 19 is a layout diagram showing a memory cell arrangement of a DRAM according to a seventh embodiment of the present invention.

In this case, the shift of the active area is about 1/4 pitch as compared with FIGS. When the phase is reversed by the Levenson mask (C is the phase opposite to D) when forming the active area, the range of the irreversible area (E) is smaller than other cells.

FIG. 20 is a layout diagram showing a memory cell arrangement of a DRAM according to the eighth embodiment of the present invention.
This is an example in which the active area 13 is in the shape of "he". (Examples 9 to 11) FIGS. 21 to 23 show the ninth to ninth aspects of the present invention.
FIG. 12 is a layout diagram showing a memory cell arrangement of a DRAM according to the eleventh embodiment. Even if either the active area or BL is perpendicular to WL, or if BL is inclined at about 45 °, the intersection 3 of WL and BL is 3 Two cell arrangements can be realized at one time. Of course, the memory cells of FIGS.
It is possible to form the stack cell for forming the capacitor after forming the L, the stack cell for forming the BL after forming the capacitor, the trench cell, or the like by directly or shifting the positions of the SN radish, the BL radish, and the BL.

As described above, according to the present invention, even if the BL and the active area are slanted, various kinds of memory cell arrays in which two cells are arranged at three intersections of WL and BL are realized to increase the degree of freedom, and the most miniaturization is achieved. You can select the facing cell. It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be made within the scope without departing from the gist thereof.

[0046]

As described above in detail, according to the present invention, a DRAM having a memory cell array in which two memory cells are arranged at three intersections of a plurality of word lines and a plurality of bit lines. In, the bit line and active area,
By arranging the memory cells at an angle from the direction orthogonal to the word lines, the memory cell size can be reduced, while ensuring a large cell capacity and easing the rules of the memory cell section.
Further, it becomes possible to achieve both relaxation of the sense amplifier section rule and reduction of array noise.

[Brief description of drawings]

FIG. 1 is a layout diagram showing a memory cell arrangement of a DRAM according to a first embodiment.

FIG. 2 is a layout diagram showing a part of layers in FIG.

FIG. 3 is a layout diagram showing a part of layers in FIG.

FIG. 4 is a layout diagram showing a part of layers in FIG.

FIG. 5 is a diagram schematically showing a position where a memory cell is arranged.

FIG. 6 is an element structure cross-sectional view showing a stack cell applied to the first embodiment.

FIG. 7 is a diagram showing an example in which a bit line is bent backward in the middle of a cell array.

FIG. 8 is a layout diagram showing a memory cell arrangement of a DRAM according to a second embodiment.

FIG. 9 is a layout diagram showing a part of layers of FIG.

FIG. 10 is a layout diagram showing a part of the layers in FIG.

FIG. 11 is a sectional view of an element structure showing a memory cell applied to the second embodiment.

FIG. 12 is a layout diagram showing a memory cell arrangement of a DRAM according to a third embodiment.

FIG. 13 is a layout diagram showing a memory cell layout of a DRAM according to a fourth embodiment.

FIG. 14 is a layout diagram showing a part of the layers in FIG.

FIG. 15 is a sectional view of an element structure showing a stack cell applied to the third and fourth embodiments.

FIG. 16 is a sectional view of a device structure showing a trench cell applied to the third and fourth embodiments.

FIG. 17 is a layout diagram showing a memory cell arrangement of a DRAM according to a fifth embodiment.

FIG. 18 is a layout diagram showing a memory cell arrangement of a DRAM according to a sixth embodiment.

FIG. 19 is a layout diagram showing a memory cell arrangement of a DRAM according to a seventh embodiment.

FIG. 20 is a layout diagram showing a memory cell arrangement of a DRAM according to an eighth embodiment.

FIG. 21 is a layout diagram showing a memory cell arrangement of a DRAM according to a ninth embodiment.

FIG. 22 is a layout diagram showing a memory cell arrangement of a DRAM according to the tenth embodiment.

FIG. 23 is a layout diagram showing a memory cell arrangement of a DRAM according to an eleventh embodiment.

FIG. 24 is a diagram showing a typical circuit example of a conventional DRAM and an equivalent circuit during operation.

FIG. 25 is a layout plan view and a sectional view of a memory cell in a conventional DRAM.

FIG. 26 is a diagram schematically showing a position where a memory cell is arranged.

FIG. 27 is a diagram showing an example in which the cell of FIG. 25 is applied to a stack cell in which a capacitor is formed after forming a bit line.

FIG. 28 is a diagram showing another circuit example of a conventional DRAM.

FIG. 29 is a diagram showing an operation example of FIG. 28;

[Explanation of symbols]

 11 ... P-well 12 ... Element isolation insulating film 13 ... Active area 14 ... Word line (WL) 15 ... First BL contact 16 ... Pad layer 17 ... Second BL contact 18 ... Bit line (BL) 19 ... SN contact 20 ... Storage node 21 ... Plate electrode

Claims (10)

[Claims] 1. From a memory cell array in which memory cells are arranged at a ratio of two to three in the word line direction and the bit line direction among intersections of a plurality of word lines and a plurality of bit lines. In the dynamic semiconductor memory device, the bit line is inclined with respect to the direction orthogonal to the word line, and an active region connecting a bit line contact of the memory cell and a storage node (SN) contact is defined as the word line. A dynamic semiconductor memory device, which is arranged so as to be inclined from an orthogonal direction. 2. A memory cell array in which memory cells are arranged at a ratio of two to three in the word line direction and the bit line direction among intersections of a plurality of word lines and a plurality of bit lines. In this dynamic semiconductor memory device, the bit line is arranged at an acute angle with respect to one direction of the word line, and an active region connecting a bit line contact of the memory cell and a storage node (SN) contact is defined by the word line. A dynamic semiconductor memory device characterized in that it is arranged at an acute angle with respect to one direction. 3. The dynamic semiconductor memory device according to claim 1, wherein said memory cell has a stack type capacitor which forms a storage node below said bit line. 4. The dynamic semiconductor memory device according to claim 3, wherein the shape of said storage node is elongated in an acute angle with respect to one of said word line directions. 5. The bit line contact is divided into a first bit line contact and a second bit line contact, the first bit line contact on the active region is connected to an upper pad layer, and a second bit line contact is formed on the pad. A bit line contact is formed and connected to the bit line, and a direction connecting the first bit line contact and the second bit line contact is an obtuse angle with respect to one of the word line directions. The dynamic semiconductor memory device according to claim 2. 6. The dynamic semiconductor memory device according to claim 1, wherein the memory cell has a stack type capacitor forming a storage node on the bit line. 7. The dynamic semiconductor memory device according to claim 1, wherein the memory cell has a trench capacitor having a storage node formed in a trench provided in a semiconductor substrate. 8. The dynamic semiconductor memory according to claim 7, wherein a direction connecting the trenches of the two memory cells sharing the bit line contact is more acute than a direction of the active region. apparatus. 9. From a memory cell array in which memory cells are arranged at a ratio of two to three in the word line direction and the bit line direction among intersections of a plurality of word lines and a plurality of bit lines, respectively. The dynamic semiconductor memory device according to claim 1, wherein the bit line is arranged so as to be inclined from a direction orthogonal to the word line. 10. Among the intersections of a plurality of word lines and a plurality of bit lines, with respect to the word line direction and the bit line direction,
In a dynamic semiconductor memory device including a memory cell array in which memory cells are arranged at a ratio of two to three, the active area connecting a bit line contact of the memory cell and a storage node (SN) contact is connected to the word line. A dynamic semiconductor memory device, which is arranged so as to be inclined from an orthogonal direction.