JP2000183268A - Lead frame and semiconductor device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a highly reliable lead frame, having improved close contact with a semiconductor chip and improved reflow crack resistivity when it is sealed, and to provide a semiconductor device using the lead frame. SOLUTION: A plurality of leads 33 support the backside of a semiconductor chip on one end part on a prescribed region, and they are fixed by insulating paste (or conductive paste, as necessary). The electrical connection parts 34 of the leads 33 are connected by a bonding wire 35. A mold resin member 35 seals the bonding wire 35, the semiconductor chip 31 and a lead part (inner lead part) excluding other terminals of the plural leads 33.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device that requires high reliability and miniaturization of a semiconductor package.

[0002]

2. Description of the Related Art FIG. 5 is a sectional view showing an example of a conventional semiconductor package. A semiconductor chip 51 is fixed on a die pad 50 by a paste 52. A plurality of leads 53 are arranged around the die pad 50. The positional relationship between the position of the lead 53 and the die pad 50 is such that the die pad 50 is at a lower level than the lead 53.

[0003] The bonding pads 54 on the semiconductor chip 51 and the predetermined locations of the leads 53 (each inner lead) are as follows.
For example, they are connected by bonding wires 55.
The die pad 50, the semiconductor chip 51, the bonding wires 55, and the connection portions thereof are sealed with a mold resin 56.

FIG. 6 is a plan view showing a general form of the die pad 50 which is a part of a conventional lead frame. By improving the fluidity of the resin at the time of sealing or relaxing the stress by devising the tie bar 61 to a level lower than the position of the lead 53 (see FIG. 5) or by providing a through hole (not shown) in the die pad 50. Aim.

However, it is known that the adhesion between the metal used for the lead frame and the molding resin is weak. Also, the heat treatment during the manufacturing process allows the die pad 5
Oxide film may be formed on the surface of the substrate, and the bonding force with the chip may be reduced.

Further, the difference in expansion coefficient between the mold resin 56 and the metal used for the lead frame is large. For this reason,
Deterioration of the adhesion between the die pad 50 and the sealing resin due to the influence of the temperature change is unavoidable and causes cracks.

[0007]

In the conventional lead frame structure, the anti-oxidation property is not sufficient, and the bonding force between the chip and the die pad is reduced by heat treatment at the time of resin sealing. Deterioration of adhesion between the die pad and the sealing resin is also a problem. Due to these effects, the resin contact portion including the die pad, the inner lead, and the chip is easily peeled off, which may cause a reflow crack.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to improve the structure of a lead frame on which a semiconductor chip is mounted so as to eliminate the cause of deterioration in the adhesion between the lead frame and the molding resin and to prevent cracks. An object of the present invention is to provide a resin-encapsulated semiconductor device realizing improvement in performance.

[0009]

According to the present invention, there is provided a lead frame which supports a back surface of a semiconductor chip in a predetermined region at one end thereof and has a plurality of leads having an electrical connection with a main surface of the semiconductor chip. A frame in which the other ends of the plurality of leads are connected and integrated.

A semiconductor device using a lead frame according to the present invention comprises: a semiconductor chip having a plurality of electrodes provided on a main surface thereof;
A plurality of leads each supporting the back surface of the semiconductor chip in a predetermined region at one end thereof and having an electrical connection portion with the main surface of the semiconductor chip; and electrically connecting each of the leads corresponding to each electrode of the semiconductor chip. A connection member for electrically connecting a connection portion, the connection member and the semiconductor chip,
And a configuration in which a lead portion of the plurality of leads excluding the other terminal is sealed with a resin.

According to the lead frame of the present invention and the semiconductor device using the same, since the die pad is not formed, the semiconductor chip is less affected by the difference in the coefficient of thermal expansion in the sealing with the mold resin and contributes to the stress relaxation. It can be mounted and fixed.

[0012]

FIG. 1 is a plan view showing a main part of a lead frame according to a first embodiment of the present invention.
Multiple leads 11 without die pad and hollow
Each of the predetermined regions 12 including one end of the semiconductor chip supports the back surface of the semiconductor chip (two-dot chain line) 13.
The lead 11 is an electrical connection 1 with the main surface of the semiconductor chip.
Four. The other ends of the leads are connected to a frame (not shown).

The electrical connection portion 14 is, for example, plated with Ag. Since the leads 11 also serve to support the semiconductor chip, the leads 11 need to be provided with an insulating bonding paste for bonding to the semiconductor chip. However, if there is a lead among the plurality of leads 11 that is desired to be electrically connected to the back surface of the semiconductor chip, the lead is naturally provided with a conductive adhesive paste.

According to the above configuration, since there is no die pad,
A lighter lead frame can be realized. Also, in those having a conventional die pad, the die pad portion is usually
Ag plating is performed, and a paste in which an epoxy-based monomer contains an amine-based curing agent and 60 to 80% of Ag is provided, so that the semiconductor chip is bonded. That is, the larger the area of the die pad portion, the more Ag
Is used.

On the other hand, in the lead frame of the present invention, a die pad is not formed, and a paste containing, for example, Ag is used for the plurality of leads 11 except for the lead to be electrically connected to the back surface of the semiconductor chip. Will not be. This reduces the area in which Ag is used, contributing to a reduction in lead frame cost. Here, as shown in FIG. 1, at least the above-mentioned electrical connection portion 14 needs to be plated with Ag.

In recent years, Cu-based materials have attracted attention as a material for lead frames represented by 42 alloys. A Cu-based lead frame has excellent characteristics for heat dissipation high-speed signal transmission, and facilitates high-performance package design.

However, since a Cu-based lead frame also undergoes a heat treatment step, an oxide film is formed on its surface. This causes instability in adhesion to the semiconductor chip. If the semiconductor chip is fixed on the die pad as in the related art, the bonding force is weakened, and the possibility of cracking or peeling increases.

On the other hand, in the lead frame of the present invention, the mounting and fixing of the semiconductor chip are supported by the predetermined regions 12 including the one ends of the plurality of leads 11, respectively. The structure is such that it is fixed.

In a copper-based lead frame, for example, C
It is a Cu alloy to which r, Zn and Zr are added. Cr, Z
r stabilizes the oxide film of Cu, and Zn has the function of improving the adhesion to the base material. 0.05 ~ 2.0wt each
% Of two kinds.

FIG. 2 is a plan view showing a configuration of a lead frame according to a second embodiment of the present invention. As in the first embodiment, the semiconductor chip (two-dot chain line) 2 is provided in each of the predetermined regions 22 including one ends of the plurality of hollow leads 21 without the die pad in the lead frame 20.
3 is supported. And lead 21
Has an electrical connection 24 with the main surface of the semiconductor chip. The electrical connection part 24 is, for example, plated with Ag.

The other ends of the plurality of leads 21 are connected to a frame (lead frame 20). 2
The large frame of the dashed line 25 indicates the region to be sealed with resin. Further, the dam bar 26 is for preventing the resin from flowing out at the time of sealing, and is finally eliminated (punched).

In the above configuration, it is not necessary that all the leads of the lead frame 20 support the back surface of the semiconductor chip at one end like the leads 21. For example, the ends of the leads 21a are electrically connected to the main surface of the semiconductor chip without supporting the back surface of the semiconductor chip.

With respect to the plurality of leads 21, the predetermined region 22 at one end supporting the back surface of the semiconductor chip is located at a level different from that of the electrical connection portion 24, that is, at a level lower than the electrical connection portion 24. May be. By adopting such a configuration, when the semiconductor chip is mounted, the electrodes (not shown) on the main surface of the semiconductor chip and the wiring (for example, bonding wires) of the electrical connection portion 24 are realized as close to the horizontal as possible and at a short distance.

According to the above configuration, the same effects as in the first embodiment can be obtained. That is, a lead frame that is reduced in weight can be realized because there is no die pad. In addition, the area where Ag is used is reduced, which contributes to cost reduction of the lead frame.

FIG. 3 is a sectional view showing a configuration of a semiconductor device according to a third embodiment of the present invention. A semiconductor chip is sealed with a mold resin by using a lead frame as shown in the first and second embodiments, thereby forming a resin-sealed semiconductor device.

That is, a plurality of electrode pads 32 are provided on the main surface of the semiconductor chip 31. Multiple leads 3
4 denotes a semiconductor chip 31 in each of predetermined regions at one end.
, And the back surface of the semiconductor chip 31 is fixed by an adhesive paste 33. The electrical connection portions 35 of the leads 34 corresponding to the respective electrode pads 32 are connected by, for example, bonding wires 36.

Although not shown, the electrical connection portion 35 is plated with metal, for example, Ag plating (see 14 and 24 in FIGS. 1 and 2). Mold resin member 37
Seals the inner lead portions of the bonding wire 36, the semiconductor chip 31, and the plurality of leads 34.

Of the plurality of leads 34, the semiconductor chip 3
1 For leads that need to maintain insulation from the back,
Insulating adhesive paste is used in a region where the semiconductor chip 31 is fixed, and in a lead that needs to maintain conductivity with the back surface of the semiconductor chip 31, the semiconductor chip 3
1 in a region where the adhesive layer 1 is fixed.
g paste) is used.

According to the configuration described above, the form in which the die pad is not formed, that is, the configuration in which the back surface of the semiconductor chip 31 is supported and fixed in each of the predetermined regions at one end of the plurality of leads 34, Eliminates the cause of deterioration of cracking properties and improves crack resistance.

That is, the semiconductor chip is hardly affected by the difference in the coefficient of thermal expansion at the time of sealing with the mold resin, and the mounting and fixing of the semiconductor chip which contributes to stress relaxation can be performed. Further, since the die pad is not formed, the configuration contributes to the reduction in thickness and size of the package.

In addition, out of the plurality of leads 34, except for the leads to be electrically connected to the back surface of the semiconductor chip 31,
For example, a paste containing Ag is not used, which contributes to cost reduction of the lead frame.

FIG. 4 is a sectional view showing a configuration of a semiconductor device according to a fourth embodiment of the present invention. The same parts as those in the third embodiment are denoted by the same reference numerals, and description thereof is omitted. Regarding the plurality of leads 34, a predetermined region 41 at one end supporting the back surface of the semiconductor chip 31 is
Is located at a level different from that of the electrical connection portion 35 with the main surface, that is, at a level lower than the position of the electrical connection portion 35.

According to the above configuration, the electrodes (for example, the bonding wires 36) between the electrodes on the main surface of the semiconductor chip 31 and the electrical connection portions 35 are realized with a distance as short as possible. Also,
In the resin sealing step, it is expected that the resin flows uniformly on the main surface side and the back surface side of the semiconductor chip 31. Accordingly, it is possible to prevent a wire flow that causes a short circuit due to deformation of the bonding wire due to the flow of the resin. Other configurations are the same as those of the third embodiment, and the same effects as those of the third embodiment can be obtained.

As described above, in the present invention, by eliminating the die pad, the stress relaxation for the difference in the thermal expansion coefficient between the 42-alloy type and the copper-type frame can be achieved by using the metal (A).
g) Plating contributes to cost reduction by using only the wire bonding portion.

In the third and fourth embodiments, bonding wires are used for the electrodes on the main surface of the semiconductor chip 31 and the wires for the electrical connection portions 35. However, the present invention is not limited to this.
As in the case of the B tape, a connection member having conductive leads formed on an insulating film so as to match the pitch of the leads 34 may be employed.

[0036]

As described above, according to the present invention,
By eliminating the die pad and supporting and fixing the semiconductor chip in the area of one end of the lead, it is possible to improve the adhesion to the semiconductor chip to be resin-sealed and the reflow crack resistance during the sealing. In addition, a highly reliable lead frame that can cope with thinning and miniaturization of a package and a semiconductor device using the same can be provided.

[Brief description of the drawings]

FIG. 1 is a plan view showing a main configuration of a lead frame according to a first embodiment of the present invention.

FIG. 2 is a plan view showing a configuration of a lead frame according to a second embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a configuration of a semiconductor device according to a third embodiment of the present invention.

FIG. 4 is a sectional view illustrating a configuration of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating an example of a conventional semiconductor package.

FIG. 6 is a plan view showing an example of a die pad which is a part of a conventional lead frame.

[Explanation of symbols]

 11, 21, 21a, 34 Lead 13, 23, 31 Semiconductor chip 14, 24, 35 Electrical connection 20 Lead frame 32 Electrode pad 33 Bonding paste 36 Bonding wire 37 Mold resin

Claims (8)

[Claims] 1. A plurality of leads each supporting a back surface of a semiconductor chip in a predetermined region at one end thereof and having an electrical connection with a main surface of the semiconductor chip, and each other end of the plurality of leads being connected and integrated. A lead frame, comprising: a lead frame. 2. The lead frame according to claim 1, wherein the plurality of leads are plated with metal at the electrical connection part. 3. The semiconductor device according to claim 1, wherein a predetermined region at one end supporting the back surface of the semiconductor chip is located at a different level from the electrical connection portion. The lead frame according to 1. 4. A semiconductor chip having a plurality of electrodes provided on a main surface thereof, and a plurality of semiconductor chips each having a predetermined region at one end supporting the back surface of the semiconductor chip and having an electrical connection with the main surface of the semiconductor chip. And a connection member for electrically connecting each electrode of the semiconductor chip and the corresponding electrical connection portion of the lead; and removing the connection member, the semiconductor chip, and the other terminal of the plurality of leads. A lead portion sealed with a resin. 5. The lead of the plurality of leads, which maintains insulation with respect to the back surface of the semiconductor chip, is provided with an insulating adhesive paste in the predetermined region, and is provided between the lead and the back surface of the semiconductor chip of the plurality of leads. 5. The semiconductor device according to claim 4, wherein the lead for maintaining conductivity is provided with a conductive adhesive paste in the predetermined region and the semiconductor chip is fixed. 6. The semiconductor device according to claim 4, wherein said plurality of leads are plated with metal at said electrical connection portions. 7. A semiconductor chip having a plurality of electrodes provided on a main surface thereof; a plurality of leads electrically connected to respective electrodes of the semiconductor chip via a connecting member; the connecting member and the semiconductor chip; And a configuration in which a lead portion of the plurality of leads excluding an external connection end side is sealed with a resin. The semiconductor chip back surface is supported in a predetermined region of the lead portion, and the semiconductor chip back surface is provided. The lead for maintaining insulation with the semiconductor chip is provided with an insulating adhesive paste in the predetermined region, and the lead for maintaining conductivity with the back surface of the semiconductor chip is provided with a conductive adhesive paste in the predetermined region. A semiconductor device having a chip fixed thereto. 8. The lead according to claim 7, wherein a predetermined area for supporting the back surface of the semiconductor chip is located at a level different from that of the external connection end. flame.