JP2000181591A - Information processor provided with lvds interface signal amplitude setting function and lvds interface signal amplitude setting method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To output the signal of optimized amplitude in an information processor provided with an LVDS interface signal amplitude setting function and an LVDS interface signal amplitude setting method. SOLUTION: An output circuit 2 is connected to a pair of cables 500 for signal, to which a liquid crystal display device 300 is connected, and outputs the differential signal of a low voltage according to an LVDS interface for the liquid crystal display device 300 onto these cables. An amplitude setting circuit 3 sets the amplitude of the differential signal outputted by the output circuit 2. A detecting means 6 detects the cable length of cables 500 for signal and forms a cable length signal corresponding to that length. Based on the cable length signal, signal forming means 16 forms an amplitude control signal. Based on the amplitude control signal, the amplitude setting circuit 3 sets the amplitude of the differential signal outputted by the output circuit 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an information processing apparatus having an LVDS interface signal amplitude setting function and an LV.
More specifically, the present invention relates to an LVD having a function of automatically setting the amplitude of a signal in a low voltage differential signal (LVDS) interface connecting a computer main body and a liquid crystal display device.
The present invention relates to an information processing apparatus having an S interface signal amplitude setting function and an LVDS interface signal amplitude setting method.

[0002]

2. Description of the Related Art In recent years, the display screen of a computer has been shifting from a cathode ray tube (CRT) to a liquid crystal display (LCD). This is because the resolution of the LCD is increased and the response speed is also increased. For this reason, the amount of data transferred from the computer body to the LCD has increased, and the data transfer rate has been increased accordingly. Therefore, this L
A low voltage differential signal (LVDS) interface has been used as a digital interface for connecting between a computer main body and an LCD so that the number of signal lines does not increase even when the resolution and speed of a CD are increased. Was.

FIG. 12 shows a transmission (driver) circuit and a reception (receiver) circuit in the LVDS interface. In FIG. 12, a driver circuit 101 is an output circuit 1
02 and an amplitude setting circuit 103. Receiver circuit 1
04 is an input circuit 105. The output circuit 102 and the input circuit 105 are connected by a pair of cables 500 for LVDS interface. The differential signal is output from the output circuit 102 onto the cable 500, and the differential signal output on the cable 500 is input to the input circuit 105. An external resistor 116 having a certain resistance value is connected to the amplitude setting circuit 103. This external resistor 116
When the user sets the resistance value of the signal to an appropriate value, the amplitude (voltage) of the signal output from the output circuit 102 is set. That is, the amplitude is set by the value of the external resistor 116, and is controlled by the amplitude setting circuit 103 to have such an amplitude. By appropriately selecting the resistance value of the external resistor 116, the amplitude is set to an appropriate value, for example, about 200 mV.

According to this LVDS interface, for example, a minute signal having an amplitude of about 200 mV or less
Data can be transferred at a high speed of bps (megabit per second). Even in such high-speed data transfer, noise can be prevented from being generated during transfer, and the number of cables 500 can be prevented from increasing even when the transfer amount increases.

[0005]

The output signal of (the output circuit 102 of) the LVDS interface is, as described above,
Because of the small amplitude and high bit rate, during its propagation,
It is necessary to consider attenuation in the cable 500 and the like.
That is, it is necessary to deal with a distributed constant circuit. Therefore,
The amplitude of the output signal of the LVDS interface is set according to the maximum cable length of the cable 500 that can be connected. Thereby, the cable 50 having the maximum cable length is used.
Even when 0 is used, the output signal can be propagated.

However, since the determination of the amplitude is made by the external resistor 116 of the amplitude setting circuit 103 as described above, a person converts it from the maximum cable length to the external resistor 11.
6, the resistance 116 having the resistance value has to be selected and externally connected. For this reason, the following various inconveniences have occurred.

That is, a human can convert the external resistor 116
Is cumbersome, and the determination of the amplitude may be erroneous. When the cable 500 shorter than the assumed maximum cable length is actually used, a signal is output with a voltage amplitude larger than necessary. In this case, electromagnetic waves are unnecessarily radiated, and may not meet environmental standards or may cause interference with other devices.

On the other hand, when the cable 500 to be connected is determined in advance, a person checks the cable length, and externally attaches an external resistor 116 having a resistance value determined from this to the amplitude setting circuit 103. Is possible. In this case, the optimum amplitude can be set, but it is troublesome for a person to measure the cable length and obtain the resistance value. Further, not only the determination of the amplitude but also the measurement itself may be erroneous.

It is an object of the present invention to provide an information processing apparatus having an LVDS interface signal amplitude setting function capable of outputting a low-voltage differential signal having an optimized amplitude.

Another object of the present invention is to provide an LVDS interface signal amplitude setting method capable of optimizing the amplitude of a low voltage differential signal.

It is another object of the present invention to provide an information processing apparatus having an LVDS interface signal frequency setting function capable of outputting a low-voltage differential signal having an optimized frequency.

[0012]

FIG. 1 is a block diagram showing the principle of the present invention, and shows an information processing apparatus 200 having an LVDS interface signal amplitude setting function according to the present invention. The information processing device 200 includes an output circuit 2, an amplitude setting circuit 3, a detecting unit 6, and a signal forming unit 16. Output circuit 2
Is connected to one end of a pair of signal cables 500 whose other ends are connected to the liquid crystal display device 300, and has a low voltage difference according to the LVDS interface which is a video data signal for the liquid crystal display device 300 on the signal cable 500. Outputs a motion signal. The amplitude setting circuit 3 sets the amplitude of the differential signal output from the output circuit 2. The detecting means 6 detects the cable length of the signal cable 500 and forms a cable length signal corresponding to the detected cable length. The signal forming means 16 forms an amplitude control signal based on the cable length signal from the detecting means 6. The amplitude setting circuit 3 sets the amplitude of the differential signal output from the output circuit 2 based on the amplitude control signal from the signal forming means 16.

According to the information processing apparatus 200 having the LVDS interface signal amplitude setting function of the present invention, the amplitude control signal can be formed based on the automatically detected cable length of the signal cable 500. This allows
The amplitude of the differential signal output from the output circuit 2 can be automatically set to a value corresponding to the cable length of the signal cable 500. Therefore, since it is not necessary for a person to calculate the resistance value of the external resistor by converting it from the cable length and externally attach the resistance value, the trouble of setting the amplitude can be eliminated, and the possibility of erroneously determining the amplitude can be eliminated. Further, since a signal having an optimum amplitude according to the cable length (in consideration of attenuation in the cable during propagation) is output, it is possible to prevent a signal having a voltage amplitude larger than necessary from being output. Therefore, it is possible to satisfy the environmental standard and prevent the interference wave to other devices. As a result, the output signal of the LVDS interface having a small amplitude and a high bit rate can be accurately propagated.

[0014]

FIG. 2 is an explanatory diagram of an information processing apparatus, showing an example of an information processing apparatus 200 having an LVDS interface signal amplitude setting function according to the present invention.

The information processing apparatus shown in FIG. 2 is, for example, a personal computer. The information processing apparatus 200 is a computer body (tower), a liquid crystal display device 300 is an output device, a keyboard 400 is an input device, and a liquid crystal display device. It comprises a signal cable 500 for 300 and a signal cable 600 for keyboard 400.

Signal cable 5 for liquid crystal display device 300
One end of 00 is connected to the information processing device 200, and the other end is connected to the liquid crystal display device 300. The signal cable 500 has a predetermined characteristic impedance. The information processing device 200 sends out a video data signal (digital signal) for the liquid crystal display device 300 via the signal cable 500 as a low-voltage differential signal according to the LVDS interface. That is, the differential signal is a minute (low voltage) signal having a mutual potential difference (amplitude) of about 200 mV or less, and has a transmission speed of about 600 Mbps. LV
Standards are defined for the DS interface.

The signal cable 500 is for transmitting an original signal (video data signal). Signal cable 500
Is a pair of cables (signal lines) as shown in FIG. 1 and the like, and is, for example, a single cable in appearance. Since the signal cable 500 transmits a video data signal and thus has a very large transmission amount, the signal cable 500 is different from the signal cable 600 for the keyboard 400. That is, the signal cable 500 can transmit the large amount of video data signals.

FIG. 3 is a block diagram of an information processing apparatus, showing an example of an information processing apparatus 200 having an LVDS interface signal amplitude setting function of the present invention.

The information processing apparatus 200 includes an output unit 1, which is an LVDS interface, a detecting unit 6, and a signal forming unit 1.
6 is provided. The output unit 1 is composed of, for example, an IC having a product name “SiI140” manufactured and provided by Silicon Image Corporation. The output unit 1 includes an output circuit 2 and an amplitude setting circuit 3. The output circuit 2 includes a signal cable 5
00, a low-voltage differential signal according to the LVDS interface, which is a video data signal for the liquid crystal display device 300, is output. The output circuit 2 includes, for example, a differential amplifier circuit. The output circuit 2 forms and outputs the differential signal according to the input of the video data signal for the liquid crystal display device 300. The amplitude setting circuit 3 sets the amplitude of the differential signal output from the output circuit 2.

The differential signal output on the signal cable 500 is input to the input unit 4 which is an LVDS interface of the liquid crystal display device 300. The input unit 4 includes an input circuit 5. The input unit 4 is composed of, for example, an IC having a product name “SiI141” that is paired with the output unit 1 manufactured and provided by Silicon Image Corporation. The input circuit 5 has an input impedance that matches (matches) the characteristic impedance of the signal cable 500. Therefore, the input circuit 5 does not reflect the differential signal output from the output circuit 2 and transmitted through the signal cable 500. The input circuit 5 includes, for example, a differential amplifier circuit.

The detecting means 6 detects the cable length of the signal cable 500 and forms a cable length signal corresponding to the detected cable length. That is, the detecting means 6 measures the time from the transmission of the differential signal to the return of the reflected wave by using the intentional reflection of the transmitted differential signal (digital signal), thereby obtaining the cable length. Is calculated. The detection means 6 includes a detection output circuit 7, a detection cable 8, a reflected wave generation circuit 9, a reflected wave detection circuit 10, and a cable length signal forming circuit 11. The detection cable 8 corresponds to the signal cable 500, the detection output circuit 7 corresponds to the output circuit 2, and the reflected wave generation circuit 9 corresponds to the input circuit 5. The cable length signal is input to the signal forming means 16.

The detection cable 8 includes a signal cable 50
This is a pair of dedicated cables for calculating the cable length of 0, and has the same length as the signal cable 500. The detection cable 8 has a predetermined characteristic impedance.
The characteristic impedance of the detection cable 8 may be the same as or different from the characteristic impedance of the signal cable 500. It should be noted that the detection cable 8 is externally integrated with the signal cable 500 (a single external cable housed in the same coating so as not to interfere with each other). You are not conscious of

The length of the detection cable 8 is substantially the same as the length of the signal cable 500. The length of the signal cable 500 is physically the length of the cable between the information processing device 200 and the liquid crystal display device 300. However, here, the length of the signal cable 500 is determined by the distance between the output terminal 30 of the output unit 1 and the input terminal 31 of the input unit 4, or the output terminal of the output circuit 2. This is the distance to the input terminal of the input circuit 5. Therefore, FIG.
It is desirable that the distance from the output terminal of the detection output circuit 7 to the reflected wave generation circuit 9 is equal to the distance from the output terminal of the output circuit 2 to the input terminal of the input circuit 5 as shown in FIG.

The detection output circuit 7 is connected to one end of the detection cable 8 and outputs a predetermined low-voltage detection differential signal for generating a reflected wave on the detection cable 8. That is, the differential signal for detection is also a differential signal according to the LVDS interface. The output impedance of the detection output circuit 7 is made to match the characteristic impedance of the detection cable 8. The detection output circuit 7 is composed of, for example, a differential amplifier circuit. The detection output circuit 7 forms and outputs the differential signal in response to the input of the reflected wave generation signal for generating the reflected wave. The reflected wave generation signal is different from the video data signal supplied to the output circuit 2 and, as shown in FIGS. 5 and 6, a signal of a fixed cycle, that is, a high level and a low level are alternately repeated every half cycle. Signal.

The reflected wave generation circuit 9 is provided at the other end of the detection cable 8 and generates a reflected wave for the detection differential signal. The input impedance of the reflected wave generation circuit 9 is intentionally made different from the characteristic impedance of the detection cable 8. As a result, a reflected wave is generated with respect to the detection differential signal (digital waveform) output from the detection output circuit 7 and transmitted through the detection cable 8. This reflected wave is transmitted through the detection cable 8 and returns to the detection output circuit 7 again. In this example, as shown in FIG. 3, the reflected wave generation circuit 9 is configured by short-circuiting the other end of the detection cable 8. Therefore, the detection output circuit 7
Are returned to the detection output circuit 7 without interfering with each other in the reflected wave generation circuit 9. That is, the signal on the non-inverted output side of the differential signal for detection reaches the inverted output side of the output circuit 7 for detection, and the signal on the inverted output side reaches the non-inverted output side of the output circuit 7 for detection.

The reflected wave detection circuit 10 includes a detection cable 8
And detects a reflected wave generated in the reflected wave generation circuit 9. The reflected wave detection circuit 10 includes, for example, a differential amplifier circuit. The side of the pair of detection cables 8 connected to the non-inverted output terminal and the inverted output terminal of the detection output circuit 7 is connected to the non-inverted input terminal and the inverted input terminal of the reflected wave detection circuit 10, respectively. The reflected wave detection circuit 10 detects a change in the potential of the detection cable 8 on the side of the detection output circuit 7. Specifically, when the potential difference between the non-inverted output terminal and the inverted output terminal of the detection output circuit 7 (that is, the reflected wave detection circuit 10) becomes larger than a predetermined threshold, the reflected wave detection circuit 10 A detection signal of the reflected wave is output. The output of the reflected wave detection circuit 10 is input to (the reflection time detection circuit 12 of) the cable length signal formation circuit 11.

The cable length signal forming circuit 11 forms a cable length signal based on the result of detection of the reflected wave by the reflected wave detection circuit 10. The cable length signal forming circuit 11 includes a reflection time detecting circuit 12 and a signal amplitude circuit 13.

The reflection time detection circuit 12 detects a time (reflection time) from when the detection differential signal is output to when the reflected wave is detected. Therefore, the reflection time detection circuit 12
, The reflected wave generation signal input to the detection output circuit 7 and the signal output from the reflected wave detection circuit 10 are input.
The reflection time detection circuit 12 obtains the difference between these signals (that is, the reflection time) and outputs this to the signal amplitude circuit 13. The reflection time is a time required for the signal to reciprocate, and is twice as long as the signal propagation time in the detection cable 8. In this example, the reflection time detection circuit 12 includes, for example, a two-input AND gate circuit 12. The input of the detection output circuit 7 (a signal for generating a reflected wave) is input to one input terminal of the AND gate circuit 12, and the output of the reflected wave detection circuit 10 is input to the other input terminal. The output of the AND gate circuit 12 is input to the signal amplitude circuit 13.

The signal amplitude circuit 13 includes the reflection time detection circuit 1
A cable length signal is formed on the basis of the reflection time detected in Step 2 and supplied to the signal forming means 16. As described below,
Since the signal forming means 16 in this example is composed of a voltage controlled variable resistance circuit, the cable length signal formed by the signal amplitude circuit 13 is a voltage giving a resistance value corresponding to the amplitude to be set. Therefore, in this example, the signal amplitude circuit 1
Reference numeral 3 includes, for example, an integrating circuit for generating the voltage. The integrating circuit 13 includes a resistor 14 and a capacitance element 15 connected in series between the output of the AND gate circuit 12 and the ground potential. The potential at the connection point between the resistor 14 and the capacitance element 15 is supplied to the signal forming means 16 as a cable length signal. Since the differential signal output from the detection output circuit 7 has a fixed period, the signal obtained by superimposing the influence of the reflected wave on the differential signal is integrated to obtain the influence of the reflected wave, that is, the detection cable 8. Is output from the integration circuit 13.

The signal forming means 16 forms an amplitude control signal based on the cable length signal from the detecting means 6. This amplitude control signal is input to the amplitude setting circuit 3. For this purpose, the signal forming means 16 comprises a voltage control variable resistance circuit for automatically setting the amplitude of the differential signal output from the output circuit 2 according to the control signal.

In this example, the voltage control variable resistance circuit 1
6 comprises an AD (analog-digital) conversion circuit 17 and a resistance circuit 18. The AD conversion circuit 17 converts an analog voltage that is a cable length signal into a digital signal of a plurality of bits at a predetermined resolution. This digital signal is supplied to the resistance circuit 18. The resistance circuit 18 is a MOSFE
T (MOS type field effect transistor) and a resistance element connected in parallel with the T are used as a unit, and the units are connected in series by the number of the plurality of bits. The resistance circuit 18 is connected, for example, between the power supply potential Vcc and the amplitude setting circuit 3. For example, if a certain bit of the plurality of bits is set to 0 as a result of the AD conversion, the corresponding MOSFET is turned off.
F, and if it is 1, the corresponding MOSFET is turned ON. As a result, the resistance value of the resistor circuit 18, which is an external resistor of the output circuit 2, is automatically set according to the cable length signal.

Next, referring to FIG. 5, the LV according to the present invention will be described.
The setting of the amplitude of the differential signal according to the DS interface will be described. FIG. 5 is a detection waveform diagram in the information processing apparatus 200 shown in FIG.

An input signal (a signal for generating a reflected wave) is input to the detection output circuit 7. The input signal is a continuous constant pulse. Let A be the waveform of this input signal. In response to this input signal, the detection output circuit 7 outputs a detection differential signal onto the detection cable 8 at time t0. The waveform of the differential signal for detection is B. The waveform B is determined by the output impedance of the detection output circuit 7 and the input impedance of the detection cable 8. A waveform B is a potential difference between the pair of detection cables 8. This waveform B is also a signal transmitted through the LVDS interface and has a very small potential difference (for example, 200 mV) and a high-speed potential (for example, 600 mV).
Mbps signal).

The reflected wave generation circuit 9 generates a reflected wave for the differential signal for detection. That is, the waveform B that has traveled through the detection cable 8 and reached the reflected wave generation circuit 9 generates a reflected wave in the reflected wave generation circuit 9. Reflected wave generation circuit 9
Since the input impedance is zero due to the short circuit, the waveform of the reflected wave has the opposite phase to the original waveform B and proceeds to the detection output circuit 7 side.

At the time t1
The reflected wave arriving at the detection output circuit 7 does not re-reflect at the detection output circuit 7 because its output impedance is the same as the characteristic impedance of the detection cable 8. That is, the output waveform A of the detection output circuit 7 and the waveform of the reflected wave have opposite phases. Therefore, as shown in FIG. 3, at time t1, the output of the detection output circuit 7 becomes 0V.

Here, as can be seen from the waveform diagram of FIG.
Signals transmitted on the VDS interface (waveform B
Is a signal of a bit rate or a frequency such that a reflected wave of the transmitted signal returns within a period of an original half cycle (a period in which the waveform A is at a high level). That is, the length of the signal cable 500 is such that the reflected wave can return to the output side within a half cycle of the signal.

The reflected wave is detected by a reflected wave detection circuit 10 provided at one end of the detection cable 8. As shown in FIG. 5, the reflected wave detection circuit 10 has an intermediate potential threshold Vth1 of the differential signal output from the detection output circuit 7. Therefore, the reflected wave detection circuit 10 starts outputting a high-level signal when the differential signal is output from the detection output circuit 7 and the output becomes larger than the threshold value Vth1, and the output becomes approximately 0 V due to the influence of the reflected wave. When the output becomes smaller than the threshold value Vth1, the output of the high-level signal is stopped (the output of the low-level signal is started). As a result, the output of the AND gate circuit 12 is at a high level from the time t0 when the differential signal for detection is output to the time t1 when the reflected wave reaches the output side. The waveform of the output of the AND gate circuit 12 is C. The pulse width of the waveform C (the width of the high-level signal, that is, from time t0 to t1) is the time required for the signal to reciprocate through the detection cable 8.

The signal amplitude circuit 13 detects the cable length of the signal cable 500 based on the detection result of the reflected wave, and forms a cable length signal based on the detection result. That is, the pulse width is proportional to the length of the detection cable 8 (that is, the length of the signal cable 500). Since the period of the waveform A output from the detection output circuit 7 is constant, the waveform C is integrated (smoothed) by the integration circuit 13 so that the voltage corresponding to the length of the detection cable 8 is integrated as a cable length signal. Output from the circuit 13. Based on the cable length signal, the signal forming means 16 forms an amplitude control signal and inputs it to the amplitude setting circuit 3. Amplitude setting circuit 3
Sets the amplitude of the differential signal output from the output circuit 2 based on the amplitude control signal. The output circuit 2 has a set amplitude of L
It outputs a low-voltage differential signal according to the VDS interface.

FIG. 4 is a block diagram of an information processing apparatus, showing an example of an information processing apparatus 200 having an LVDS interface signal amplitude setting function of the present invention. FIG. 6 is a waveform chart in the information processing apparatus 200 shown in FIG.

The reflected wave generation circuit 9 in the information processing apparatus 200 shown in FIG. 4 is constructed by opening the other end of the detection cable 8. Other configurations are the same as those of the information processing apparatus 200 shown in FIG. That is, this is an example in which the input impedance of the reflected wave generation circuit 9 is infinite.

As shown in FIG. 6, the information processing device 2 shown in FIG.
In the same manner as in the case of 00, the detection output circuit 7 outputs the differential signal of the waveform B in response to the input of the input signal of the waveform A.
Output to the top. Since the input impedance of the reflected wave generation circuit 9 is infinite due to opening, the waveform of the reflected wave in the reflected wave generation circuit 9 has the same phase as the original waveform B and proceeds to the detection output circuit 7 side. At this time, unlike the information processing apparatus 200 of FIG. 3, the reflected wave travels in the opposite direction on the cable through which the differential signal has been transmitted. The detection cable 8 proceeds in reverse, and at time t2, the detection output circuit 7
The reflected wave which has arrived at the detection output circuit 7 does not cause re-reflection because its output impedance is the same as the characteristic impedance of the detection cable 8. That is,
The output waveform B of the detection output circuit 7 and the waveform of the reflected wave have the same phase. Therefore, as shown in FIG. 5, at time t2, the waveform B has a wave height that is about twice the original differential signal.

As shown in FIG. 4, the inverted input terminal and the non-inverted input terminal of the reflected wave detection circuit 10
Are connected to the side connected to the non-inverted output terminal and the inverted output terminal of the detection output circuit 7 in the pair. That is, the connection is reverse to that of the information processing apparatus 200 in FIG. Further, the reflected wave detection circuit 10 has a threshold value Vth2 of an intermediate potential between the original waveform B output from the detection output circuit 7 and a double peak value thereof.

Accordingly, the reflected wave detection circuit 10 starts outputting a high level signal when the differential signal which is a reflected wave generation signal is output from the detection output circuit 7 and the output is smaller than the threshold value Vth2. When the output becomes a double peak value due to the influence of the wave and the output becomes larger than the threshold value Vth2, the output of the high-level signal is stopped (the output of the low-level signal is started). As a result, the output of the AND gate circuit 12 is set to a high level from the time t0 when the differential signal for detection is output to the time t2 when the reflected wave reaches the output side, as shown as a waveform C. You. Thereafter, similarly to the information processing apparatus 200 in FIG. 3, a cable length signal is formed, and the amplitude of the differential signal of the output circuit 2 is set based on the cable length signal.

FIG. 7 is a block diagram of the information processing apparatus, showing another example of the information processing apparatus 200 having the LVDS interface signal amplitude setting function of the present invention.

The reflection time detection circuit 12A in this example
Consists of, for example, a counter. This counter 12A
The counting of time is started in response to the (high level) input of the reflected wave generation signal having the waveform A, and the counting of time is stopped in response to the input of the reflected wave output from the reflected wave detection circuit 10. For example, the clock of the CPU of the information processing device 200 is used for counting the time. This allows
From the time t0 to the time t1 or t2, that is, the reflection time is detected.

The signal amplitude circuit 13 A in this example is realized by executing a program for executing a cable length signal forming process in the CPU of the information processing apparatus 200. This program is stored in the memory of the information processing device 200. This program, ie, the signal amplitude circuit 13
A includes a cable length detection / signal amplitude table (not shown) in the memory. The signal propagation time per unit length of the detection cable 8 can be known in advance. Therefore, the cable length of the detection cable 8 can be obtained from the above and the reflection time. Therefore, the cable length detection / signal amplitude table stores the cable length of the detection cable 8 for each reflection time, and further stores the corresponding voltage value for each cable length. The signal amplitude circuit 13A includes a counter 12A
And the corresponding cable length is determined by referring to the table using the reflection time given by the controller, and a voltage value corresponding to the cable length is output as a cable length signal.
When the cable length signal is an analog signal, the signal forming circuit 16 has the same configuration as the information processing device 200 in FIG. 3, and when the cable length signal is a digital signal, the AD conversion circuit 17 can be omitted.

FIGS. 8 and 9 show an example in which the length of the signal cable 500 is detected on the liquid crystal display device side where the input circuit 5 is provided.

FIG. 8 is a block diagram of the information processing apparatus, showing another example of the information processing apparatus 200 having the LVDS interface signal amplitude setting function of the present invention.

In FIG. 8, an amplifying circuit 19 is used as means for forming a cable length signal (cable length signal forming circuit).
And a smoothing circuit 20. The cable length signal forming circuit detects the amplitude of the differential signal output from the output circuit 2 at the other end of the signal cable 500, and forms a cable length signal based on the detection result. The amplifying circuit 19 detects a signal attenuated by being transmitted through the signal cable 500, amplifies the signal appropriately, and the smoothing circuit 20 smoothes (averages) the signal. Since the amount of attenuation is proportional to the length of the signal cable 500, a voltage corresponding to the length of the detection cable 8 is output from the smoothing circuit 20 by smoothing the attenuated signal. This voltage is input to the signal forming circuit (voltage control resistance variable circuit) 16 as a cable length signal.

FIG. 9 is a block diagram of the information processing apparatus, showing another example of the information processing apparatus 200 having the LVDS interface signal amplitude setting function of the present invention.

In FIG. 9, a detection cable 22, a power supply 21 and a resistor 23 are provided as means for forming a cable length signal (cable length signal forming circuit). The detection cable 22 has the same length as the signal cable 500, but includes a single signal line. The power supply 21 is connected to one end of the detection cable 22 and applies a predetermined voltage to this. The voltage of the power supply 21 is set to a value (for example, several volts) sufficiently larger than the amplitude (for example, 200 mV) of the signal according to the LVDS interface. The resistor 23 is connected between one end of the detection cable 22 and the ground potential. That is, the cable length signal forming circuit of this example includes the detection cable 22, the power supply 21, and the resistor 23. A signal cable 50 is connected to the connection point between the resistor 23 and the detection cable 22.
By transmitting 0, a voltage drop appears.
Since the amount of the voltage drop is proportional to the length of the signal cable 500, a voltage corresponding to the length of the detection cable 22 can be obtained by detecting the potential of the connection point. The voltage at the other end of the detection cable 22 is input as a cable length signal to the signal forming circuit (variable voltage control resistance circuit) 16.

8 and 9, the cable length signal may be converted into a digital signal in advance and then input to the signal forming circuit (variable voltage control resistor circuit) 16. That is, the output of the smoothing circuit 20 or the terminal voltage of the resistor 23 may be converted into a digital signal by an AD conversion circuit (not shown) and supplied to the voltage control resistance variable circuit 16. In this case, the AD conversion circuit 17 constituting the signal forming circuit 16 is omitted.

FIGS. 10 and 11 show frequency setting for setting the frequency of the low-voltage differential signal output from the output circuit 2 based on the detection result of the cable length of the signal cable 500 instead of the amplitude setting circuit 3. This is an example in which a circuit 24 is provided.

FIG. 10 is a block diagram of an information processing apparatus, showing an example of an information processing apparatus 200 having an LVDS interface signal frequency setting function of the present invention.

The information processing apparatus 200 shown in FIG. 10 includes a frequency setting circuit 24 for setting the frequency of the differential signal output from the output circuit 2 and a signal cable 5 for setting the frequency.
A cable length signal detecting circuit for detecting a cable length of 00 (cable length signal forming circuit); and a signal forming unit 16A for forming a frequency control signal based on the cable length signal. The frequency setting circuit 24 sets the frequency of the low-voltage differential signal output from the output circuit 2 based on the frequency control signal. The information processing apparatus 200 in FIG. 10 has a configuration substantially the same as that of the information processing apparatus 200 in FIG. That is, a frequency setting circuit 24 is provided instead of the amplitude setting circuit 3. The cable length signal forming circuit includes an amplifier circuit 19 and a smoothing circuit 20. The output (voltage) of the smoothing circuit 20 is input to the signal forming means 16A as a cable length signal.
The signal forming means 16A has the same configuration as the signal forming means 16, and forms a frequency control signal having a voltage value according to the cable length signal. The frequency setting circuit 24 includes, for example, a voltage control frequency variable circuit. The frequency setting circuit 24 forms a signal having a frequency corresponding to the frequency control signal and inputs the signal to the means circuit 2.

FIG. 11 is a block diagram of the information processing apparatus, showing another example of the information processing apparatus 200 having the LVDS interface signal amplitude setting function of the present invention.

The information processing apparatus 200 shown in FIG. 11 has substantially the same configuration as the information processing apparatus 200 shown in FIG. That is, power supply 2
1. A cable length signal forming circuit including a detection cable 22 and a resistor 23 is provided. The terminal voltage of the resistor 23 is input to the signal forming unit 16A as a cable length signal.
Thus, the frequency control signal having the voltage value corresponding to the cable length signal is input to the frequency setting circuit 24, and the frequency control signal is formed.

In each of the examples shown in FIGS. 10 and 11, the cable length signal may be converted into a digital signal before being input to the signal forming means 16A. That is, the output of the smoothing circuit 20 or the terminal voltage of the resistor 23 may be converted into a digital signal by an AD conversion circuit (not shown) and supplied to the signal forming unit 16A. In this case, the AD conversion circuit (1
7) is omitted.

[0059]

As described above, according to the information processing apparatus of the present invention, the output circuit is provided by providing the means for detecting the cable length of the signal cable and forming the amplitude control signal based on the detection result. Can automatically set the amplitude of the differential signal to be output to a value corresponding to the cable length of the signal cable, eliminating the need for humans to set the amplitude based on the cable length. And the possibility of erroneously determining the amplitude can be eliminated. Further, according to the information processing apparatus of the present invention, since a signal having an optimum amplitude according to the cable length is output, it is possible to prevent a signal having a voltage amplitude larger than necessary from being output, and satisfy environmental standards. Can be prevented.

[Brief description of the drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is an explanatory diagram of an information processing apparatus.

FIG. 3 is a configuration diagram of an information processing apparatus.

FIG. 4 is a configuration diagram of an information processing apparatus.

FIG. 5 is a detection waveform diagram.

FIG. 6 is a detection waveform diagram.

FIG. 7 is a configuration diagram of an information processing apparatus.

FIG. 8 is a configuration diagram of an information processing apparatus.

FIG. 9 is a configuration diagram of an information processing apparatus.

FIG. 10 is a configuration diagram of an information processing apparatus.

FIG. 11 is a configuration diagram of an information processing apparatus.

FIG. 12 is an explanatory diagram of a conventional information processing apparatus.

[Explanation of symbols]

 Reference Signs List 2 output circuit 3 amplitude setting circuit 5 input circuit 6 detection means 7 detection output circuit 8 detection cable 9 reflected wave generation circuit 10 reflected wave detection circuit 11 cable length signal formation circuit 12 reflection time detection circuit 13 signal amplitude circuit 16 signal formation Means 200 Information processing device 300 Liquid crystal display device 500 Signal cable

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Masaki Utsunomiya 98, Unoki-nu, Unoki-cho, Kawakita-gun, Ishikawa Pref. No. 2 Inside PFU Co., Ltd. (72) Inventor Yuji Ishikawa 98 Uno Ki Nu, Unoki-cho, Kawakita-gun, Ishikawa Pref. F-term (reference) 2H093 NC21 NC52 ND33 NE07 5C006 AA01 AF46 AF51 AF61 AF81 BF16 BF25 BF38 BF43 FA18

Claims (8)

[Claims] 1. An L signal, which is a video data signal for a liquid crystal display device, is connected to one end of a pair of signal cables whose other ends are connected to a liquid crystal display device.
An information processing apparatus comprising: an output circuit that outputs a low-voltage differential signal according to a VDS interface; and an amplitude setting circuit that sets an amplitude of the differential signal output by the output circuit. The cable length of the signal cable is detected. Detecting means for forming a cable length signal corresponding to the detected cable length; andsignal forming means for forming an amplitude control signal based on the cable length signal from the detecting means. An information processing apparatus having an LVDS interface signal amplitude setting function, wherein an amplitude of a differential signal output from the output circuit is set based on an amplitude control signal from a signal forming unit. 2. The detecting means, comprising: a pair of detection cables having the same length as the signal cable; and one end connected to one end of the detection cable for generating a reflected wave on the detection cable. A detection output circuit that outputs a predetermined low-voltage detection differential signal, a reflected wave generation circuit that is provided at the other end of the detection cable, and that generates a reflected wave with respect to the detection differential signal; A reflected wave detection circuit provided at one end of a detection cable, for detecting a reflected wave generated in the reflected wave generation circuit; and a cable for forming a cable length signal based on a detection result of the reflected wave in the reflected wave detection circuit 2. The information processing apparatus according to claim 1, comprising a long signal forming circuit. 3. The LVDS interface signal amplitude setting according to claim 2, wherein the reflected wave generating circuit is configured such that the other ends of the pair of detection cables are opened or short-circuited to each other. Information processing device with functions. 4. The signal forming means comprises a voltage-controlled variable resistance circuit for forming a control signal, and the cable length signal forming circuit detects the reflected wave after the detection differential signal is output. A reflection time detection circuit for detecting a reflection time until the reflection time, based on the reflection time detected by the reflection time detection circuit,
3. The L according to claim 2, further comprising a cable length detection / signal amplitude circuit for forming the cable length signal.
An information processing device having a VDS interface signal amplitude setting function. 5. A cable length signal forming unit for detecting, at the other end of the signal cable, an amplitude of a differential signal output from the output circuit, and forming a cable length signal based on a result of the detection. 2. The information processing apparatus according to claim 1, wherein the information processing apparatus comprises a circuit. 6. The detection means comprises: a single detection cable having the same length as the signal cable; and a power supply connected to one end of the detection cable and applying a predetermined voltage thereto. The voltage drop at the other end of the single detection cable is output as a cable length signal.
An information processing apparatus comprising the LVDS interface signal amplitude setting function according to item 1. 7. An LVDS for setting an amplitude of a low-voltage differential signal output on a pair of signal cables connected to a liquid crystal display device and conforming to an LVDS interface, which is a video data signal for the liquid crystal display device. An interface signal amplitude setting method, comprising: outputting a predetermined low-voltage detection differential signal for generating a reflected wave on a pair of detection cables having the same length as the signal cable; Generating a reflected wave for the detection differential signal on the detection cable, detecting the generated reflected wave, and forming a cable length signal corresponding to the cable length based on a result of the detection of the reflected wave; An LVDS interface comprising: forming an amplitude control signal based on a cable length signal; and setting an amplitude of the differential signal based on the amplitude control signal. Base signal amplitude setting method. 8. An LVDS which is connected to one end of a signal cable whose other end is connected to a liquid crystal display device, and which is a video data signal for the liquid crystal display device on the signal cable.
An information processing apparatus comprising: an output circuit that outputs a low-voltage differential signal according to an interface; and a frequency setting circuit that sets a frequency of the differential signal output by the output circuit, wherein a cable length of the signal cable is detected. Detecting means for forming a cable length signal according to the detected cable length, and signal forming means for forming a frequency control signal based on the cable length signal from the detecting means; An information processing apparatus having an LVDS interface signal frequency setting function, wherein the frequency of a differential signal output from the output circuit is set based on a control signal.