JP2000181567A - Four-phase clock signal preparation system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily prepare a four-phase clock signal with a compact circuit configuration. SOLUTION: In the four-phase clock signal preparation system 1, according to a preset program 4, a CPU 3 outputs a signal when the count value of clock signals of an oscillator 2 by a counter 5 becomes a preset comparative value and corresponding to the output from this counter 5, pattern data stored in a memory 6 are selectively read out and outputted to an external interface 8 by a direct memory access controller 7. The external interface 8 outputs the pattern data outputted from the direct memory access controller 7 to the outside as a four-phase clock signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention belongs to the technical field of a four-phase clock signal generating system in which, for example, an ultrasonic motor is used in a drive control circuit or the like.

[0002]

2. Description of the Related Art Conventionally, as a driving device for driving an ultrasonic motor, a driving device using a four-phase clock signal has been proposed, for example, in Japanese Patent Application Laid-Open No. 2-36778. In the ultrasonic motor driving device disclosed in this publication, a sawtooth wave is output from an oscillator controlled by an arithmetic circuit unit, and the sawtooth wave is converted into a four-phase rectangular wave that is time-shifted by a distributor. These four-phase rectangular waves are amplified and input to an output transformer. The output transformer outputs voltages of a pseudo sine wave and a pseudo cosine wave. The ultrasonic motor is supplied to the motor to drive the ultrasonic motor.

[0003]

In such a conventional ultrasonic motor driving apparatus, a four-phase clock signal is used to generate a voltage to be supplied to the ultrasonic motor by an output transformer. . The four-phase clock signal is provided in the ultrasonic motor driving device.
It is created by an arithmetic circuit unit, an oscillator, a distributor, and the like.

However, the use of such a large number of components as the arithmetic circuit section, the oscillator, and the distributor complicates the circuit of the ultrasonic motor driving device. Further, the use of a large number of components makes the ultrasonic motor driving device expensive.

The present invention has been made in view of such circumstances, and an object of the present invention is to provide a compact circuit configuration.
An object of the present invention is to provide an inexpensive four-phase clock signal generation system that can easily generate a phase clock signal.

[0006]

According to a first aspect of the present invention, there is provided a four-phase clock signal generating system for generating a four-phase clock signal. And a central processing unit for outputting a four-phase clock signal in accordance with a predetermined clock pattern based on the oscillation signal.

Further, the invention according to claim 2, wherein the central processing unit counts based on the oscillation signal, and outputs when the count value reaches a preset comparison value.
A program for storing data of a predetermined clock pattern for generating the four-phase clock signal, a program for controlling the counter, and a clock pattern for selecting and outputting a predetermined clock pattern based on an output signal from the counter It is characterized by comprising output means and an external interface for outputting a clock pattern output from the clock pattern output means as a four-phase clock signal to the outside.

Further, according to a third aspect of the present invention, at least two first and second counters that count in synchronization with each other are provided as the counter, and the comparison value is set in the first counter. And two other comparison values consisting of a variable value set in the second counter, and two clocks as data of the predetermined clock pattern. First data comprising a pattern and second data comprising two other clock patterns are provided, and the clock pattern output means outputs two clocks of the first data from the first counter. A first clock pattern for outputting to the external interface a clock pattern corresponding to the output of the first counter among the patterns; Output means and second clock pattern output means for outputting, to the external interface, a clock pattern corresponding to the output of the second counter among the two clock patterns of the second data, based on the output from the second counter. It is characterized by having.

[0009]

In the four-phase clock signal generating system according to the present invention, the central processing unit includes
A four-phase clock signal can be easily created using a predetermined clock pattern based on the oscillation signal from the oscillator. In this case, the counter, clock pattern output means and external interface built in the central processing unit, and the program software constitute a four-phase clock signal generation system, so that the circuit configuration of the system becomes extremely compact.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a basic configuration of a four-phase clock signal generation system according to the present invention.

As shown in FIG. 1, a four-phase clock signal generating system 1 according to the present invention includes an oscillator 2 for outputting a clock signal α having a constant period, and a clock signal from the oscillator 2 according to a predetermined program. And a central processing unit (hereinafter also referred to as a CPU) 3 which outputs a four-phase clock signal based on the stored four-phase pattern data in accordance with the count value. C
RO3 for creating a four-phase clock signal in PU3
The clock signal of the oscillator 2 is counted by the program 4 consisting of M and the counter set value of the program 4 and the count control signal β. When the count value becomes a comparison value set in advance by the program 4, the count is incremented. A counter 5 for outputting a signal γ, and a program 4
Of the clock pattern data and comparison value of the comparison value δ
And the pattern data .epsilon. Of the memory 6 corresponding to the count-up signal .gamma. From the counter 5 is read. 4
The data is output as the phase clock generation pattern data signal ζ, and the updated value of the comparison value stored in the memory 6 is fetched into the buffer by the comparison value data signal η from the program 4 and the count-up signal γ of the counter 5 The comparison value writing signal θ for writing the comparison value data in the buffer to the comparison value of the counter 5
, And an external interface (hereinafter, I / O) that outputs the 4-phase clock generation pattern data signal ζ from the DMA 7 to the outside of the CPU 3 as a 4-phase clock signal ι. 8). That is, in the CPU 3, the counter 5, the DMA 7, and the I / O
A peripheral unit having a function other than the arithmetic operation consisting of O8 is built in.

In the four-phase clock signal generating system 1 configured as described above, the CPU 3 determines the peripheral unit of the CPU 3 based on the count value of the clock signal from the oscillator 2 in accordance with the preset program 4. A four-phase clock signal having the following pattern is created.

Next, a specific embodiment of the four-phase clock signal generation system 1 for generating a four-phase clock signal will be described. FIG. 2 is a diagram showing a specific embodiment of the four-phase clock signal generation system 1 of the present invention.

As shown in FIG. 2, the four-phase clock signal generating system 1 of this embodiment is provided with two counters ITU-A and ITU-B as the counter 5.
ITU-A is provided with a comparison value A and a comparison value B, and ITU-B is provided with a comparison value C and a comparison value D. Also, the ITU-A count value and the ITU-A
The count value of B is synchronized and always equal to each other.

The memory 6 stores two data A and B for a four-phase clock signal. The data A includes two patterns A and C, and the data B includes two patterns A and B. It consists of patterns B and D. Pattern A
Indicates that Bit0 is “1”, Bit1 is “0”, Bit2 is “0”, Bit3
Are data of (0001) consisting of “0”, pattern C is also data of (0010), pattern B is also data of (0100), and pattern D is data of (1001). It is.

Further, the DMA 7 has three controllers D
MA-A, DMA-B and DMA-C, and a buffer is provided in DMA-C.
The other configuration of the four-phase clock signal generation system 1 of this embodiment is the same as the basic configuration shown in FIG.

Next, generation of a four-phase clock signal by the four-phase clock signal generation system 1 configured as described above will be described. The generation of the four-phase clock signal is performed according to a predetermined sequence.

FIG. 3 is a timing chart used for generating a four-phase clock signal by the CPU 3 of this embodiment.
Referring to FIG. 3, first, each of the comparison values A, B, C, and D will be described. The comparison value A of ITU-A is set to 0, and the comparison value B is the count value of ITU-A in the four-phase clock signal generation sequence. It is set to a relatively large value that is impossible. Also, the comparison value D of ITU-B is set to the maximum value that is smaller than the comparison value B but counted in the four-phase clock signal generation sequence, and the comparison value C is set to half the comparison value D. I have. In that case, the comparison values A and B are fixed values, and the comparison values C and D are variable values.
The comparison value D determines the cycle of the four-phase clock signal, and is therefore determined based on the cycle of the clock signal to be created. It is needless to say that the comparison value A does not necessarily need to be set to 0 and can be set to an arbitrary value. However, in the following description, the comparison value A is 0.
The description will be made assuming that the setting has been made.

When the ROM of the program 4 is set in the CPU 4 and the four-phase clock signal generating system 1 is started, each information contained in the program 4 is supplied to each part of the CPU. That is, the data of the comparison value A (set to 0 in this embodiment) and B of the program 4 are supplied to the comparison values A and B of the ITU-A by the counter setting value signal β, and the ITU is output by the comparison value data signal η. The data of the comparison values C and D of -B is DMA-C
Buffer. Further, the updated values of the patterns A and C of the data A of the program 4, the patterns B and D of the data B and the updated value of the comparison value C are stored in the memory 6 according to the clock pattern data and the updated value signal δ of the comparison value.

Further, the clock signal α of the oscillator 2 is
-A and ITU-B respectively. The ITU-A and ITU-B both start counting from "0" in response to the count control signal β from the program 4.
At this time, since ITU-A and ITU-B are synchronized with each other as described above, the respective count values are equal to each other.

As shown in FIG. 3, when the count value of the ITU-A becomes the comparison value A, that is, in this embodiment, since the comparison value A is set to "0", the counting by the ITU-A starts at the same time. Signal γ is DMA from ITU-A
-A is output. Then, the DMA-A is activated and D-
MA-A reads pattern A of data A in memory 6 based on signal ε. At the same time, DMA-C is activated,
The signal θ causes the DMA-C to transmit the ITU-
The comparison value data of the comparison values C and D of B are read, and these data are written to the comparison values C and D of ITU-B, respectively. As shown in FIG. 3, when the count value of ITU-B becomes the comparison value C set to one half of the comparison value D, DMA-B is started, and DMA-B is stored in the memory 6 based on the signal ε. The pattern B of the data B is read.

When the count value of ITU-B reaches the comparison value D for determining the period of the four-phase clock signal as shown in FIG.
Are cleared and set to "0" again.
Both ITU-A and ITU-B start counting again from "0". At the same time, the DMA-A outputs the read data of the pattern A to the I / O 8 according to the signal ζ. Then, the I / O 8 converts the data of the pattern A (0001) into the four-phase clock signal ι as shown in each bit of FIG.
And output to the outside.

Further, as shown in FIG. 3, simultaneously with the start of the re-counting of the ITU-A, the DMA-A is started again,
The DMA-A reads out the data of the pattern C of the data A in the memory 6. At the same time, DMA-C is activated again and D
The MA-C reads again the comparison value data of the comparison values C and D of ITU-B in the buffer, and
Write the comparison values C and D of B. When the count value of ITU-B again becomes the comparison value C as shown by in FIG.
MA-B is activated again, and DMA-B reads pattern D of data B in memory 6. At the same time, the DMA-A outputs the read data of the pattern B to the I / O 8. Then, the I / O 8 outputs the data of the pattern B (0100) as shown in each Bit of FIG.
And output to the outside.

Further, when the count value of ITU-B again becomes the comparison value D, as shown in FIG. 3, the count values of ITU-A and ITU-B are cleared again and set to "0", and ITU-B A and ITU-B are both "0"
Start counting from. At the same time, the DMA-A outputs the read data of the pattern C to the I / O 8. Then, the I / O 8 outputs the data of the pattern C (0010) to the outside as the four-phase clock signal ι as shown in each bit of FIG.

Further, as shown in the second part of FIG.
Simultaneously with the start of the re-counting of the UA, the DMA-A is started again, and the DMA-A reads out the data of the pattern A of the data A in the memory 6 again. At the same time, the DMA-C is activated again, and the DMA-C reads out the comparison value data of the comparison values C and D of the ITU-B in the buffer again, and writes the comparison value data of the comparison values C and D of the ITU-B, respectively. When the count value of ITU-B again becomes the comparison value C as indicated by the symbol on the second surface in FIG.
-B reads the pattern B of the data B in the memory 6.
At the same time, the DMA-B outputs the read data of the pattern D to the I / O 8. Then, the I / O 8 outputs the data of the pattern D (1000) to the outside as the four-phase clock signal ι, as shown in each bit of FIG. Thereafter, the same operation is repeated.

Thus, the CPU 3 returns to FIG.
By repeatedly operating at the timing of →→→→→→→..., Four-phase clock signals are continuously output as shown in each Bit of FIG. At this time, from the output of the four-phase clock signal of pattern A to the output of the next four-phase clock signal of pattern A, that is, from the output of the clock signal of pattern A to the end of the clock signal of pattern D, One cycle (cycle) of the four-phase clock signal is provided. This one cycle is determined by the comparison value D.

Note that even if the ITU-A and ITU-B are not synchronized, the count value of ITU-A is not cleared even if the count value of ITU-B becomes the comparison value D for some reason. If A continues to count,
When the count value of ITU-A reaches the comparison value B, IT
The count value of UA is cleared.
This prevents one count of ITU-A from becoming unnecessarily long.

As described above, according to the four-phase clock signal generating system of this embodiment, the peripheral unit and the software built in the CPU 3 can perform the four-phase clock signal generation without the need for the above-described components such as the distributor.
The phase clock signal can be easily created with a compact circuit configuration.

FIG. 4 shows another embodiment of the present invention.
FIG. In the embodiment shown in FIG.
The U3 incorporates two ITUs and three DMAs, and the pattern data of the four-phase clock signal is divided into two. In this embodiment, only one ITU5 and one DMA7 are incorporated in the CPU 3, respectively. The circuit configuration is further compacted by combining the pattern data into one.

That is, as shown in FIG. 4, in the four-phase clock signal generating system 1 of this embodiment, one
One ITU5 is provided and this ITU5
Are provided with a comparison value E (corresponding to the comparison value A in the above-described embodiment), a comparison value F (also corresponding to the comparison value D), and a buffer. The memory 6 of the CPU 3 stores one data for a four-phase clock signal. This data is composed of four patterns A, B, C, and D, and these patterns A, B, C, and D are the same as the patterns of the above-described embodiment. Further, one DMA 7 is provided in the CPU 3. Other configurations of the four-phase clock signal generation system 1 of this embodiment are the same as those of the embodiment shown in FIG.

Next, generation of a four-phase clock signal by the four-phase clock signal generation system 1 configured as described above will be described. The generation of the four-phase clock signal is performed according to a predetermined sequence, similarly to the above-described embodiment.

FIG. 5 is a timing chart used for generating a four-phase clock signal by the CPU 3 of this embodiment.
Referring to FIG. 5, first, each of the comparison values E and F will be described. The comparison value E is a fixed value set to 0 similarly to the comparison value A of the above-described embodiment, and is built in the ITU 5 in advance. Further, the comparison value F determines the cycle of the four-phase clock signal similarly to the comparison value D of the above-described embodiment, and is a variable value.

When the ROM of the program 4 is set in the CPU 4 and the four-phase clock signal generating system 1 is started, the information contained in the program 4 is stored in each part of the CPU, as in the above-described embodiment. Supplied to That is, the ITU stored in the program 4
The data of the comparison value F of 5 is supplied to the buffer of ITU5. Further, four patterns A, B, C, and D of the data of the program 4 are stored in the memory 6, respectively.

Further, the clock signal α of the oscillator 2 is ITU
5 is input. In response to the count control signal β from the program 4, the ITU 5 starts counting from “0”, reads the comparison value data in the buffer, and writes this data to the comparison value F. Also, similarly to the above-described embodiment, the DMA 7 is started simultaneously with the start of the counting, and
The MA 7 reads the pattern A of the data in the memory 6.
When the count value of ITU5 becomes the comparison value F that determines the period of the four-phase clock signal, as shown in FIG.
Is cleared and set to “0” again,
TU5 starts counting again from "0". At the same time, the DMA 7 converts the read data of the pattern A into I / O data.
8 is output. Then, the I / O 8 outputs the data of the pattern A (0001) to the outside as the four-phase clock signal ι as shown in each bit of FIG.

Further, as shown in FIG. 5, simultaneously with the start of the re-counting of the ITU 5, the DMA 7 is started again, and the DM 7 is started.
A7 reads the pattern B of the data in the memory 6. When the count value of ITU5 becomes the comparison value F again as shown by in FIG. 5, the count value of ITU5 is cleared again and set to "0", and ITU5 starts counting again from "0". At the same time, the DMA 7 outputs the read data of the pattern B to the I / O 8. Then I / O8
Is a pattern B (010) as shown in each Bit of FIG.
0) is output to the outside as a four-phase clock signal ι.

Further, as shown in FIG. 5, simultaneously with the start of the re-counting of the ITU 5, the DMA 7 is started again and the DM 7 is started.
A7 reads the pattern C of the data in the memory 6. When the count value of ITU5 becomes the comparison value F again as shown by in FIG. 5, the count value of ITU5 is cleared again and set to "0", and ITU5 starts counting again from "0". At the same time, the DMA 7 outputs the read data of the pattern C to the I / O 8. Then I / O8
Represents a pattern C (001) as shown in each Bit of FIG.
0) is output to the outside as a four-phase clock signal ι.

Further, as shown in FIG. 5, simultaneously with the start of the re-counting of the ITU 5, the DMA 7 is started again, and the DM 7 is started.
A7 reads the data pattern D in the memory 6. As shown in FIG. 5, when the count value of ITU5 becomes the comparison value F again, the count value of ITU5 is cleared again and set to "0", and ITU5 starts counting again from "0". At the same time, the DMA 7 outputs the read data of the pattern D to the I / O 8. Then I / O8
Represents a pattern D (100) as shown in each Bit of FIG.
0) is output to the outside as a four-phase clock signal ι. Thereafter, the same operation is repeated.

Thus, the CPU 3 returns to FIG.
By repeatedly operating at the timing of →→→→→→→→→..., Each Bit shown in FIG.
As shown in FIG. 7, four-phase clock signals are continuously output. At this time, from the output of the four-phase clock signal of pattern A to the output of the next four-phase clock signal of pattern A, that is, from the output of the clock signal of pattern A to the end of the clock signal of pattern D, This 4
One cycle of the phase clock signal. And
This one cycle is determined by the comparison value F.

As described above, according to the four-phase clock signal generation system of this embodiment, the four-phase clock signal can be easily generated with a compact circuit configuration by using the peripheral unit and software built in the CPU 3. Become.

The four-phase clock signal generating system of the present invention can be applied to any system or apparatus that requires a four-phase clock signal, including the above-described ultrasonic motor drive circuit.

[0041]

As is apparent from the above description, according to the four-phase clock signal generation system of the present invention, the four-phase clock signal is generated by the central processing unit using the predetermined clock pattern based on the oscillation signal from the oscillator. A clock signal can be easily created.

Further, a four-phase clock signal generating system is
Since it is composed of the counter, clock pattern output means and external interface built in the central processing unit and the program software, the circuit configuration of the system can be made extremely compact.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic configuration of a four-phase clock signal generation system according to the present invention.

FIG. 2 is a diagram showing a specific example of a four-phase clock signal generation system according to the present invention.

FIG. 3 is a timing chart used for generating a four-phase clock signal by the central processing unit of the embodiment shown in FIG. 2;

FIG. 4 is a diagram showing another specific embodiment of the four-phase clock signal generation system of the present invention.

FIG. 5 is a timing chart used for generating a four-phase clock signal by the central processing unit of the embodiment shown in FIG. 2;

[Explanation of symbols]

1. Four-phase clock signal generation system 2. Oscillator 3.
Central processing unit (CPU), 4 programs (ROM),
5 ... Counter (ITU), 6 ... Memory (RAM), 7 ...
Direct memory access controller (DMA), 8
… External interface (I / O)

Claims (3)

[Claims] 1. A four-phase clock signal generating system for generating a four-phase clock signal, comprising: an oscillator that outputs a constant oscillation signal; and a central unit that outputs a four-phase clock signal according to a predetermined clock pattern based on the oscillation signal. And a processing device.
Phase clock signal creation system. 2. The counter according to claim 1, wherein said central processing unit counts based on said oscillation signal, and outputs a counter when a count value reaches a predetermined comparison value, and a predetermined clock pattern for generating said four-phase clock signal. Data stored therein, a program for controlling the counter, and clock pattern output means for selecting and outputting a predetermined clock pattern based on an output signal from the counter,
2. The four-phase clock signal generation system according to claim 1, further comprising an external interface for outputting a clock pattern output from the clock pattern output means as a four-phase clock signal to the outside. 3. At least two first and second counters that count in synchronization with each other are provided as the counter, and the first and second counters are used as the comparison value.
Two comparison values consisting of a fixed value set in the counter and two other comparison values consisting of a variable value set in the second counter are provided. As the data of the predetermined clock pattern, First data composed of two clock patterns and second data composed of the other two clock patterns are provided, and the clock pattern output means outputs the first data by the output from the first counter. A first clock pattern output unit for outputting a clock pattern corresponding to the output of the first counter to the external interface, and an output from the second counter; A second clock for outputting a clock pattern corresponding to the output of the second counter to the external interface; 4-phase clock signal generation system according to claim 2, characterized in that it comprises a Kkupatan output means.