JPH04235616A - Clock generator - Google Patents

Abstract

PURPOSE:To generate plural clock signals having no relation of the integer multiple with each other with use of e single oscillator by writing an optional numerical value into a programmable divider. CONSTITUTION:A crystal oscillator 1 is oscillated with e frequency of 0.259MHz, i.e., a common pultiple between 9600Hz and 10368Hz, for instance, of the frequency of a necessary clock signal. An n-bit divider 2 divides the oscillation signal inputted from the oscillator 1 based on the numerical value written previously. An n-bit latch 3 writes an optional numerical value into the divider 2, and this numerical value is inputted from a CPU through a data bus of (n = 5). Furthermore a control signal is inputted from the CPU so that the numerical value inputted from the CPU can be held.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation device, and is used, for example, in a modem device for a facsimile machine.

0002

2. Description of the Related Art For example, in a modem device for a facsimile machine, 10368 Hz for G2 mode and G
A 9600 Hz clock for three modes is generated. In this case, as shown in FIG.
While generating a 10368Hz clock by
A clock of 9600 Hz was generated by a crystal oscillator 13 having an oscillation frequency that is an integral multiple of 9600 Hz and a frequency divider 14.

0003

However, the conventional device described above has a problem in that it is relatively expensive because two crystal oscillators are required. In view of the above circumstances, the present invention provides a single oscillator that uses multiple clock signals that are not integral multiples of each other (for example, the aforementioned 103 clock signals).
An object of the present invention is to provide a clock generation device capable of generating two clock signals of 68 Hz and 9600 Hz.

0004

[Means for Solving the Problems] In order to solve the above problems, a clock generation device according to the present invention includes an oscillator whose oscillation frequency is a common multiple of the frequencies of a plurality of required clock signals; It is equipped with a programmable frequency divider that divides the oscillation signal input from this oscillator based on a pre-written numerical value, and a numerical value writing means for writing an arbitrary numerical value to this programmable frequency divider. It is a feature.

[0005]

[Operation] According to the above structure, by simply writing an arbitrary value to the programmable frequency divider, one oscillator can generate a plurality of clock signals that are not integral multiples of each other.

[0006]

[Embodiment] An embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a block diagram showing a schematic configuration of a clock generator, in which 1 is a crystal oscillator, 2 is an n-bit frequency divider (programmable frequency divider), and 3 is a crystal oscillator.
is an n-bit latch (numerical writing means).

Since the required clock signal frequencies are, for example, 9600 Hz and 10368 Hz, the crystal oscillator 1 used is one that oscillates at a frequency of 0.2592 MHz, which is a common multiple thereof. The n-bit frequency divider 2 performs frequency division on the oscillation signal input from the crystal oscillator 1 based on a numerical value written in advance.

[0008] The n-bit latch 3 is designed to write an arbitrary value into the n-bit frequency divider 2. The above numerical values are input from a CPU (not shown) through n=5 data buses. Further, by inputting a control signal from the CPU, the above-mentioned numerical value inputted from the CPU at that time is held.

In the above configuration, the numerical value "27" in 5-bit data is input from the CPU to the n-bit latch 3 through the data bus, and the n-bit latch 3 further receives the "27" by inputting a control signal. hold,
This numerical value "27" continues to be supplied to the n-bit frequency divider 2. n-bit frequency divider 2 is 0.2592 from crystal oscillator 1
A MHz oscillation signal is input, and one pulse is output every time 27 signals are counted. This results in 0.25
The 92 MHz oscillation signal is divided into 1/27 and becomes 96 MHz.
A clock of 00Hz is generated.

On the other hand, the numerical value "2" is transmitted through the data bus.
5” is input, and the corresponding value “2” is input by inputting the control signal.
5" is held and this value "25" is supplied to the n-bit frequency divider 2. The n-bit frequency divider 2 divides the frequency by 1 every time it counts 25 0.2592 MHz oscillation signals from the crystal oscillator 1. It starts outputting pulses.As a result, 0.
The 2592 MHz oscillation signal is divided into 1/25,
A 10368Hz clock is generated.

[0011] Therefore, 2 of 10368Hz and 9600Hz
This eliminates the conventional drawback that two crystal oscillators must be provided to generate one clock signal, and the cost of the device can be reduced. In addition,
In this embodiment, two required clock signal frequencies, 9600 Hz and 10368 Hz, are shown, and 0.2592 MHz is shown as a common multiple thereof, but these are just examples, and other frequencies that are integral multiples of each other are shown. There may be no frequency, and other common multiples. Furthermore, the present invention is also applicable to cases where three or more clock signal frequencies are required.

0012

As described above, according to the present invention, a single oscillator can generate a plurality of clock signals that are not integral multiples of each other, thereby reducing costs.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a clock generation device as an embodiment of the present invention.

FIG. 2 is a configuration diagram showing a conventional clock generation device.

[Explanation of symbols]

1 Crystal oscillator 2 n-bit frequency divider 3 n-bit latch

Claims (1)

[Claims] Claim 1: An oscillator whose oscillation frequency is a common multiple of the frequencies of a plurality of required clock signals, and a frequency division based on a pre-written value for the oscillation signal input from this oscillator. 1. A clock generation device comprising: a programmable frequency divider that performs a frequency change; and a numerical value writing means for writing an arbitrary numerical value to the programmable frequency divider.