JPS592904B2 - display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Storage information stored in different address positions in a storage device, configured such that one word has two or more bits, is specified by an address signal from a read address register and read out from the storage device. The information read word by word from the storage device is directly supplied to a parallel-serial converter to convert it into a time series signal, which is then used as a video signal on the display surface (fluorescent surface) of a cathode ray tube. Alternatively, the information read out word by word from the storage device may be converted by a converter such as a so-called character generator or the like and then sent to a parallel-to-serial converter. A scanning display device is a scanning display device that is configured to supply a video signal, convert it into a time-series signal, and display it as a video signal on the display surface of a cathode ray tube as a desired reproduced image. It is extremely effective as a man-machine interface because it enables display in various display formats that match the pattern recognition function of humans.

FIG. 1 shows a conventional example of the above-mentioned scanning display device, in which stored information read word by word from a storage device is immediately applied to a parallel-serial converter to convert it into a time-series signal, and this is transmitted to a cathode ray tube. 1 is a block diagram showing a schematic configuration of a display device configured to supply a clock to a reference clock; in FIG. 5 is a gate circuit, 6 is a horizontal address counter, 7 is a storage device, 8 is a parallel-to-serial converter,
Reference numeral 9 indicates a block having an information writing function including a write information input circuit, a write address register, a write control circuit, and the like. The oscillation wave from the reference clock oscillator 1 is given to the frequency divider 2, and is also given to the parallel-to-serial converter 8 as its time base clock input, and is read word by word from the storage device 7. The oscillation wave from the oscillator 1 of this reference clock is , one period is the horizontal scanning of one pixel in the reproduced image reproduced on the display screen of the cathode ray tube when the time series signal from the parallel-serial converter 8 is supplied to the cathode ray tube as a video signal. It is required that the length in the direction and the corresponding time length be equal.

Note that the horizontal length of one pixel in the reproduced image described above is applied to the horizontal resolution required for the reproduced image to be projected on the display surface of the cathode ray tube and the deflection system of the cathode ray tube. Needless to say, it is determined depending on the criteria of the power scanning method. The frequency divider 2 described above divides the oscillation wave of the reference clock oscillator 1 by an appropriate frequency division ratio, and provides the divided output to the timing generator 3.
Then, a timing pulse to be applied to the horizontal address counter control circuit 4, a memory timing signal to be applied to the storage device 7, a memory read timing signal to be applied to the parallel-to-serial converter 8, etc. are generated. The horizontal address counter 4 generates a gate pulse having a required pulse width from a specific time position with respect to the time position of the horizontal synchronization signal using the timing pulse from the timing generator 3, and operates the gate circuit. 5 so that the oscillation wave (clock pulse) from the reference clock oscillator 1 is applied from the gate circuit 5 to the horizontal address counter 6 during the period of the gate pulse.

The horizontal address counter 6 uses the above-mentioned clock pulses supplied thereto to read the stored information in the storage device 7 corresponding to each picture element arranged in the horizontal direction in the reproduced image to be displayed on the display surface of the cathode ray tube. A horizontal address signal for designating the address position of is generated and applied to the storage device 7. Note that in order to read information at a predetermined address position in the storage device 7, a vertical address signal is required in addition to the above-mentioned horizontal address signal, and this is performed by a vertical address counter. However, in the display device shown in the first diagram, the illustration of the vertical address counter is omitted (this point will be explained later in the circuit shown in the second diagram). The same applies to placement).

In the conventional display device shown in FIG. 1, the stored information sequentially read word by word from the storage device 7 in accordance with the designation of the address signal is supplied to the parallel-to-serial converter 8 from the reference clock oscillator 1. Under the control of the clock pulse, the signal is converted into a time-series signal and sent to the cathode ray tube as a video signal as described above. In order for the image to be displayed on the display screen of the cathode ray tube without disturbance, a horizontal address signal from the horizontal address counter 6 and a horizontal synchronization signal that regulates the operation of the cathode ray tube's deflection system must be used. Since they are required to be maintained in a specific time relationship with each other, the frequency division ratio of the frequency divider 2 that divides the frequency of the oscillation wave of the reference clock oscillator 1 is necessarily the same as that of the reference clock oscillator 1. The frequency division ratio of the frequency divider 2 is always an integer.

Therefore, in the conventional scanning display device shown in FIG. 1, there is a restriction that the reference clock oscillator 1 must have an oscillation frequency value that is an integral multiple of the horizontal scanning frequency value. Therefore, there was a problem in that the time base of the parallel-to-serial conversion operation in the parallel-to-serial converter 8 to which the time base clock is supplied from the reference clock oscillator 1 cannot be arbitrarily set.

According to the present invention, stored information of 2 bits or more read word by word from a storage device in which one word is made up of at least 2 bits is stored at each address, either as is or later via a converter. In a display device in which a time-series signal is obtained from the parallel-to-serial converter by being supplied to a parallel-to-serial converter, the reproduction is reproduced on the display surface of a cathode ray tube by the time-series signal. oscillates at a frequency that has a period of horizontal scanning time for one pixel in the image, and
An externally controllable start/stop oscillator is provided, and the output from the start/stop oscillator is frequency-divided to provide a horizontal address signal for the storage device.
A scanning display device (hereinafter simply referred to as a display device) in which the parallel-to-serial conversion operation of the parallel-to-serial converter is regulated by the output of the start-stop oscillator described above solves the problems in the conventional device. At the same time, a display device has been obtained which has various functions that were not available in the conventional device, and the contents thereof will be specifically explained below with reference to the accompanying drawings.

FIG. 2 is a block diagram showing a schematic configuration of an embodiment of the display device of the present invention, and in FIG. 2, the components corresponding to the components in the circuit arrangement shown in FIG. The same drawing symbols as those used in FIG. 1 are given.

In the display device of the present invention shown in FIG. 2, 1 is a reference clock oscillator, 2 is a frequency divider, and 3 is a timing generator, and the oscillation wave from the reference clock oscillator 1 is divided by the frequency divider 2. Synchronizing signals (horizontal and vertical synchronizing signals) for synchronizing the deflection system of the cathode ray tube are sent out via the conductor group 15, and required outputs are also given to the timing generator 3.

The timing generator 3 receives the Mizuno synchronization signal Ph {Figure a}
A timing pulse P1 {Fig. 3b} is generated at a time position separated by a predetermined time interval τ from the oscillation controller 1.
0 and determines the rising time TO of the oscillation control signal P2 (FIG. 3C) to be supplied from the oscillation controller 10 to the start-stop oscillator 11.

The time TO of the rise of the oscillation control signal P2 is the time of generation of the timing pulse P1 in the timing generator 3,
In other words, depending on how the time interval τ for the horizontal synchronization signal Ph to be set in the timing generator 3 is determined, it can be set at any time point on the time axis, and the above-mentioned time point TO of the rise of the oscillation control signal P2 can be set at any time point. Since a change on the time axis causes a horizontal movement of the display position of the reproduced image on the display surface of the cathode ray tube, by adjusting the time point TO of generation of the timing pulse P1 in the timing generator 3, The horizontal position of the reproduced image on the display surface of the cathode ray tube can be adjusted. For example, a flip-flop may be used as the oscillation controller 10 described above, and the oscillation controller 10 is set by the timing pulse P1 from the timing generator 3 described above, and is set by the timing signal generator 12 described later.
By being reset by the reset signal given from
is applied to the start/stop oscillator 11 to control its oscillation state. The start-stop oscillator 11 is an oscillator that oscillates at a predetermined oscillation frequency only during the period when the oscillation control signal P2 sent from the oscillation controller 10 is applied. Since the oscillation wave P3 from 11 (FIG. 3d) is supplied to the horizontal address counter 6 and the parallel-to-serial converter 8, the horizontal address signal in the horizontal address counter 6 is The updating operation and the parallel-to-serial conversion operation in the parallel-to-serial converter 8 are always performed in a synchronized state, no matter what frequency the start-stop oscillator 11 is oscillating.

In addition, in the display device of the present invention, the address in the horizontal direction is generated by the oscillation wave of the start-stop oscillator 11, which is configured to perform an oscillation operation from the time point set as required in the timing generator 3. Since the counter 6 and the parallel-serial converter 8 are operated, the oscillation frequency of the start-stop oscillator 11 may be set to an arbitrary frequency value unrelated to the horizontal scanning frequency. As a result, the problems with the conventional device described above can be satisfactorily solved. The time length corresponding to one cycle of the oscillation wave from the start-stop oscillator 11 described above is the time length per pixel in the time-series signal sent from the parallel-serial converter 8. By making the oscillation frequency of the stop oscillator 11 variable, the horizontal display width of the reproduced image on the display surface of the cathode ray tube can be made variable.

As described above, in the display device of the present invention, the horizontal position of the reproduced image on the display surface of the cathode ray tube is controlled by controlling the start-stop oscillator 11 to change the oscillation start point and the oscillation frequency. In addition, since the horizontal display width can be adjusted extremely easily, for example, when transmitting a time-series signal to an external monitor receiver to display a reproduced image, the above-mentioned adjustment on the display device side is possible. Through control, a reproduced image of a desired size can be easily projected at a desired position on the display surface of a monitor receiver. This is much simpler than adjusting the system so that the reproduced image is projected at a desired position and size on the display surface of a cathode ray tube.

In other words, in a monitor receiver, the operations of the high voltage system and the deflection system are often related to each other, and the operations of the amplitude adjustment and linearity adjustment in the deflection system are also often related to each other. This is because it is extremely difficult to adjust the horizontal position and horizontal display width of the reproduced image on the display surface as desired on the monitor receiver side.

The horizontal address counter 6 counts the oscillation waves given from the shift stop oscillator 11 and supplies the counted value to the storage device 7 as a horizontal read address signal, and also outputs the counted value to the storage device 7 as a horizontal read address signal.
Also give to 2.

The timing signal generator 12 generates a memory timing signal for controlling the operation of the storage device 7 and a memory timing signal for controlling the operation of the storage device 7.
A memory read signal to be applied to the parallel-to-serial converter 8 in order to read stored information to the parallel-to-serial converter 8, a timing signal for controlling the gate control signal generation circuit 13, etc. are generated. In order to simplify the illustration and explanation, FIG. This is a waveform diagram showing the timing relationship of the operation of each component in the display device, taking as an example the case where the display device is configured with bits (consisting of bits). The oscillation operation starts from the time TO of application of the oscillation control signal P2 shown in FIG. 3c.

When the start/stop oscillator 11 starts oscillating, the horizontal address counter 6 starts and stops.
Counting of the oscillation waves of the stop oscillator 11 is started, and one word of address signal WA is constructed for every four bits.

In Fig. 3e, symbols WAO, WAl...
Subscript number 011 in WA7, WAO, etc.
...7, 0, etc. are added to distinguish the addresses of each word, and the addresses of each word WAO, WAl...
. . . each has four bit addresses BAl~
BA4 (in order to avoid complication of illustration, pit addresses BAl to BA4 are not shown in FIG. 3). The addresses of the storage information to be sequentially read out from the storage device 7 are specified one after another by the horizontal readout address signal shown in FIG. Since it is necessary for a certain period of time to pass after the address signal is supplied to the storage device 7 in order to read the stored information from the storage device 7 to the parallel-to-serial converter 8 in units of words, it is The timing signal P4 is supplied from the timing signal generator 12 to the parallel-to-serial converter 8 such that the timing signal P4 can be executed after the elapse of the above-mentioned fixed time, which is determined depending on the performance of the storage device 7.

FIG. 3f is an example waveform diagram of the timing signal P4 described above. By the way, as mentioned above, the time TO when the horizontal address signal is supplied to the storage device 7 and the time t when the storage information is read out from the storage device 7 to the parallel-to-serial converter 8
On the other hand, for the parallel-serial converter 8, there is a time lag between the start time and the time TO.
Since the time base clock pulse for the parallel-to-serial conversion operation is supplied immediately from the start of the oscillation operation of the stop oscillator 11, the parallel-to-serial converter 8 receives the necessary storage information from the storage device 7 at time t1. The previous time T given.

Since the parallel-to-serial conversion operation has already been performed at time T. During the period from time t1 to time t1, the parallel-to-serial converter 8 sends out an output signal with undefined content.
Figure 3g is a modeled representation of the time-series signal sent from the parallel-serial converter 8 as described above, and the symbols WAIO, WAI, etc. in the figure are , horizontal address signals WAO, WAl...
It is a time-series signal having information content corresponding to the storage information in the storage device 7 specified by .
As shown, at time T.

The contents of the time-series signal sent from the parallel-to-serial converter 8 between the time t1 and the time t1 are indefinite as described above. Therefore, in the display device of the present invention, an AND circuit (
The above-mentioned time T using AND gate) 14.

The above-mentioned problem is solved by preventing the transmission of time-series signals with undefined contents between the time t1 and the time t1. That is, the output signal from the parallel-to-serial converter 8 is given as one input of the AND gate 14, and the other input of the AND gate 14 is given as the output signal from the time t1 when a normal time series signal appears to the end of the time series signal. A gate signal having a pulse width over a period up to time T2 {Figure 3h}P
5 from the gate control signal generation circuit 13, the time-series signal sent from the parallel-serial converter 8 has the indefinite information content part invalidated, as shown in FIG. Therefore, an inconvenient situation such as the left end of the reproduced image becoming disordered due to undefined information content does not occur.

The time series signal in one horizontal scanning period is transmitted to the parallel to serial converter 8.
At time T2 when the signal has been sent out, the oscillation controller 10 and the gate control signal generation circuit 13 are reset by the set pulse P6 (FIG. 3J) sent from the timing signal generator 12, thereby The oscillation control signal P2 and gate signal P5 described above become low level at time T2.

The horizontal address counter 6 in the display device of the above embodiment can be set to any time between time T2 and a time point delayed by τ from the time position of the next horizontal synchronization signal Ph. In the case where the horizontal address counter 6 is reset in this way, the counting content of the horizontal address counter 6 is always zero at a time delayed by τ from the time position of each horizontal synchronizing signal Ph. This corresponds to time T in the illustrated example. The number of oscillation waves oscillated by the start/stop oscillator 11 between T2 and time T2 is larger than the number of 32 bits to be read from the storage device 7 within one horizontal scanning period for the reason mentioned above. The set time T. Since the number of oscillation waves oscillated during the period from t1 to time t1 is greater than the number of oscillation waves, the count value of the horizontal address counter 6 at time T2 is not O, but the number of words in the third illustrated example. This is because even though the address is O, the bit address is 2, and if the next cycle is started in this state, the images that should appear in the successive horizontal scanning periods will not be reproduced correctly. In the above explanation, the count value of the horizontal address counter 6 is always set to zero at the start time TO of each read cycle, but as a general expression, each read cycle is The count value of the horizontal address counter 6 at the time point TO at the start of the cycle may always indicate a specific value (the specific value may be O, or it may be any other value). ).

In the above embodiment, the count value of the horizontal address counter is always set to a specific value in each read cycle, but in other embodiments, the maximum count value of the horizontal address counter The count value and the maximum number of picture elements N in an image within one horizontal scanning period (32 in the example described above)
In other words, the oscillation wave of the start/stop oscillator 11 is frequency-divided by a horizontal address counter constituted by an N-ary counter to obtain a horizontal address signal. A time series signal (WA[7 in FIG. 3) corresponding to the information in the storage device 7 specified by the last address signal in the direction (WA7 in FIG. 3) is sent from the parallel-serial converter 8. The start/stop oscillator 1 starts at the point when the
1, and the counting state of the horizontal address counter 6 consisting of an N-ary counter and the state of the timing signal generator 12 at this point in time (T2 in FIG. 3) are used to determine the next horizontal scanning period. The start/stop oscillator 11 is held for a period until it is restarted, and furthermore, the start/stop oscillator 11 is
When the stop oscillator 11 is activated and starts oscillating, the states of the horizontal address counter 6 consisting of the N-ary counter described above and the timing signal generator 12 are changed to the states held during the period up to that point. The structure may be such that the operation continues until the next state is reached.

As is clear from the above detailed explanation, the display device of the present invention uses a start-stop oscillator that oscillates at a frequency that does not require any correlation with the frequency value of the horizontal synchronization signal to determine the horizontal address. Since it drives the counter and parallel-to-serial converter,
The display device is capable of satisfactorily solving the problems of the conventional device described above, and also allows the position and display width of the reproduced image on the display surface of the cathode ray tube to be adjusted very easily and over a wide range. This provides advantages such as the ability to significantly increase the utility value of.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an example of a conventional display device, FIG. 2 is a block diagram of an embodiment of the display device of the present invention, and FIGS. 3 a to 3 are waveform diagrams for explaining operation. . 1...Reference clock oscillator, 2...
Frequency divider, 3... Timing generator, 4...
・・Horizontal address counter control circuit, 5...
... Gate circuit, 6 ... Horizontal address counter, 7 ... Memory device, 8 ... Parallel-serial converter, 10 ... Oscillation control Vessel, 11...
...Start/stop oscillator, 12...
Timing signal generator, 13... Gate control signal generation circuit, 14... AND gate.

Claims (1)

[Scope of Claims] 1. Storage information of 2 bits or more read word by word from a storage device in which 1 word is made up of at least 2 bits is stored at each address.
Alternatively, in a display device in which a time-series signal is obtained from the parallel-serial converter by being supplied to the parallel-serial converter after passing through a converter, the time-series signal is applied to the display screen of the cathode ray tube. It is equipped with a start-stop oscillator that oscillates at a frequency that has a period of horizontal scanning time for one pixel in the reproduced image reproduced above, and that can be externally controlled. A display device in which an output is divided into a horizontal address signal for a storage device, and a parallel-to-serial conversion operation in a parallel-to-serial converter is regulated by the output of the start-stop oscillator. 2. Memory information of 2 bits or more read word by word from a storage device in which 1 word is made up of at least 2 bits is stored at each address.
Alternatively, in a display device in which a time-series signal is obtained from the parallel-serial converter by being supplied to the parallel-serial converter after passing through a converter, the time-series signal is applied to the display screen of the cathode ray tube. It is equipped with a start-stop oscillator that oscillates at a frequency that has a period of horizontal scanning time for one pixel in the reproduced image reproduced above, and that can be externally controlled. The output is divided into a horizontal address signal for the storage device, and the output of the start/stop oscillator regulates the parallel/serial conversion operation in the parallel/serial converter. A display device comprising means for changing the horizontal display width of a reproduced image on a display surface of a cathode ray tube by changing the oscillation frequency value of a stop oscillator. 3 Memory information of 2 bits or more read word by word from a storage device in which 1 word is made up of at least 2 bits is stored at each address.
Alternatively, in a display device in which a time-series signal is obtained from the parallel-serial converter by being supplied to the parallel-serial converter after passing through a converter, the time-series signal is applied to the display screen of the cathode ray tube. It is equipped with a start-stop oscillator that oscillates at a frequency that has a period of horizontal scanning time for one pixel in the reproduced image reproduced above, and that can be externally controlled. The output is divided into a horizontal address signal for the storage device, and the output of the start/stop oscillator regulates the parallel/serial conversion operation in the parallel/serial converter. By changing the time point at which the stop oscillator starts oscillating with respect to the time position of the horizontal synchronization signal, the display position of the reproduced image reproduced on the display surface of the cathode ray tube by the time series signal is adjusted in the horizontal direction. A display device that makes it possible. 4 Memory information of 2 bits or more read word by word from a storage device in which 1 word is made up of at least 2 bits is stored at each address.
Alternatively, the display device is configured such that a time-series signal is obtained from the parallel-to-serial converter by being supplied to the parallel-to-serial converter after passing through a converter, the time-series signal being applied to a cathode ray tube. The above-mentioned start-stop oscillator is provided with a start-stop oscillator that oscillates at a frequency that has a period of horizontal scanning time for one pixel in a reproduced image reproduced on a display screen and is externally controllable. The output from the start/stop oscillator is frequency-divided to produce a horizontal address signal for the storage device, and the output of the start/stop oscillator regulates the parallel-to-serial conversion operation in the parallel-to-serial converter. In the device, the start
The stop oscillator is activated and starts oscillating when the output of the frequency divider that indicates the horizontal address signal shows a certain value, and then the readout operation of stored information from the storage device and the parallel-to-serial converter are performed. When the parallel-to-serial conversion operation is performed, the storage device specified by the horizontal address signal indicated by the output of the frequency divider is at the starting point of the start of oscillation in the start-stop oscillator. The output from the parallel-to-serial converter is made invalid during the period until the stored information in the parallel-to-serial converter starts to be output as a time-series signal, and the output from the parallel-to-serial converter is A time-series signal is sent from the parallel-to-serial converter between the point at which the invalidation period has elapsed and the last piece of information that should belong to that horizontal scanning period after that point, and the above-mentioned horizontal scanning period At the point in time when the last piece of information that should belong to has been sent out from the parallel-serial converter as a time-series signal, the oscillation of the start-stop oscillator described above is stopped, and this start-stop oscillator is then started and starts oscillating. In the display device, the output of the frequency divider indicating the above-mentioned horizontal address signal during the period up to the start of the above-mentioned horizontal direction address signal indicates the above-mentioned specific value. Memory information consisting of at least 2 bits or more is stored at each address. Memory information of 2 bits or more read word by word from a storage device is converted into parallel to serial data as is or after passing through a converter. The display device is configured such that a time-series signal is obtained from the parallel-serial converter by being supplied to a device, and a reproduced image is reproduced on a display surface of a cathode ray tube by the time-series signal. It is equipped with a start/stop oscillator that oscillates at a frequency whose period is the horizontal scanning time for one pixel in , and is externally controllable, and the output from the start/stop oscillator is divided and stored. In a display device in which the output of the start/stop oscillator is used as a horizontal address signal for the device and regulates the parallel-to-serial conversion operation in the parallel-to-serial converter, reproduction on the display surface of the cathode ray tube is performed. When the number of picture elements in the horizontal direction of an image is N, an N-ary counter is used as a frequency divider to obtain the horizontal address signal, and the number of picture elements in the storage device specified by the last address signal in the horizontal direction is used as a frequency divider. The oscillation of the start/stop oscillator is stopped at the point when the information has been output from the parallel-serial converter as a time-series signal, and the state of the timing signal generator that controls the N-ary counter and the storage device, etc. at this point. is held until the start/stop oscillator is activated in the next horizontal scanning period, and the start/stop oscillator is
When the stop oscillator is started and starts oscillating, the N-ary counter and timing signal generator, etc.
The operation continues so that the state is the same as the state held during the previous period, and the output from the parallel-to-serial converter is ANDed with the oscillation control signal for the start/stop oscillator described above. A display device that obtains time-series signals.