JP2000174192A - External lead of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize solder wettability of high quality and to prevent solder chips by low melting point plating an inside of an external lead, high melting point plating an outside of the lead, and providing a plurality of rectangular continuous protrusion and recess parts at leading end of the lead. SOLUTION: The external lead 21 of a semiconductor device is formed in a double structure, its inside is low melting point plated 12, and its outside is high melting point plated 13. Here, a composition ratio of the plating 12 contains 60±10% of Sn and 40±10% of Pb, and a composition ratio of the plating 13 is 90±10% of Sn and 10±5% of Pb. A plurality of rectangular continuous protrusion and recess parts (widths of the protrusion and the recess of about 10 μm) are provided on a leading end of the lead 21, and the plating 12 is intruded into the recess when plated. Thus, its inside can hold its solder wettability at high quality level, and its inside has a high hardness to prevent solder chips.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an external lead of a semiconductor device, and more particularly to an external lead of a semiconductor device which simultaneously satisfies both high quality solder wettability and prevention of generation of solder dust.

[0002]

2. Description of the Related Art In the plating of external leads of a semiconductor device, it is one of important factors to maintain high quality solder wettability (solderability) and to prevent generation of solder dust generated during semiconductor device manufacturing. I have. For this purpose, usually, plating is applied to the external lead portions of the semiconductor device so that the solder wettability can be maintained to some extent and the hardness of the composition is increased to some extent. FIG. 3 is a sectional view of an external lead of a conventional semiconductor device.

[0003]

However, in the above-mentioned conventional technique, when the solder wettability is improved, the hardness is reduced, and when the hardness is increased, the solder wettability is reduced. For this reason, it has not been possible to sufficiently satisfy two of high quality solder wettability and prevention of generation of solder dust at the same time.

A main object of the present invention is to provide an external lead of a semiconductor device which simultaneously satisfies both high quality solder wettability and prevention of generation of solder dust.

[0005]

The external leads of the semiconductor device according to the present invention are characterized by having a double structure plating, the inside being low melting point plating and the outside being high melting point plating.

Further, the present invention is characterized in that a plurality of continuous rectangular irregularities are provided at the tip of the external lead.

According to the present invention, since the inside is plated with a low melting point, the solder wettability can be at a high quality level. Further, since the outside is formed of a high melting point plating, the hardness is high, and the generation of solder dust generated at the time of manufacturing a semiconductor device can be prevented.

[0008]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a lead portion showing a first embodiment of an external lead of a semiconductor device according to the present invention.

The external lead of the semiconductor device according to the first embodiment shown in FIG. 1 has a double plating structure, whereas the external lead of the conventional semiconductor device has a single plating structure. I have. The inside is the low melting point plating 12 and the outside is the high melting point plating 13.

Since the inside is made of the low melting point plating 12, the solder wettability can be maintained at a high quality level, and since the outside is made of the high melting point plating 13, the hardness is high and the solder dust generated during the manufacture of the semiconductor device is reduced. Generation can be prevented.

The composition ratio of the inner low melting point plating 12 is Sn 60 ± 10%, Pb 4
0 ± 10%, and the composition ratio of the outer high melting point plating 13 is:
It is preferable that Sn 90 ± 5% and Pb 10 ± 5%.

FIG. 2 is a sectional view of a lead portion showing a second embodiment of the external lead of the semiconductor device according to the present invention.

External leads 21 of the semiconductor device shown in FIG.
The plating has a double structure as in the first embodiment, and the inside is a low melting point plating 12 and the outside is a high melting point plating 13.

However, in the second embodiment, the end of the external lead 21 is provided with a plurality of continuous rectangular irregularities. Therefore, the inner plating, which has a low melting point, enters into the recess at the time of plating. For this reason,
At the time of mounting the semiconductor device, more low melting point plating is present at the tip of the external lead as compared with the first embodiment.
Higher quality solder wettability can be realized.

In order to allow more of the inner plating having a low melting point to enter into the concave portion during plating, the width of each of the concave portion and the convex portion of the external lead is preferably about 10 μm.

[0017]

As described above, the plating of the external leads of the semiconductor device of the present invention is doubled and the inside is plated with a low melting point, so that the solder wettability can be made high quality. Since the outside is plated with a high melting point, the hardness is high and the generation of solder dust can be prevented.

Further, since the external leads of the semiconductor device of the present invention have irregularities having a continuous rectangular shape at the tip end,
More low melting point plating can be held in the recess,
Higher quality solder wettability can be realized.

[Brief description of the drawings]

FIG. 1 is a sectional view of a lead portion showing a first embodiment of an external lead of a semiconductor device of the present invention.

FIG. 2 is a sectional view of a lead portion showing a second embodiment of the external lead of the semiconductor device according to the present invention;

FIG. 3 is a cross-sectional view of an external lead of a conventional semiconductor device.

[Explanation of symbols]

 11, 21, 31 External lead 12 Inner low melting point plating 13 Outer high melting point plating 32 Plating

Claims (6)

[Claims] 1. An external lead of a semiconductor device having a double-structure plating, a low melting point plating on the inside, and a high melting point plating on the outside. 2. The composition ratio of the inner low melting point plating is Sn
60 ± 10% and Pb40 ± 10%, and the composition ratio of the outer high melting point plating is Sn90 ± 5%, Pb10 ± 5%.
The external lead of the semiconductor device according to claim 1, wherein 3. The external lead of a semiconductor device according to claim 1, wherein a plurality of rectangular irregularities are provided at a tip portion. 4. The external lead of a semiconductor device according to claim 1, wherein a plurality of continuous rectangular irregularities are provided at a tip portion. 5. The external lead of a semiconductor device according to claim 3, wherein a width of the concave portion of the concave and convex is about 10 μm. 6. The external lead of a semiconductor device according to claim 3, wherein a width of the convex portion of the unevenness is about 10 μm.