JP2000163281A - In-circuit emulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inexpensive in-circuit emulator capable of easily corelating an instruction with access. SOLUTION: A selector 108 receives access data from a data aligner 104 and an instruction code from an instruction holding circuit 105 as inputs and outputs only the access data based on a select signal from an access data switching control circuit 109 or multiplexes a part of the instruction code to the access data and outputs it when access width is smaller than maximum data width. A selector 107 outputs only the instruction code from the circuit 105 based on the select signal from an instruction code switching control circuit 106 or multiplexes a part of an instruction code from an instruction aligner 102 to the instruction code and outputs it when an instruction whose instruction length is longer than a prescribed value is carried out.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an in-circuit emulator, and more particularly to an in-circuit emulator used for debugging hardware and software of a system equipped with a microcomputer.

[0002]

2. Description of the Related Art Generally, an in-circuit emulator (hereinafter, referred to as IE) has a CPU (hereinafter, referred to as E-CPU) for emulating a microcomputer. The E-CPU has functions of stopping the execution of the program of the microcomputer, starting the program from an arbitrary address, and outputting the operation state inside the CPU from a terminal.

In order to increase the instruction execution speed, recent microcomputers read an instruction, store it in an instruction queue, and then execute the instruction. When a memory access cycle caused by an instruction occurs, the microcomputer employing this structure executes the next instruction in the instruction queue.

That is, since a memory access cycle occurs after a certain time has elapsed after the execution of the instruction, the instruction execution of the microcomputer has advanced before the instruction which caused the memory access. For this reason, according to the execution result of the E-CPU left in a memory (hereinafter, referred to as a trace memory) that stores an execution history executed by the microcomputer, the instruction and the access cycle cannot be synchronized.

For this reason, IE control software (hereinafter, referred to as a debugger) predicts the relationship between an instruction and a memory access cycle from the trace contents and performs the association. However, it takes time to perform the association. , The association may be shifted. Further, when a sampling trace is used when it is desired to keep a specific write cycle in the history, the history remains only in the write cycle, and the instruction that caused the write cycle cannot be associated, and the debugging efficiency is reduced.

In order to solve this problem, an emulator having means for holding a fetch address and writing it to an independent trace memory for each bus cycle has been known (Japanese Patent Laid-Open No. 3-125232). Gazette). This conventional emulator includes a trace memory 202 and an address latch circuit 2 as shown in FIG.
Circuit 2 consisting of address circuit 03 and address control unit 204
01. Further, the trace circuit 201 is connected to the master bus 207 together with the emulation memory unit 205 and the like.
Through the master microprocessor (MMCU) 209
Is controlled by

The trace circuit 201 holds a series of instruction addresses sequentially output from the program counter of the slave microprocessor (SMCU) 208 via the slave bus 206 independently of other trace information for each bus cycle. Because of the instruction address holding area, by finding a bug from the trace result, it is possible to immediately know the address of the instruction that wrote the erroneous data, thereby making it possible to correspond to the instruction on the source list. The program can be modified quickly.

[0008]

However, the above-mentioned conventional in-circuit emulator can only sequentially process fetched instructions, so that a plurality of instructions can be executed at the same time, and an instruction that can be executed first is executed in the order of execution. In recent microcomputers that perform complicated processes that are interchanged and executed, there is a problem that it is difficult to associate instructions with memory accesses.

In addition, the conventional in-circuit emulator requires the trace memory 202 dedicated to the address, so that a high-speed emulator requires a large number of high-speed memories, which is the largest factor in cost increase, and is expensive.

[0010] The present invention has been made in view of the above points,
It has a function of dividing the instruction code and data executed by the microcomputer and recording the divided instruction code in the trace memory, and in particular, a function of adding a part of the instruction code to the continuous related instruction code each time and writing the same in the trace memory. And to provide an inexpensive in-circuit emulator that has a function of adding a part of an instruction code to a related access cycle and writing the instruction code to a trace memory to easily associate an instruction with a memory access. Aim.

[0011]

In order to achieve the above object, the present invention provides an in-circuit emulator used for debugging hardware and software of a system equipped with a microcomputer. The instruction code executed, the status signal indicating the access size and the read / write direction, the access data at the time of memory access, the access address at the time of memory access, the instruction access data and the access address are valid. An emulation CPU that outputs a first strobe signal indicating that there is a signal and a second strobe signal that indicates instruction execution timing, and stores access data and access addresses output by the emulation CPU based on the first strobe signal. A data aligner, an instruction aligner for holding an instruction address and a first instruction code output from the emulation CPU based on a second strobe signal, and first and second strobe signals and a status signal output from the emulation CPU. And using a timing control circuit that receives the first instruction code as an input and outputs a timing signal and an output timing signal of the timing control circuit to hold the first instruction code held by the instruction aligner in order to match the first access code with the access cycle. An instruction holding circuit having a pipeline structure for outputting as an instruction code, an access data from a data aligner and a second instruction code from the instruction holding circuit are received as inputs, and only access data is received based on a first select signal. Or a part of the second instruction code in the access data A first selector for multiplexing and outputting, a first switching control circuit for receiving the first strobe signal and a timing signal from the timing control circuit, generating a first select signal, and outputting the first select signal to the first selector; It has the structure which has.

According to the present invention, when the access width is smaller than the maximum data width, a part of the second instruction code is multiplexed and output to the access data. It becomes possible.

According to the present invention, the first selector and the first switching control circuit are replaced with or in addition to the first selector and the first switching control circuit, and the control is performed by determining the instruction length of the first instruction code held by the instruction aligner. An instruction decoder for outputting a signal, a first and second strobe signal output from the emulation CPU and a status signal as inputs, a timing control circuit for outputting a timing signal, a control signal generated by the instruction decoder and a timing control An instruction holding circuit having a pipeline structure for holding a first instruction code held by an instruction aligner in accordance with an access cycle and outputting it as a second instruction code by using an output timing signal of the circuit; Receiving a first instruction code from the aligner and a second instruction code from the instruction holding circuit as inputs, A second instruction code alone or a part of the first instruction code multiplexed and output as the second instruction code, and a second instruction code from the instruction decoder. And a second switching control circuit for receiving a strobe signal of the above and a timing signal from the timing control circuit, generating a second select signal, and outputting the generated second select signal to the second selector.

According to the present invention, when an instruction having an instruction length longer than a predetermined value is executed, a part of the first instruction code can be multiplexed into a second instruction code which is divided and output.

[0015]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a configuration diagram of an embodiment of an in-circuit emulator according to the present invention.
In FIG. 1, an E-CPU 101 is a central processing unit (CPU) for emulating a microcomputer. The instruction aligner 102 is a circuit that aligns and holds the instruction address and the instruction code output from the E-CPU 101. The timing control circuit 103 outputs a timing signal for holding an instruction, an access size signal, and writing to the trace memory 110 based on a strobe signal indicating an instruction execution timing, an access size, and a status signal indicating a read / write direction output from the E-CPU 101. This is a circuit that generates a strobe signal.

The data aligner 104 includes the E-CPU 10
1 is a circuit for holding the access data and the access address output by 1. The instruction decoder 111 is a circuit that determines a stored instruction code and generates a control signal.
The instruction holding circuit 105 holds the instruction code held by the instruction aligner 102 using the control signal generated by the instruction decoder 111 and the signal generated by the timing control circuit 103 in order to match the instruction code with an access cycle or a long instruction. Circuit.

The instruction code switching control circuit 106 and the access data switching control circuit 109
3 is a circuit that uses the control signal output from the instruction decoder 3 and the control signal output from the instruction decoder 111 to generate a switching timing signal for switching data output to the trace memory 110. The selector 107 and the selector 108 use the switching timing signal to store a part of the instruction code in the trace memory 1.
10 is a circuit for outputting the signal.

I_code is the instruction code executed by the E-CPU 101, I_adr is the address where the instruction code is located, fstb is a signal indicating the timing at which the output of the instruction code and the address of the instruction code is valid, A_code
data is data at the time of memory access, A_adr
Is the address at the time of memory access, and tasb is A_
data and A_adr are signals indicating valid timing, Clock is a clock for operating the E-CPU 101, Acc_stat is a status signal indicating access size and read / write direction, and these signals are E-
Output from the CPU 101.

Long_inst is a signal indicating a long instruction length instruction output from the timing control circuit 103, Ac
c_inst indicates that the instruction decoder 111
05, a signal indicating an instruction accompanied by a memory access,
Code_latch is a signal indicating a latch timing in the instruction holding circuit 105. Code is the instruction code held by the instruction aligner 102, hld_co
de is the instruction code held by the instruction holding circuit 105, da
ta is the access data held by the data aligner 104, Acc_size is a signal indicating the access width output from the timing control circuit 103, and code_sel1 is to switch between outputting the access data and outputting a part of the instruction code. A signal output from the access data switching control circuit 109, code_sel2, is used to switch between outputting the instruction code output from the instruction aligner 102 as it is or outputting a part of the instruction code.
This is a signal output from the instruction code switching control circuit 106.

Further, trwrz is a write signal to the trace memory 110 output by the timing control circuit 103, accadr is a write to the trace memory 110, a memory access address from the data aligner 104, and accdat is a write to the trace memory 110. , Memory access data from selector 108, In
st_adr is an instruction execution address from the instruction aligner 102 to be written into the trace memory 110, Inst_adr
"code" is an instruction code from the selector 107 to be written into the trace memory 110.

Next, the data select operation of the embodiment of FIG. 1 will be described with reference to the trace data recording contents 1 (data select) of FIG. 2 and the timing chart of an example of the data selector of FIG. First, the selector 108
Will be described. E-CPU1
01 is an execution address of the instructions a, b, c and d in the I_adr, ie, addresses 100, 102, 106 and 1
Output address 0c. Further, the E-CPU 100 calculates the instruction execution address I_adr (address 100, address 102, 1
Aabb, c at the timing of addresses 06 and 10c)
It outputs instruction codes I_code called cddeeff, gghh, and ijj, and activates a timing signal fstb indicating valid timing.

The instruction aligner 102 is an E-CPU 101
Holds the instruction execution address I_adr output from the memory and writes the write address Inst_adr to the trace memory 1
10 while holding the instruction code I_code output from the E-CPU 101 and storing the instruction code cod
Output as e. In this example, the E-CPU 101
The address 100, the address 102, and the address 1
The addresses 06 and 10c are output, and at the timing of addresses 100, 102, 106 and 10c, as shown in FIGS. 2 and 3, aabb, ccdde
eff, gghh, and ijj are output to code.

Hereinafter, description will be made assuming that the instructions a and b are instructions accompanied by access. The instruction decoder 111 decodes the instruction code “code” from the instruction aligner 102 and, as shown in FIG. 3, activates the output signal Acc_inst (at the high level in the example of FIG. 3) at the timing of the instructions “a” and “b” accompanied by the access. . Instruction holding circuit 10
5 holds the instruction code from the instruction aligner 102 while the input signal Acc_inst is active. The instruction holding circuit 105 has a pipeline of several stages so that no problem occurs even if the access instructions continue.

Assuming that the access A is a memory access cycle generated by the instruction a, the memory access cycle of the instruction a occurs at the clock following the execution of the instruction a as shown in FIG. The E-CPU 101 sets the data A_dat when the memory is accessed at this timing.
“11223344” as a, and a status signal Acc_s indicating the access size and the read / write direction
A signal indicating a 32-bit read is output as tat.

The timing control circuit 103 generates Acc_size indicating the access width from the information of the status signal Acc_stat.
At the time of access B, a signal indicating 16 bits is output. A_data, A_data
The value of adr is held at the timing of the timing signal tasb shown in FIG. 3 from the E-CPU 101, and the access data data and the memory access address accadr are held.
Output as Here, the access data data is “11223344” and the memory access address acc
adr is “1000”.

Here, since the access A is a 32-bit access, if the instruction code is multiplexed with the access data and outputted, the access data does not remain in the trace memory 110 correctly. Therefore, in this embodiment, as shown in the timing chart of FIG.
access data switching control circuit 10 operating in synchronization with k
9, the access data switching control signal Code_
sel1 is input to the selector 108, and the access data data extracted from the data aligner 104 and input to the selector 108 is selected and output to the trace memory 110 as memory access data accdat.

Access B is a 16-bit write to address 1004. The write cycle actually occurs at the same time as the execution timing of the instruction c. When the access data is 16 bits, a part of the instruction code can be multiplexed into the access data and output. Therefore, in this embodiment, the access data switching control signal Code_sel1 generated by the access data switching control circuit 109 is input to the selector 108, extracted from the instruction holding circuit 105, and
8, the instruction code hld_cod shown in FIG.
e is selected, and this hld_code is output to the trace memory 110 as the memory access data accdat.

In this way, the trace memory 110
Is a write signal tr from the timing control circuit 103.
At the timing of wrz, as shown in FIGS.
In the case of 2-bit access A, the 32-bit memory access data accda selected by the selector 108
ta “11223344” is written, and in the case of 16-bit access B, 16
Accd in which 16-bit instruction code “ccdd” of a part of instruction code hld_code “ccddeeff” is added to bit memory access data “5566”
Write data.

As described above, in this embodiment, when the access width is smaller than the maximum data width, a part of the instruction code is output as the access data and the trace memory 110 is output.
, The access can be associated with the instruction code, and the instruction that caused the access can be easily found from the instruction code. Also, no dedicated memory for addresses is required.

Next, the instruction select operation of the embodiment of FIG. 1 will be described with reference to the trace data recording content 2 (instruction select) of FIG. 4 and the timing chart of an example of the instruction select of FIG.

In this example, as shown in FIG. 4, an instruction e at address 200, an instruction f at address 204, an instruction g at address 20c, and three instructions are executed. Further, the instruction f is executed at f-1, f-2,
f-3. That is, it is assumed that the instruction f is a long instruction having a length of 12 bytes and the execution time is as long as 3 clocks (instructions f-1, f-2, and f-3 for each clock).

As shown in the timing diagram of FIG. 5, the timing signal fstb output from the E-CPU 101 and indicating that the instruction has been executed is composed of the instruction e, the first instruction code of the instruction f, and the instruction g. It becomes active at each timing. The instruction aligner 102 in FIG.
adr, instruction code I_code, and timing signal f
It latches at the active timing of stb, and outputs an instruction execution address Inst_adr and an instruction code.

If the instruction is a long instruction, the instruction decoder 111 outputs a signal long_inst indicating that the instruction has a long instruction length as shown in FIG.
As shown in (2), it is activated at the timing of the second instruction code f-2 of the instruction f. When the long_inst is active, the instruction holding circuit 105
de is latched.

The instruction code switching control circuit 106 receives as input the timing signal obtained by delaying the timing signal fstb by one clock and the long_inst signal, and outputs the instruction code output by the instruction aligner 102 as it is, or outputs a part of the instruction code. A switching signal Code_sel2 for switching whether to perform switching is generated. Switching signal Code_
When sel2 is active, the selector 107 selects the instruction code hld_code from the instruction holding circuit 105 and stores the instruction code hld_code in the trace memory 11.
0 is output as the instruction code Inst_code.

When the switching signal Code_sel2 is inactive, the selector 107 selects an instruction code from the instruction aligner 102, and selects the instruction code.
Instruction code Ins for writing to the trace memory 110
Output as t_code.

As a result, as shown in FIG. 5, when the I_code is the instruction f-1 of the instruction f having a long instruction length, "ijk
lmnop ”, instruction“ qrst ”for instruction f-2, instruction f
In the case of -3, the instruction code Inst_code output from the selector 107 to the trace memory 110 is “instruction code” in FIG. 4 and, as shown in FIG. When it is −1, it is “ijjklmnop” which is the same as the input I_code, whereas “ijjklq” is executed at the execution timing of the instruction f-2.
rst ”and“ ijk ”at the execution timing of the instruction f-3.
luvwx ”is output.

That is, in this embodiment, when the instruction f having a long instruction length is executed, a part of the instruction code “ijk” is executed.
l ”is obtained by dividing the divided instruction codes“ qrst ”and“ uvw
x ”is multiplexed on the upper side of the trace memory 1
It is output to 10. As a result, it is found that the instruction is in the middle of an instruction having a long instruction length, and the processing by the debugger is simplified. Further, a memory having an instruction length is not required.

[0038]

As described above, according to the present invention,
If the access width is smaller than the maximum data width, the access data can be associated with the instruction code by multiplexing and outputting a part of the instruction code to the access data. You can easily find it.

According to the present invention, when an instruction having an instruction length longer than a predetermined value is executed, a part of the first instruction code is multiplexed into a second instruction code, which is output. As a result, it is known that the instruction is in the middle of an instruction having a long instruction length, and the processing by the debugger can be simplified.

Further, according to the present invention, it is possible to eliminate the need for a memory dedicated to addresses and a memory having an instruction length, thereby realizing cost reduction of the emulator.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing an example of trace data recording contents (data select) in FIG. 1;

FIG. 3 is a timing chart of an example of a data select in FIG. 1;

FIG. 4 is a diagram showing an example of trace data recorded contents (instruction select) in FIG. 1;

FIG. 5 is a timing chart of an example of an instruction select in FIG. 1;

FIG. 6 is a configuration diagram of a conventional example.

[Explanation of symbols]

101 E-CPU 102 Instruction Aligner 103 Timing Control Circuit 104 Data Aligner 105 Instruction Holding Circuit 106 Instruction Code Switching Control Circuit 107 Selector 2 108 Selector 1 109 Access Data Switching Control Circuit 110 Trace Memory 111 Instruction Decoder I_code Instruction Executed by E-CPU Code I_adr Address where the instruction code is placed fstb Timing signal that the output of the instruction code and the address of the instruction code is valid Clock indicating clock E_CPU operates Acc_stat Status signal indicating access size and read / write direction ng_inst A signal indicating an instruction with a long instruction length Acc_inst A signal indicating an instruction involving memory access Code_latch A signal indicating a latch timing in the instruction holding circuit code An instruction code held in the instruction aligner hld_code An instruction code held in the instruction holding circuit data A data aligner Retained access data Acc_size Signal indicating access width Code_cell Switching signal for outputting access data or outputting a part of instruction code Code_sel2 Instruction code output by instruction aligner is output as it is, or part of instruction code is output. Signal for switching whether to output trwrz Write signal to trace memory accadr Memory access address to write to trace memory accdat Write to trace memory 1 clock delayed signal of the instruction code D1_fstb FSTB write instruction execution address Inst_code trace memory f is written to the non-memory access data Inst_adr trace memory

Claims (6)

[Claims] 1. An in-circuit emulator used for debugging hardware and software of a system equipped with a microcomputer, comprising: an instruction address at which an instruction is executed; an instruction code executed; A status signal indicating the direction, access data at the time of memory access, an access address at the time of memory access, a first strobe signal indicating that the instruction access data and the access address are valid,
An emulation CPU that outputs a second strobe signal indicating an instruction execution timing; a data aligner that holds the access data and an access address output by the emulation CPU based on the first strobe signal; An instruction aligner that holds the instruction address and the instruction code output by the emulator based on the second strobe signal; and receives the first and second strobe signals and the status signal output by the emulation CPU as inputs, An instruction holding circuit having a pipeline structure for holding an instruction code held by the instruction aligner in accordance with an access cycle by using a timing control circuit for outputting a signal and an output timing signal of the timing control circuit; A circuit, receiving, as inputs, access data from the data aligner and an instruction code from the instruction holding circuit, and multiplying the access data only or a part of the instruction code in the access data based on a first select signal. A first selector for multiplexing and outputting, a first selector for receiving the first strobe signal and a timing signal from the timing control circuit, generating the first select signal, and outputting the first select signal to the first selector; An in-circuit emulator comprising a switching control circuit. 2. The first switching control circuit determines whether or not the timing signal indicates that an access width is smaller than a maximum data width, and when the access width is the maximum data width, the first selector controls the access by the first selector. 2. The in-circuit emulator according to claim 1, wherein only the data is selected, and when the data width is smaller than the maximum data width, the first selector causes the access data to multiplex and select a part of the instruction code. . 3. An in-circuit emulator used for debugging hardware and software of a system equipped with a microcomputer, wherein at least an instruction address at which an instruction is executed, a first instruction code at which an instruction is executed, an access size, An emulation CP that outputs a status signal indicating a read / write direction, a first strobe signal indicating that the instruction access data and the access address are valid, and a second strobe signal indicating an instruction execution timing.
U, an instruction aligner that holds the instruction address and the first instruction code output by the emulation CPU based on the second strobe signal, and an instruction length of the first instruction code held by the instruction aligner. An instruction decoder that determines and outputs a control signal; a timing control circuit that receives as input the first and second strobe signals and a status signal output by the emulation CPU and outputs a timing signal; A pipeline structure for holding a first instruction code held by an instruction aligner in accordance with an access cycle and outputting it as a second instruction code using the control signal and the output timing signal of the timing control circuit. And a first instruction code from the instruction aligner. And a second instruction code from the instruction holding circuit as inputs, and based on a second select signal, the second instruction code alone or the second instruction code is added to the first instruction code. A second selector that multiplexes and outputs a second selector signal; a second selector that receives an instruction length determination signal from the instruction decoder, the second strobe signal, and a timing signal from the timing control circuit; And a second switching control circuit for generating and outputting the generated switching signal to the second selector. 4. The second switching control circuit, when the instruction length discrimination signal from the instruction decoder indicates that the instruction length is longer than a predetermined value, the second selector controls the second selector to control the second selector.
And when the instruction length is shorter than the predetermined value, causing the second instruction code to multiplex and select a part of the first instruction code by the second selector. The in-circuit emulator according to claim 3, wherein: 5. An in-circuit emulator used for debugging hardware and software of a system equipped with a microcomputer, comprising: at least an instruction address at which an instruction is executed; an instruction code at which an instruction is executed; A status signal indicating the direction, access data at the time of memory access, an access address at the time of memory access, a first strobe signal indicating that the instruction access data and the access address are valid,
An emulation CPU that outputs a second strobe signal indicating an instruction execution timing; a data aligner that holds the access data and an access address output by the emulation CPU based on the first strobe signal; And an instruction aligner for holding the instruction address and the first instruction code output by the instruction aligner based on the second strobe signal; and determining a control signal by determining an instruction length of the first instruction code held by the instruction aligner. An instruction decoder that outputs, a timing control circuit that receives the first and second strobe signals and the status signal output by the emulation CPU as inputs, and outputs a timing signal; and the control signal generated by the instruction decoder. The timing control circuit An instruction holding circuit having a pipeline structure for holding the first instruction code held by the instruction aligner in accordance with an access cycle and outputting the second instruction code as a second instruction code, using a power timing signal; An access data from a data aligner and a second instruction code from the instruction holding circuit are received as inputs, and only the access data or a part of the second instruction code is added to the access data based on a first select signal. A first selector that multiplexes and outputs a first instruction code from the instruction aligner and a second instruction code from the instruction holding circuit, and based on a second select signal, A second instruction code for multiplexing only the second instruction code or a part of the first instruction code to the second instruction code and outputting the result; A first switching control circuit that receives the first strobe signal and a timing signal from the timing control circuit, generates the first select signal, and outputs the first select signal to the first selector; A second switching control circuit for receiving the instruction length discrimination signal, the second strobe signal, and the timing signal from the timing control circuit, generating the second select signal, and outputting the second select signal to the second selector An in-circuit emulator comprising: 6. The first switching control circuit determines whether or not the timing signal indicates that an access width is smaller than a maximum data width. When the timing signal has a maximum data width, the first selector controls the access by the first selector. Only the data is selected, and when smaller than the maximum data width, the first selector causes the access data to multiplex and select a part of the second instruction code, and the second switching control circuit includes: When the instruction length determination signal from the instruction decoder indicates that the instruction length is longer than a predetermined value, the second selector selects only the second instruction code,
6. The method according to claim 5, wherein when the instruction length is shorter than the predetermined value, the second selector causes the second instruction code to multiplex and select a part of the first instruction code. In-circuit emulator.