JP2000152646A - Inverter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inverter which simultaneously realizes large capacity and high efficiency with use of GCT. SOLUTION: A pressure welding structure is formed by tightening first to fourth GCTs 2a to 2d, first to fourth free wheel diodes 3a to 3d and first to second clamp diodes 13a, 13b with cooling fins 8a to 8o, provided among these elements, and a copper bus bar 11 is used for connection between the cathode side of a first GCT2a of the pressure welding structure and the cathode side of the first clamp diode 13a, between the cathode of the second free wheel diode 3b and the cathode side of the first clamp diode 13a, between the anode side of a fourth GCT2d and the anode side of the second clamp diode 13b and between the anode side of the third free wheel diode 3c and the anode side of the second clamp diode 13b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to an inverter device,
In particular, the present invention relates to a three-level inverter device to which a self-extinguishing type semiconductor device, for example, a gate commutation type turn-off thyristor or the like, to which a critical voltage rising rate is not specified or specifically has a critical voltage rising rate exceeding 1 kV / μs.

[0002]

2. Description of the Related Art A conventional self-extinguishing type semiconductor device applied to construct a large-capacity inverter device is, for example, a GTO.
(Gate turn-off thyristor), IGBT (insulated gate bipolar transistor) and the like. Recently, a gate commutation type turn-off thyristor (hereinafter GC)
T) was developed. Current GCTs have a maximum rating of 4.5 kV, 4.0 kA and a wafer diameter of 4 inches. This is because the turn-off operation can be performed in a very short time by flowing a steep gate-off current having substantially the same value as the on-current conducted from the gate circuit to the GCT, and the switching variation time for each product can be extremely reduced. Can be smaller.

[0003] In principle, the GCT is capable of performing a turn-off operation near a turn-off gain of 1, in which all the main current is commutated to the gate drive circuit. Therefore, the definition of the critical voltage rise rate of the conventional GTO has no meaning for GCT, which means that a snubber capacitor is not required in principle. Also, by supplying a high gate-on current to the GCT at the time of turn-on, it is possible to expect a significant improvement in the resistance against the current increase rate. A three-level large-capacity inverter device in which the GTO is replaced by a GCT that does not define a critical voltage rise rate in order to simultaneously respond to the demands for further increase in capacity, miniaturization, cost reduction, and high reliability of the inverter device from the market. Is becoming mainstream.

A three-level inverter device comprises a DC voltage circuit having three potentials, ie, potentials P and N and an intermediate potential C,
An inverter device having a three-level inverter bridge that can output a potential P, a potential C, or a potential N. FIG. 1 shows a circuit configuration showing a three-level inverter bridge of the inverter device, and FIG. 6 shows a specific simplified structure thereof. The details are disclosed in Japanese Patent Application No. 10-019410 “Inverter Device”.

First, in the circuit configuration of FIG. 1, reference numeral 1 denotes a DC voltage circuit having a potential P, a potential C and a potential N (each potential difference between the potential P and the potential C and the potential C and the potential N is E (V));
GCTs as self-extinguishing semiconductor elements are connected in series. Reference numerals 3a to 3d denote freewheel diodes which are connected in anti-parallel to the GCTs 2a to 2d, respectively. 13a and 13b are connected in series and
It is a clamp diode connected in anti-parallel to the series body of T2b and 2c. The series connection point of the clamp diodes 13a and 13b is connected to the terminal of the potential C. 4a, 4
b is an anode reactor, 4a is connected between the anode of the GCT 2a and the terminal of the potential P, and 4b is connected between the cathode of the GCT 2d and the terminal of the potential N, respectively.

[0006] 5a and 5b are reset diodes, 7a,
7b is a clamp capacitor, and a reset diode 5a
And a clamp capacitor 7a connected in series to form a GCT 2a
And the reset diode 5b and the clamp capacitor 7b are connected in series and connected between the cathode of the GCT 2d and the terminal of the potential C, respectively. 6a and 6b are reset resistors, 6a is between a series connection point of the reset diode 5a and the clamp capacitor 7a and the terminal of the potential P, and 6b is a series connection point of the reset diode 5b and the clamp capacitor 7b and the potential N Are connected between the terminals.
OUT is an output terminal connected to a load (not shown).

In the simple structure shown in FIG.
a to 2d, freewheel diodes 3a to 3d,
The clamp diodes 13a, 13b are separated and configured as separate semiconductor packages having the same diameter. The reset diodes 5a and 5b are configured as semiconductor packages smaller than the diameters of the freewheel diodes 3a to 3d or the clamp diodes 13a and 13b. 6a and 6b are water-cooled resistors as reset resistors, 8a to 8o are cooling fins,
a and 4b are anode reactors, and 7a and 7b are clamp capacitors. 9 is a GCT 2a to 2d, a freewheel diode 3a to 3d, and a clamp diode 1.
The first pressure-welding structure 10 formed by stacking ten semiconductor packages 3a and 13b together with the cooling fins 8a to 8k interposed between the semiconductor packages is reset. A second configuration in which diodes 5a and 5b and reset resistors 6a and 6b are superimposed, and cooling fins 8l to 8o provided between and on both outer sides of the diodes 5a and 5b and insulators 14a and 14b are fastened together. It is a pressure contact structure. Reference numerals 11a to 11o denote electrical connection means, which are formed by, for example, wide copper bus bars.

Next, the circuit operation will be described with reference to FIGS. Regarding the circuit operation of the three-level inverter, the operation related to GCT2a and GCT2b and the operation of GCT2
The operation regarding d and GCT2c is completely symmetric. Therefore, the circuit operation relating to GCT2a and GCT2b will be described here, and the description of the circuit operation relating to GCT2d and GCT2c will be omitted. First, the switching operation of the GCT 2a will be described with reference to FIGS. In each figure, to show the change of the current path, (1)
The same circuits are indicated by the reference numerals (1) to (4) or (1) to (5), but the reference numerals of the circuit elements are assigned only to (1) and are not assigned to the other circuits. When the GCT 2a switches, the GCTs 2a, 2b and the clamp diodes 13a, G
The commutation operation with CT2b may be considered.

As indicated by the arrow in FIG. 7A, the GCT 2 is switched from the ON state of the GCTs 2a and 2b where the load current is flowing.
The load current immediately after a is turned off is bypassed to the reset diode 5a → the clamp capacitor 7a → the clamp diode 13a as indicated by the arrow in FIG. 7 (2). At this time, the current change rate of the GCT 2a, that is, the commutation speed to the bypass path is dir / dt (A / s), the capacitance of the clamp capacitor 7a is C (F), and the bypass from the anode terminal to the cathode terminal of the GCT 2a. The stray inductance existing in the path is L1 (H), the current change rate d of the clamp diode 13a and the reset diode 5a.
Assuming that the forward recovery voltage (transient ON voltage) with respect to i1 / dt is VC (V) and VR (V), the maximum value VDSP1 (V) of the spike voltage applied to the GCT 2a can be expressed by Expression 1.

VDSP1 = 1 / C · １ ／ i1dt + L1 · di1 / dt + VC + VR (Equation 1)

Thereafter, as shown by the arrow in FIG. 7 (3), when the current of the GCT 2a becomes zero, all the load current is commutated to the clamp diode 13a.
The energy stored in the anode reactor 4a is recovered by the clamp capacitor 7a. When the current of the anode reactor 4a becomes zero (A), the turn-off operation of the GCT 2a ends. Then, clamp capacitor 7
a is a DC voltage circuit 1 as shown by an arrow in FIG.
Is discharged through the reset resistor 6a until the voltage reaches the voltage E (V).

Immediately after the GCT 2a is turned on from the off state shown in FIG. 8 (1), as shown by an arrow in FIG. Current is supplied. Also,
As shown by the arrow in FIG. 8C, the maximum value of the reverse recovery current of the clamp diode 13a is superimposed on the current.
When the off state of the clamp diode 13a is established, as shown by an arrow in FIG.
The energy due to the reverse recovery current of the clamp diode 13a, which is excessively accumulated, is recovered by the clamp capacitor 7a. The current of the anode reactor 4a is equal to the load current I.
When it becomes equal to (A), the turn-on operation of the GCT 2a ends. The clamp capacitor 7a is discharged to the DC voltage circuit 1 through the reset resistor 6a until reaching the voltage E (V), as indicated by the arrow in FIG. 8 (5).

Next, the switching operation of the GCT 2b will be described with reference to FIGS. When the GCT 2b switches, the commutation operation of the GCT 2b, the clamp diode 13a, and the freewheel diodes 3c and 3d may be considered for the load current having the current value I (A).

As shown by the arrow in FIG. 9A, the load current immediately after the GCT 2b is turned off from the on state of the GCT 2b and the clamp diode 13a, as shown by the arrow in FIG. Capacitor 7b
→ Bypass to reset diode 5b → freewheel diode 3d → freewheel diode 3c. The current change rate of the GCT 2b at this time, that is, the commutation speed to the bypass path is di1 / dt (A / s), the capacitance of the clamp capacitor 7b is C (F), and the anode of the clamp diode 13a is connected from the cathode terminal of the GCT 2b. The stray inductance existing in the bypass path to the terminal is represented by L2 (H), freewheel diodes 3c and 3d, clamp diode 13a, and reset diode 5b.
Assuming that the forward recovery voltage (transient ON voltage) with respect to the current change rate di1 / dt is VF (V), VC (V), and VR (V), the maximum value V of the spike voltage applied to the GCT 2b is V
DSP2 can be expressed by Equation 2.

VDSP2 = 1 / C · ∫i1dt + L2 · di1 / dt + 2VF + VC + VR (Expression 2)

Thereafter, when the current of the GCT 2b becomes zero (A), as shown by the current path by the arrow in FIG. 9 (3), the load current commutates from the reset diode 5b to the anode reactor 4b. This commutation is caused by the clamp capacitor 7
Since this is performed by the difference voltage between the charging voltage of b and the voltage E (V) of the DC voltage circuit 1, the same energy as the energy by the load current stored in the anode reactor 4b is stored in the clamp capacitor 7b. The turn-off operation ends when the current of the anode reactor 4b becomes equal to the load current I (A). The clamp capacitor 7b is
As shown by the arrow in FIG. 9D, the DC voltage circuit 1 is discharged through the reset resistor 6b until the voltage reaches the voltage E (V).

Immediately after the GCT 2b is turned on from the off state, the current path is indicated by an arrow in FIG.
As indicated by the arrow in FIG. 10B, current is supplied from the DC voltage circuit 1 up to the value of the load current that is conducting the freewheeling diodes 3c and 3d. In addition, the maximum value of the reverse recovery current of the freewheel diodes 3c and 3d is superimposed on the current, as indicated by the arrow in FIG.
When the off state of the freewheel diodes 3c and 3d is established, the energy due to the reverse recovery current of the freewheel diodes 3c and 3d excessively stored in the anode reactor 4b is reduced as shown by an arrow in FIG. 7b. Anode reactor 4
When the current b becomes zero (A), the turn-on operation of the GCT 2b ends. The clamp capacitor 7b is provided as shown in FIG.
As shown by the arrow in (5), the DC voltage circuit 1 is discharged through the reset resistor 6b until the voltage reaches the voltage E (V).

[0018]

FIG. 11 shows the GCT 2a shown in FIG. 7 (2) by the turn-off bypass path, and FIG. 12 shows the GCT 2b shown in FIG. 9 (2) the turn-off bypass path by thick lines. Shown by line. In order to improve the interruption capability of the GCT and increase the capacity of the device, it is necessary to minimize the stray inductance existing in the bypass path as much as possible. In addition, the copper bus bars must be connected with due care so as not to hinder the circuit operation due to the electrically connected copper bus bars.

As shown in the conventional simplified structure of FIG.
Freewheel diode 3b from cathode side of T2a
Is connected by a copper bus bar 11a, and the cathode side of the freewheel diode 3b is connected to the cathode side of the clamp diode 13a by the copper bus bar 11b. Similarly, the anode side of the GCT 2d is connected to the anode side of the freewheel diode 3c. Are connected by the copper bus bar 11j, and the anode side of the clamp diode 13b is connected from the anode side of the freewheel diode 3c to the anode side of the clamp diode 13b by the copper bus bar 11i.
Immediately after the GCT 2a shown in FIG. 7 (2) is turned off from the on state of the GCT 2a and 2b, the bypass path shown by the thick line in FIG.
Since the load current was flowing until 2a turned off,
The steep change in the current direction causes the copper busbar 11
An induced voltage is generated at a and 11b. The energy caused by the induced voltage of the copper bus bar 11a is equal to the GCT2 that is turned off.
a, the energy due to the induced voltage of the copper bus bar 11b is changed from the copper bus bar 11b to the cooling fin 8e to the GCT.
2b → cooling fin 8d → freewheel diode 3b
→ A circulating current flows through the copper bus bar 11b. The circulating current path is shown by a thick line in FIG.

The decay time of the circulating current is determined by the ON voltage of the GCT 2b, the forward voltage of the freewheel diode 3b, and the inductance value of the copper bus bar 11b. Assuming GC
5V on-voltage of T2b, freewheel diode 3
Assuming that the forward voltage of b is 5 V and the inductance value of the copper bus bar 11b is 0.2 μH, the decay rate becomes 50 A / μs, and when 4000 A is cut off, (load current + 4000) A is superimposed on the GCT 2 b and added to the load current value. 8 to return
It takes as long as 0 μs. As described above, the sum of the load current and the circulating current flows through the GCT 2b. If the GCT 2b is turned off within the decay time, the current duty of the GCT 2b becomes very severe, and there is a possibility that the interruption may fail. Therefore, it is difficult to increase the capacity of the device.

Next, when the reset diodes 5a and 5b, the reset resistors 6a and 6b, the cooling fins 8l to 8o, and the insulators 14a and 14b are fastened together in the second insulation displacement structure 10, the reset resistors 6a and 6b 11, the stray inductance existing in the bypass path when the GCT 2a is turned off as indicated by the thick line and the stray inductance existing in the bypass path when the GCT 2b is turned off as indicated by the thick line in FIG. 12 are increased, and the spike voltage VDSP1 is increased. , VDSP2 rise. In other words, the clamp capacitors 7a, 7a have a thickness corresponding to the thickness of the reset resistors 6a, 6b.
b, the copper bus bar 11f, 11e or 11e,
The distance of 11 m is increased, and the effect of reducing the stray inductance due to their mutual inductance is reduced. Therefore,
The current duty at the turn-off of GCT becomes severe,
It is difficult to increase the capacity of the device.

When the clamp capacitors 7a and 7b are not fastened to the second press-connecting structure 10, the stray inductance existing in the bypass path at the time of turning off the GCT 2a shown by the thick line in FIG. 11 and the thick line shown in FIG. The stray inductance existing in the bypass path at the time of turning off the GCT 2b, which is indicated by, increases, and the spike voltages VDSP1 and VDSP2 increase. That is, the clamp capacitor 7 is separated by the distance that the clamp capacitor is separated.
copper busbars 11f, 11e or 1 connected to a, 7b
1e and 11m are required. Therefore, GCT2a, 2b
The duty of current at the time of turn-off becomes severe, and it is difficult to increase the capacity of the device.

Next, when the wiring inductance of the copper bus bar 11e connected to the terminal of the potential C is large, G of FIG.
Due to the commutation operation when the CT 2a is turned off, an induced voltage is generated in the wiring inductance of the copper bus bar 11e, and
At the time of turning off of T2a, the discharge of the clamp capacitor 7b irrelevant is performed through the reset resistor 6b, and the DC voltage circuit 1 is finally charged to the voltage E (V) via the reset diode 5b. FIG.
When the GCT 2a is turned on, an induced voltage is generated in the wiring inductance of the copper bus bar 11e by the commutation operation, and when the GCT 2a is turned on, an unrelated clamp capacitor 7b is charged through the reset diode 5b, and finally the DC voltage circuit 1 is turned on. Is discharged through the reset resistor 6b until the voltage reaches the voltage E (V).

Further, when the GCT 2b shown in FIG. 9 is turned off, an induced voltage is generated in the wiring inductance of the copper bus bar 11e by the commutation operation, and when the GCT 2b is turned off, an unrelated discharge of the clamp capacitor 7a is performed through the reset resistor 6a. Finally, the DC voltage circuit 1 is charged through the reset diode 5a until it reaches the voltage E (V). Further, when the GCT 2b in FIG. 10 is turned on, an induced voltage is generated in the wiring inductance of the copper bus bar 11e by the commutation operation, and when the GCT 2b is turned on, an unrelated clamp capacitor 7a is charged through the reset diode 5a, and finally a DC voltage is applied. The voltage E is applied to the voltage circuit 1 via the reset resistor 6a.
It is discharged until it becomes (V). As described above, the charging and discharging of the unrelated clamp capacitor is performed in all commutation operations, the loss of the reset resistor is increased, and the efficiency of the device is reduced. Therefore, it is desirable to minimize the wiring inductance of the copper busbar connected to the terminal of the potential C.

The present invention has been made in order to solve the above problems, and has been made by using a GCT having a rating equal to or higher than the GTO rating and having a high critical voltage rise rate tolerance. It is an object of the present invention to provide an inverter device that simultaneously achieves higher capacity and higher efficiency.

[0026]

An inverter device according to the present invention comprises a DC voltage circuit having three potentials P and N and an intermediate potential C, and a three-level inverter bridge capable of outputting each of the potentials. The three-level inverter bridge includes first to fourth GCTs connected in series, first to fourth freewheel diodes connected in anti-parallel to each of the GCTs, and the DC voltage circuit. A first clamp diode connected between the terminal of the potential C and the anode terminal of the second GCT;
A second clamp diode connected between the cathode terminal of the GCT and the terminal of the potential C of the DC voltage circuit;
A first anode reactor connected between a terminal of the potential P of the DC voltage circuit and an anode terminal of the first GCT; a first reset diode connected in parallel to the first anode reactor; A first series connection composed of a reset resistor, a first reset diode connected between a connection point between the first reset diode and the first reset resistor and a terminal of the potential C of the DC voltage circuit; A first clamp capacitor that can be discharged to the DC voltage circuit only via a resistor, a second anode reactor connected between an anode terminal of a fourth GCT and a potential N terminal of the DC voltage circuit, A second series connection body including a second reset diode and a second reset resistor connected in parallel to the second anode reactor; a second reset diode and a second reset diode; It is connected between the terminals of the potential C of the connection point between the direct voltage of the set resistance, a second that can be discharged into the DC voltage circuit only via the second reset resistance
Of the second GCT and the third GCT
And a bridge circuit having an output terminal provided at a connection point with the GCT, wherein each of the GCTs, each freewheel diode, and the first and second clamp diodes are configured as separate semiconductor packages, In addition, cooling fins each functioning as a conductor are interposed between the semiconductor packages, and they are pressed against each other in the direction of electric current to form a press-contact structure, thereby forming a first press-contact structure. The cathode side of the GCT and the cathode side of the first clamp diode, the cathode side of the second freewheel diode and the cathode side of the first clamp diode, the anode side of the fourth GCT and the anode side of the second clamp diode, and Connect the anode side of the third freewheel diode and the anode side of the second clamp diode. It is obtained so as to connect Zoredo bus bar.

Further, the inverter device of the present invention is an inverter device having a DC voltage circuit having three potentials P and N and an intermediate potential C, and a three-level inverter bridge capable of outputting each of the potentials. The three-level inverter bridge includes first to fourth GCTs connected in series and first to fourth GCTs connected in anti-parallel to the respective GCTs.
A fourth freewheeling diode, a first clamp diode connected between the terminal of the potential C of the DC voltage circuit and an anode terminal of the second GCT, and a third GCT
A second clamp diode connected between the cathode terminal of the DC voltage circuit and the terminal of the potential C of the DC voltage circuit; and a second clamp diode connected between the terminal of the potential P of the DC voltage circuit and the anode terminal of the first GCT. A first anode reactor
A first series connected body composed of a first reset diode and a first reset resistor connected in parallel to the anode reactor of the first embodiment, a connection point between the first reset diode and the first reset resistor, and the DC voltage A first clamp capacitor connected between the terminal of the circuit potential C and capable of being discharged to the DC voltage circuit only through a first reset resistor; an anode terminal of a fourth GCT and a potential of the DC voltage circuit; A second anode reactor connected between the second anode reactor and a second reset diode, and a second series connection body including a second reset diode and a second reset resistor connected in parallel to the second anode reactor; The direct-current circuit is connected between a connection point between a second reset diode and a second reset resistor and a terminal of the potential C of the DC voltage circuit, and is connected only through a second reset resistor. A bridge circuit having a second clamp capacitor capable of discharging to a voltage circuit and an output terminal provided at a connection point between the second GCT and the third GCT, wherein each GCT and each freewheel The diode and the first and second clamp diodes are configured as separate semiconductor packages, and cooling fins each functioning as a conductor are interposed between the semiconductor packages. The clamped first pressure contact structure, the first and second reset diodes, and the cooling fins coupled to the respective reset diodes and functioning as conductors are pressed against each other in the direction in which they are energized without passing through reset resistors. It is provided with a second press-contact structure fastened together.

Further, in the inverter device according to the present invention, the second pressure contact structure includes first and second reset diodes.
The cooling fin which is coupled to each reset diode and functions as a conductor, and the first and second clamp capacitors are fastened together.

Further, the inverter device of the present invention is an inverter device having a DC voltage circuit having three potentials P and N and an intermediate potential C, and a three-level inverter bridge capable of outputting each of the potentials. The three-level inverter bridge includes first to first inverters connected in series.
A fourth GCT, and a first GCT connected in anti-parallel to each of the GCTs.
To a fourth freewheel diode, a first clamp diode connected between the terminal of the potential C of the DC voltage circuit and an anode terminal of the second GCT, and a third GC
A second clamp diode connected between the cathode terminal of T and the potential C terminal of the DC voltage circuit, and a second clamp diode connected between the potential P terminal of the DC voltage circuit and the anode terminal of the first GCT; A first anode reactor, a first reset diode and a first reset resistor connected in parallel to the first anode reactor.
And a connection point between a first reset diode and a first reset resistor and a terminal of the potential C of the DC voltage circuit, and the DC voltage is connected only via the first reset resistor. A first clamp capacitor capable of discharging to a circuit, a second anode reactor connected between an anode terminal of a fourth GCT and a potential N terminal of the DC voltage circuit, and a parallel connection to the second anode reactor A second series connection composed of a second reset diode and a second reset resistor, a connection point between the second reset diode and the second reset resistor, and a terminal of a potential C of the DC voltage circuit. And a second clamp capacitor which is connected between the second GCT and the third GCT, and which can be discharged to the DC voltage circuit only through the second reset resistor. And a bridge circuit having a power terminal, wherein each of the GCTs, each of the freewheeling diodes, and the first and second clamp diodes is formed as a separate semiconductor package, and between each of the semiconductor packages. A first pressure-welded structure and a first reset diode and a reset resistor, and a second reset diode and a reset resistor, which are provided with cooling fins functioning as conductors and pressed together in the energizing direction and fastened together, A cooling fin functioning as a conductor is interposed between the two, and the second fin is pressed together in the direction of electric current and fastened together.
And a plurality of copper bus bars for connecting the two pressure-welding structures and the DC voltage circuit so as to constitute the bridge circuit, and a first pressure-welding structure, a second pressure-welding structure and the DC A copper bus bar for connecting to the terminal of the potential C of the voltage circuit is constituted by two copper bus bars connected in parallel, one of the copper bus bars is arranged close to the copper bus bar connected to the terminal of the potential P, and the other copper bus bar Is arranged close to a copper bus bar connected to the terminal of the potential N.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Hereinafter, a first embodiment of an inverter device according to the present invention will be described with reference to the drawings. FIG. 1 shows a circuit configuration showing a three-level inverter bridge of an inverter device, and FIG. 2 shows a specific simplified structure of a three-level inverter bridge which is a first embodiment of the inverter device according to the present invention. It is.

In FIG. 1, 1 is a DC voltage circuit having a potential P, a potential C, and a potential N (the potential difference between the potential P and the potential C, and the potential difference between the potential C and the potential N is E (V)). GCTs as arc-shaped semiconductor elements are connected in series. Reference numerals 3a to 3d denote freewheel diodes which are connected in antiparallel to the GCTs 2a to 2d, respectively. 13
Reference numerals a and 13b denote clamp diodes connected in series and connected in anti-parallel to the series body of the GCTs 2b and 2c. The series connection point of the clamp diodes 13a and 13b is connected to the terminal of the potential C. Reference numerals 4a and 4b denote anode reactors, 4a is connected between the anode of the GCT 2a and the terminal of the potential P, and 4b is connected between the cathode of the GCT 2d and the terminal of the potential N.

5a and 5b are reset diodes, 7a,
7b is a clamp capacitor, and a reset diode 5a
And a clamp capacitor 7a connected in series to form a GCT 2a
And the reset diode 5b and the clamp capacitor 7b are connected in series and connected between the cathode of the GCT 2d and the terminal of the potential C, respectively. 6a and 6b are reset resistors, 6a is between a series connection point of the reset diode 5a and the clamp capacitor 7a and the terminal of the potential P, and 6b is a series connection point of the reset diode 5b and the clamp capacitor 7b and the potential N Are connected between the terminals.
OUT is an output terminal connected to a load (not shown).

In FIG. 2, the GCTs 2a to 2d, the freewheel diodes 3a to 3d, and the clamp diodes 13a and 13b are separated from each other, and are configured as separate semiconductor packages having the same diameter. The reset diodes 5a and 5b are freewheel diodes 3a to 3d or clamp diodes 13a and 3b.
It is configured as a semiconductor package smaller than the apertures a and 13b. 6a and 6b are water-cooled resistors as reset resistors, 8a to 8o function as conductors, and cooling fins serving also as connection conductors, 4a and 4b are anode reactors,
7a and 7b are clamp capacitors.

Reference numeral 9 denotes GCTs 2a to 2d, freewheel diodes 3a to 3d, clamp diodes 13a,
13b, a first press-contact structure constituted by stacking ten semiconductor packages stacked together and cooling fins 8a to 8k interposed between the respective semiconductor packages, and 10 is a reset diode 5a , 5b and reset resistors 6a, 6b, cooling fins 8l-8o provided between and on both outer sides thereof, and insulators 14a, 14b. The pressure contact structures 11a to 11o are electric connection means, and are formed by, for example, wide copper bus bars.

The cathode side of the GCT 2a and the cathode side of the clamp diode 13a are connected by the copper bus bar 11a, and the cathode side of the freewheel diode 3b and the cathode side of the clamp diode 13a are connected by the copper bus bar 11b. Similarly, the copper bus bar 11
By connecting the anode side of the GCT 2d and the anode side of the clamp diode 13b by j, and connecting the anode side of the free wheel diode 3c and the anode side of the clamp diode 13b by the copper bus bar 11i, the GCTs 2a and 2b are turned on. Immediately after the GCT 2a is turned off, a copper bus bar 11a between the cathode side of the GCT 2a and the cathode side of the clamp diode 13a.
Is consumed by the GCT 2a, and the GCT 2b is not superimposed with the circulating current due to the induced voltage generated by the copper bus bar 11a, and interrupts the normal load current. The same applies to the case where the GCT 2d is turned off from the on state of the GCTs 2c and 2d.

On the other hand, the connection between the first pressure contact structure and the second pressure contact structure is made by connecting the cathode side of the freewheel diode 3a and the cooling fin 8l, ie, the anode side of the reset diode 5a, by a copper bus bar 11c. , The copper bus bar 11e passes between the insulators 14a and 14b to connect the cathode side of the clamp diode 13a to the connection point of the clamp capacitors 7a and 7b and the terminal of the potential C, and the copper bus bar 11k connects the freewheel diode 3d.
And the cooling fin 8o, that is, the cathode side of the reset diode 5b.

The anode reactor 4a is connected to the cooling fin 81, ie, the anode side of the reset diode 5a, and the terminal of the potential P by the copper bus bars 11h and 11g, and the terminal of the potential P is connected to the reset resistor 6a by the copper bus bar 11d. Is connected to one end. Further, the anode reactor 4b is connected to the cooling fin 8o, that is, the cathode side of the reset diode 5b, and the terminal of the potential N by the copper bus bars 11o and 11n, and the terminal of the potential N is connected to one end of the reset resistor 6b by the copper bus bar 11l. It is connected. The other end of the clamp capacitor 7a is connected to the other end of the reset resistor 6a by a copper bus bar 11f, and the other end of the clamp capacitor 7b is connected to the copper bus bar 1f.
1m is connected to the other end of the reset resistor 6b.

Embodiment 2 Next, a second embodiment of the inverter device according to the present invention will be described with reference to the drawings.
FIG. 3 shows a specific simplified structure according to the second embodiment. In FIG. 3, the same or corresponding parts as those in the first embodiment shown in FIG. The difference from FIG. 2 is that the second pressure welding structure 10
, Anode reactors 4a, 4b, reset resistor 6
a, 6b and clamp capacitors 7a, 7b. Second
The press-contact structure 10 is constructed by fastening the reset diodes 5a and 5b, the cooling fins 8l and 8o, and the insulators 14a and 14b together in a stacked state as shown in FIG.
The reset resistors 6a and 6b are connected to the cooling fins 8m and 8m, respectively.
n and connected to the anode reactors 4a and 4b by copper bus bars 11d and 11l. The other ends of the clamp capacitors 7a and 7b are connected to the copper bus bars 11d and 11l, respectively.
f, 11m are connected to the cathode side of the reset diode 5a and the anode side of 5b.

The second pressure contact structure 10 is formed by reset diodes 5a and 5b, cooling fins 8l and 8o, insulators 14a,
14b and the reset resistors 6a and 6b are not jointly fastened, so that the stray inductance L1 (H) existing in the bypass path when the GCT 2a is turned off and the bypass path when the GCT 2b is turned off. The existing stray inductance L2 (H) is made as small as possible. That is, the clamp capacitors 7a, 7b
Bus bar 11f, 11e or 11e, 1 connected to
The distance of 1 m is reduced, the effect of reducing the stray inductance by their mutual inductance is increased, and the spike voltage is suppressed.

Embodiment 3 Next, a third embodiment of the inverter device according to the present invention will be described with reference to the drawings.
FIG. 4 shows a specific simplified structure according to the third embodiment. In FIG. 4, the same or corresponding parts as those of the second embodiment shown in FIG. What is different from FIG.
In place of the insulators, clamp capacitors 7a and 7b are arranged at the positions of the insulators 14a and 14b in FIG. 3, and the clamp capacitors 7a and 7b are fastened together with the reset diodes 5a and 5b and the cooling fins 8l and 8o. It constitutes.

By clamping the clamp capacitors 7a and 7b together with the second pressure-bonding structure 10, the stray inductance L1 (H) existing in the bypass path when the GCT 2a is turned off and the floating inductance L1 (H) in the bypass path when the GCT 2b is turned off. This is to reduce the existing stray inductance L2 (H) and suppress the spike voltage.

Embodiment 4 Next, a fourth embodiment of the inverter device according to the present invention will be described with reference to the drawings.
FIG. 5 shows a specific simplified structure according to the fourth embodiment. In FIG. 5, the same or corresponding parts as those in the first embodiment shown in FIG. 2 is different from FIG. 2 in that the copper bus bar 11e of FIG. 2 connected to the terminal of the potential C is composed of two copper bus bars connected in parallel, and one copper bus bar 11e is an insulator 1
4a and the copper bus bar 11d connected to the terminal of the potential P so as to be sandwiched between the block 12 and the other copper bus bar 11p connected to the terminal of the potential N so as to be sandwiched between the insulator 14b and the block 12. The copper bus bars 11e and 11p are arranged as close as possible to the copper bus bar 11l so as to minimize the wiring inductance.

In this case, the block 12 may be any structure as long as it can withstand the pressure welding. For example, an iron block, an insulating block or the like can be applied. This embodiment minimizes charging / discharging of the clamp capacitor 7b irrespective of when the GCT 2a is turned off or turned on, suppresses the generation loss of the reset resistor 6b, and enables high efficiency of the device. Similarly, when the GCT 2b is turned off and turned on, the clamp capacitor 7 has no relation when the GCT 2b is turned on.
The charge and discharge of a are minimized, and the generation loss of the reset resistor 6a is suppressed.

[0044]

As described above, according to the inverter device of the present invention, the cathode side of the GCT 2a and the cathode side of the first clamp diode, the cathode side of the second freewheel diode, The cathode side of the first clamp diode, the anode side of the GCT 2d and the anode side of the second clamp diode, and the anode side of the third freewheel diode and the anode side of the second clamp diode are connected by copper bus bars, respectively. , GCT2a, 2b
Immediately after the 2a is turned off, the energy due to the induced voltage generated in the copper bus bar 11a between the cathode side of the GCT 2a and the cathode side of the clamp diode 13a becomes GC.
It is consumed when the T2a is turned off, and the circulating current due to the induced voltage generated in the copper bus bar 11a is not superimposed on the GCT 2b, so that a normal load current flows and the capacity of the device can be increased. It is. G
The same effect can be obtained when the GCT 2d is turned off from the on state of the CTs 2c and 2d.

According to the inverter device of the present invention,
Since the second pressure contact structure is configured to fasten the first and second reset diodes and the cooling fins that are coupled to the respective reset diodes and function as conductors without passing through the reset resistors, the clamp capacitors 7a, 7
b, the copper bus bar 11f, 11e or 11e,
The distance of 11 m can be reduced, the stray inductance due to their mutual inductance can be reduced, and the spike voltage can be suppressed.

According to the inverter device of the present invention,
A second pressure-welding structure is formed by fastening together the first and second reset diodes, the cooling fin that is coupled to each of the reset diodes, and functions as a conductor, and the first and second clamp capacitors. Therefore, the stray inductance L1 (H) existing in the bypass path when the GCT 2a is turned off and the stray inductance L2 (H) existing in the bypass path when the GCT 2b is turned off can be reduced, and the spike voltage can be suppressed. Is what you can do.

According to the inverter device of the present invention,
A copper bus bar for connecting the first pressure-bonding structure and the second pressure-bonding structure to the terminal of the potential C of the DC voltage circuit is constituted by two copper bus bars connected in parallel, and one of the copper bus bars is a terminal of the potential P. And the other copper bus bar is arranged close to the copper bus bar connected to the terminal of the potential N, so that the mutual inductance due to the reciprocating current is increased, and the copper bus bar is connected to the terminal of the potential C. The wiring inductance of the copper bus bar can be reduced as much as possible, and the charging and discharging of the clamp capacitor 7b irrelevant at the time of turning off and turning on the GCT 2a can be suppressed,
Since the generation loss of the reset resistor 6b is suppressed, it is possible to increase the efficiency of the device. Similarly, when the GCT 2b is turned off and turned on, the charging and discharging of the irrelevant clamp capacitor 7a is minimized, and the reset resistor 6 is turned on.
The occurrence loss of a can be suppressed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of a three-level inverter bridge.

FIG. 2 is a diagram showing a simplified structure of a three-level inverter bridge according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a simplified structure of a three-level inverter bridge according to a second embodiment of the present invention.

FIG. 4 is a diagram showing a simplified structure of a three-level inverter bridge according to a third embodiment of the present invention.

FIG. 5 is a diagram showing a simplified structure of a three-level inverter bridge according to a fourth embodiment of the present invention.

FIG. 6 is a diagram showing a simplified structure of a conventional three-level inverter bridge.

FIG. 7 is a diagram showing a circuit operation of a three-level inverter bridge in a conventional inverter device.

FIG. 8 is a diagram showing a circuit operation of a three-level inverter bridge in a conventional inverter device.

FIG. 9 is a diagram showing a circuit operation of a three-level inverter bridge in a conventional inverter device.

FIG. 10 is a diagram showing a circuit operation of a three-level inverter bridge in a conventional inverter device.

FIG. 11 is a diagram illustrating a bypass path of the three-level inverter bridge of FIG. 6;

FIG. 12 is a diagram illustrating a bypass path of the three-level inverter bridge of FIG. 6;

FIG. 13 is a diagram showing a circulating current path of the three-level inverter bridge of FIG. 6;

[Explanation of symbols]

1 DC voltage circuit, 2a-2d GCT, 3a-3d
Freewheel diode, 4a, 4b Anode reactor, 5a, 5b Reset diode, 6a, 6b
Reset resistor, 7a, 7b Clamp capacitor, 8
a to 8o cooling fins, 9 first press-contact structure, 10
2nd press contact structure, 11a-11p copper bus bar, 13
a, 13b Clamp diode.

Claims (4)

[Claims] 1. An inverter device comprising: a DC voltage circuit having three potentials of potentials P and N and an intermediate potential C; and a three-level inverter bridge capable of outputting each potential, wherein the three-level inverter is provided. The bridge includes first to fourth self-extinguishing semiconductor devices connected in series, first to fourth freewheeling diodes connected in anti-parallel to the self-extinguishing semiconductor devices, and the DC voltage circuit. A first clamp diode connected between the terminal of the potential C and the anode terminal of the second self-extinguishing semiconductor device;
A second clamp diode connected between the cathode terminal of the third self-extinguishing type semiconductor device and the terminal of the potential C of the DC voltage circuit; A first anode reactor connected between the anode terminal of the arc-extinguishing type semiconductor device, a first reset diode and a first reset resistor connected in parallel to the first anode reactor. The DC voltage circuit is connected between a series connection, a connection point between a first reset diode and a first reset resistor, and a terminal of the potential C of the DC voltage circuit, and only via the first reset resistor. A first clamp capacitor that can be discharged to the second anode reactor connected between the anode terminal of the fourth self-extinguishing semiconductor device and the terminal of the potential N of the DC voltage circuit; A second series connection body including a second reset diode and a second reset resistor connected in parallel to the anode reactor; a connection point between the second reset diode and the second reset resistor; and the DC voltage circuit A second self-extinguishing type semiconductor element and a third self-extinguishing type semiconductor element, which are connected between the terminal and the third self-extinguishing type semiconductor element. A bridge circuit having an output terminal provided at a connection point with the arc type semiconductor element, wherein each of the self-extinguishing type semiconductor elements, each freewheel diode, and the first and second clamp diodes are respectively provided. It is configured as a separate semiconductor package, and cooling fins each functioning as a conductor are interposed between the semiconductor packages, and they are connected to each other. To form a pressure contact structure by co-fastening in pressure contact with the conductive direction, the cathode side and the first of the first self-extinguishing type semiconductor device of the pressure-contacting structure
, The cathode side of the second freewheel diode and the cathode side of the first clamp diode, the anode side of the fourth self-extinguishing semiconductor device, the anode side of the second clamp diode, and the third side.
Wherein the anode side of the freewheel diode and the anode side of the second clamp diode are connected by a copper bus bar. 2. An inverter device comprising: a DC voltage circuit having three potentials P and N and an intermediate potential C; and a three-level inverter bridge capable of outputting each of the potentials, wherein the three-level inverter is provided. The bridge includes first to fourth self-extinguishing semiconductor devices connected in series, first to fourth freewheeling diodes connected in anti-parallel to the self-extinguishing semiconductor devices, and the DC voltage circuit. A first clamp diode connected between the terminal of the potential C and the anode terminal of the second self-extinguishing semiconductor device;
A second clamp diode connected between the cathode terminal of the third self-extinguishing type semiconductor device and the terminal of the potential C of the DC voltage circuit; A first anode reactor connected between the anode terminal of the arc-extinguishing type semiconductor device, a first reset diode and a first reset resistor connected in parallel to the first anode reactor. The DC voltage circuit is connected between a series connection, a connection point between a first reset diode and a first reset resistor, and a terminal of the potential C of the DC voltage circuit, and only via the first reset resistor. A first clamp capacitor that can be discharged to the second anode reactor connected between the anode terminal of the fourth self-extinguishing semiconductor device and the terminal of the potential N of the DC voltage circuit; A second series connection body including a second reset diode and a second reset resistor connected in parallel to the anode reactor; a connection point between the second reset diode and the second reset resistor; and the DC voltage circuit A second self-extinguishing type semiconductor element and a third self-extinguishing type semiconductor element, which are connected between the terminal and the third self-extinguishing type semiconductor element. A bridge circuit having an output terminal provided at a connection point with the arc type semiconductor element, wherein each of the self-extinguishing type semiconductor elements, each freewheel diode, and the first and second clamp diodes are respectively provided. It is configured as a separate semiconductor package, and cooling fins functioning as conductors are interposed between each semiconductor package, and they are connected in the direction of conduction. The current-carrying direction of the first pressure-welded structure and the first and second reset diodes which are crimped and fastened together, and the cooling fin which is coupled to each reset diode and functions as a conductor without passing through a reset resistor. An inverter device comprising a second pressure-contact structure that is pressed against and fastened to the second pressure-contact structure. 3. A second insulation displacement structure is coupled to the first and second reset diodes and to each reset diode.
3. The inverter device according to claim 2, wherein the cooling fin functioning as a conductor and the first and second clamp capacitors are fastened together. 4. An inverter device comprising: a DC voltage circuit having three potentials P and N and an intermediate potential C; and a three-level inverter bridge capable of outputting each of the potentials, wherein the three-level inverter is provided. The bridge includes first to fourth self-extinguishing semiconductor devices connected in series, first to fourth freewheeling diodes connected in anti-parallel to the self-extinguishing semiconductor devices, and the DC voltage circuit. A first clamp diode connected between the terminal of the potential C and the anode terminal of the second self-extinguishing semiconductor device;
A second clamp diode connected between the cathode terminal of the third self-extinguishing type semiconductor device and the terminal of the potential C of the DC voltage circuit; A first anode reactor connected between the anode terminal of the arc-extinguishing type semiconductor device, a first reset diode and a first reset resistor connected in parallel to the first anode reactor. The DC voltage circuit is connected between a series connection, a connection point between a first reset diode and a first reset resistor, and a terminal of the potential C of the DC voltage circuit, and only via the first reset resistor. A first clamp capacitor that can be discharged to the second anode reactor connected between the anode terminal of the fourth self-extinguishing semiconductor device and the terminal of the potential N of the DC voltage circuit; A second series connection body including a second reset diode and a second reset resistor connected in parallel to the anode reactor; a connection point between the second reset diode and the second reset resistor; and the DC voltage circuit A second self-extinguishing type semiconductor element and a third self-extinguishing type semiconductor element, which are connected between the terminal and the third self-extinguishing type semiconductor element. A bridge circuit having an output terminal provided at a connection point with the arc type semiconductor element, wherein each of the self-extinguishing type semiconductor elements, each freewheel diode, and the first and second clamp diodes are respectively provided. It is configured as a separate semiconductor package, and cooling fins functioning as conductors are interposed between each semiconductor package, and they are connected in the direction of conduction. Cooling fins functioning as electric conductors are interposed between the first pressure-welded structure and the first reset diode and the reset resistor, and the second reset diode and the reset resistor, which are jointly fastened by pressing, and energized. A second pressure-welded structure pressed together in the direction and co-tightened, and a copper bus bar for connecting the two pressure-welded structures and the DC voltage circuit so as to constitute the bridge circuit, and a first pressure-welded structure; A copper bus bar for connecting the second pressure welding structure and the terminal of the potential C of the DC voltage circuit is constituted by two copper bus bars connected in parallel, and one copper bus bar is connected to the terminal of the potential P. , And the other copper bus bar is disposed close to a copper bus bar connected to a terminal of a potential N.