JP2000150958A - Semiconductor light emitting device - Google Patents
Semiconductor light emitting deviceInfo
- Publication number
- JP2000150958A JP2000150958A JP32383498A JP32383498A JP2000150958A JP 2000150958 A JP2000150958 A JP 2000150958A JP 32383498 A JP32383498 A JP 32383498A JP 32383498 A JP32383498 A JP 32383498A JP 2000150958 A JP2000150958 A JP 2000150958A
- Authority
- JP
- Japan
- Prior art keywords
- light emitting
- layer
- semiconductor layer
- semiconductor
- emitting device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
- H01L33/385—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending at least partially onto a side surface of the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、基板に絶縁性基板
を用いた半導体発光素子に関する。[0001] The present invention relates to a semiconductor light emitting device using an insulating substrate as a substrate.
【０００２】[0002]
【従来の技術】例えば、サファイア基板上に窒化ガリウ
ム系の半導体層を備える発光素子のように、基板に絶縁
性基板を用いる半導体発光素子においては、素子の表面
側にｐ型とｎ型の電極を形成し、これらの電極にワイヤ
ボンディングを施して配線を行っていた。しかしなが
ら、組み立て作業性が悪い、信頼性が悪い等の理由によ
って、例えば特開平成8―３３０６３１号公報に開示さ
れているように、所定の半導体層の側面から絶縁性基板
の側面に渡って電極を形成することが提案されている。2. Description of the Related Art For example, in a semiconductor light emitting device using an insulating substrate as a substrate, such as a light emitting device having a gallium nitride based semiconductor layer on a sapphire substrate, p-type and n-type electrodes are provided on the surface side of the device. And wire bonding is performed on these electrodes to perform wiring. However, due to poor assembly workability and poor reliability, for example, as disclosed in Japanese Patent Application Laid-Open No. Hei 8-330631, an electrode extends from a side surface of a predetermined semiconductor layer to a side surface of an insulating substrate. It has been proposed to form
【０００３】しかしながら、上記公報にて提案の構造は
いずれも、側面電極を形成するための工程数が多いとと
もに、素子分離用の溝の中に電極形成を行うので、レジ
スト用パターン等の形成を高精度に行う必要が有り、汎
用性にかけるという課題がある。However, all of the structures proposed in the above-mentioned publications require a large number of steps for forming side electrodes, and since electrodes are formed in trenches for element isolation, the formation of a resist pattern or the like is not possible. It needs to be performed with high precision, and there is a problem of applying to versatility.
【０００４】[0004]
【発明が解決しようとする課題】そこで本発明は、組立
作業性が良い半導体発光素子を提供することを課題の１
つとする。また、製造時の工数増加や精度の低下を防ぐ
ことができる半導体発光素子を提供することを課題の１
つとする。SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor light emitting device having good assembling workability.
One. Another object of the present invention is to provide a semiconductor light emitting device that can prevent an increase in man-hours and a decrease in accuracy during manufacturing.
One.
【０００５】[0005]
【課題を解決するための手段】本発明の半導体発光素子
は、絶縁性基板の上に第1の半導体層を備え、この第1の
半導体層の上に発光層を挟んで第2の半導体層を備える
半導体発光素子において、この発光素子の1つの側面に
導電物質層を形成し、この側面と平行に素子の表面から
前記発光層を貫通して前記第1の半導体層の途中までの
深さの溝を形成したことを特徴とする。A semiconductor light emitting device according to the present invention comprises a first semiconductor layer on an insulating substrate, and a second semiconductor layer with a light emitting layer interposed on the first semiconductor layer. In a semiconductor light-emitting device comprising: a conductive material layer is formed on one side surface of the light-emitting device, and a depth from the surface of the device in parallel with the side surface through the light-emitting layer to a depth of the first semiconductor layer. Is formed.
【０００６】本発明の半導体発光素子は、絶縁性基板の
上に第1の半導体層を備え、この第1の半導体層の上に発
光層を挟んで第2の半導体層を備える半導体発光素子に
おいて、この発光素子の上面の内、素子の１つの側面に
近接した位置にワイヤボンド用の電極を形成し、前記側
面と対面する側面に導電物質層を形成し、この側面と平
行に素子の上面から前記発光層を貫通して前記第1の半
導体層の途中までの深さの溝を形成したことを特徴とす
る。A semiconductor light emitting device according to the present invention comprises a first semiconductor layer on an insulating substrate, and a second semiconductor layer on the first semiconductor layer with a light emitting layer interposed therebetween. An electrode for wire bonding is formed at a position close to one side surface of the light emitting device, and a conductive material layer is formed on a side surface facing the side surface, and the upper surface of the device is parallel to the side surface. A groove extending through the light emitting layer to a depth halfway through the first semiconductor layer is formed.
【０００７】[0007]
【発明の実施の形態】以下本発明の実施例を、絶縁性の
サファイヤ基板の上に窒化ガリウム系の半導体層を結晶
成長して構成した青色系の半導体発光素子を例にとって
説明する。図１は、本発明の１実施例に係る半導体発光
素子１の斜視図であって、この素子1は、厚さが１００
μｍ程度のサファイア基板（絶縁性基板）２の上に、有
機金属化学的気相成長法（ＭＯＣＶＤ法）によって第1
の半導体層３、発光層４、第2の半導体層５を順次結晶
成長させて形成している。第1の半導体層３は、例え
ば、基板2の上に必要に応じてＧａＮ，ＡｌＧａＮ，Ａ
ｌＮ等のバッファ層を介在してｎ型のＧａＮ層、ｎ型の
クラッド層（ＡｌＧａＮ）等のｎ型ＧａＮ系の層を積層
して構成することができる。発光層４は、ＧａＮやＩｎ
ＧａＮなどの単層構造、もしくは、ＩｎＧａＮの混晶比
を変えて構成した多重量子井戸構造のものを用いること
ができる。第２の半導体層５は、例えば、発光層４の上
に位置してｐ型のクラッド層（ＡｌＧａＮ）、その上に
位置するｐ型のキャップ層（ＧａＮ）等のｐ型のＧａＮ
系の層を積層して構成することができる。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to a blue semiconductor light emitting device in which a gallium nitride semiconductor layer is formed by crystal growth on an insulating sapphire substrate. FIG. 1 is a perspective view of a semiconductor light emitting device 1 according to one embodiment of the present invention.
On a sapphire substrate (insulating substrate) 2 of about μm, a first metalorganic chemical vapor deposition (MOCVD) method is used.
The semiconductor layer 3, the light emitting layer 4, and the second semiconductor layer 5 are formed by sequentially growing crystals. The first semiconductor layer 3 is, for example, formed on the substrate 2 by GaN, AlGaN, A
An n-type GaN layer such as an n-type GaN layer and an n-type clad layer (AlGaN) can be stacked with a buffer layer such as 1N interposed therebetween. The light emitting layer 4 is made of GaN or In.
A single layer structure such as GaN or a multiple quantum well structure formed by changing the mixed crystal ratio of InGaN can be used. The second semiconductor layer 5 is, for example, a p-type cladding layer (AlGaN) located on the light-emitting layer 4 and a p-type GaN such as a p-type cap layer (GaN) located thereon.
It can be configured by stacking system layers.
【０００８】第2の半導体層５の上には、透明電極（Ｎ
ｉ／Ａｕ）６を介在してｐ型の電極（Ｎｉ／Ａｕ）７が
形成されている。このｐ型の電極７は、素子の１つの側
面８の近傍、好ましくは素子１の上面９の隅部分に位置
して形成している。透明電極６は必ずしも必要ではな
く、電流分布を広く確保する場合に設けられる。On the second semiconductor layer 5, a transparent electrode (N
A p-type electrode (Ni / Au) 7 is formed with i / Au) 6 interposed therebetween. The p-type electrode 7 is formed in the vicinity of one side surface 8 of the element, preferably at a corner of the upper surface 9 of the element 1. The transparent electrode 6 is not always necessary and is provided when a wide current distribution is ensured.
【０００９】発光素子１の前記側面８と対面する１つの
側面１０には、ｎ電極１１を構成する例えばＴｉ／Ａｌ
等の導電物質層が側面１０の全面を覆うように形成され
ている。発光素子１の上面９には、前記ｎ電極１１が形
成された側面１０と平行に、しかも当該側面１０と若干
の間隔を持った位置に、素子１の上から発光層４を貫通
して第1の半導体層３の途中に至る電流遮断用の溝１２
が形成されている。素子１の裏面には、必要に応じて反
射用の被膜１３が形成されている。この被膜１３は、前
記側面１０に形成された電極材料と同じ材料で構成する
こともできる。On one side surface 10 facing the side surface 8 of the light emitting element 1, for example, Ti / Al
Is formed so as to cover the entire side surface 10. On the upper surface 9 of the light-emitting element 1, the light-emitting layer 4 is penetrated from above the element 1 at a position parallel to the side surface 10 on which the n-electrode 11 is formed and at a slight distance from the side surface 10. Current interrupting groove 12 reaching the middle of one semiconductor layer 3
Are formed. A reflection coating 13 is formed on the back surface of the element 1 as necessary. The coating 13 can be made of the same material as the electrode material formed on the side surface 10.
【００１０】次に、上記発光素子１の製造方法につい
て、図3、図4を参照して説明する。まず、絶縁性基板と
して厚さが１００〜３００μｍのサファイヤ基板２ａを
用意し、ＭＯＣＶＤ法によって第１の半導体層３、発光
層４、第２の半導体層５を順次積層する（図３（ａ）参
照）。次に、上記のウエハにドライエッチング等によっ
て幅５μｍ程度の溝１２を素子１の幅と同等の間隔（３
００μｍ前後）をもってストライプ状に複数形成する
(図３（ｂ）参照)。この溝１２は、発光層４を貫通して
第１の半導体層３の途中で止まる深さに形成されてい
る。Next, a method for manufacturing the light emitting device 1 will be described with reference to FIGS. First, a sapphire substrate 2a having a thickness of 100 to 300 μm is prepared as an insulating substrate, and a first semiconductor layer 3, a light emitting layer 4, and a second semiconductor layer 5 are sequentially laminated by MOCVD (FIG. 3A). reference). Next, a groove 12 having a width of about 5 μm is formed in the above wafer by a dry etching or the like at an interval (3
(About 00 μm) to form a plurality of stripes
(See FIG. 3 (b)). The groove 12 is formed to a depth that penetrates the light emitting layer 4 and stops in the middle of the first semiconductor layer 3.
【００１１】次に、第２の半導体層５のみを覆うように
透明電極を形成するとともに、その上に、ｐ型の電極７
をパターン形成する（図３（ｃ）参照）。その次に、サ
ファイヤ基板２ａを研磨して厚さが１００μｍ程度の基
板２とした後、この裏面に蒸着によってＡｌ等を主体と
する反射被膜１３を形成する（図３（ｄ）参照）。Next, a transparent electrode is formed so as to cover only the second semiconductor layer 5, and a p-type electrode 7 is formed thereon.
(See FIG. 3C). Next, the sapphire substrate 2a is polished to obtain a substrate 2 having a thickness of about 100 μm, and a reflective film 13 mainly composed of Al or the like is formed on the rear surface by vapor deposition (see FIG. 3D).
【００１２】次に、溝１２から一定の間隔を保ってダイ
ヤモンドポイントによるスクライブラインの形成を行
い、このラインに沿ってウエハをブレイクしてバー状体
１ａに分割する（図４（ｅ）参照）。Next, a scribe line is formed by diamond points at a constant distance from the groove 12, and the wafer is broken along the line to divide the wafer into bar-like bodies 1a (see FIG. 4E). .
【００１３】次に、前記バー状体１ａを、溝１２に近接
した分割側面１０が上になるように配置するとともに、
このバー状体１ａの電極７などが形成された上面９を被
覆するための前記バー状体１ａと同等形状のシリコンな
どによって形成した保護バー１４を用意し、この保護バ
ー１４を前記バー状体１ａと密着対面させて配置する
（図４（ｆ）参照）。そして、その上からｎ電極材料と
なるＡｌ／Ｔｉを蒸着等によって成膜することによっ
て、バー状体１ａの側面１０に第１半導体層３と電気的
に接続したｎ電極１１を形成する（図４（ｇ）参照）。Next, the bar-shaped member 1a is arranged so that the divided side surface 10 adjacent to the groove 12 faces upward.
A protection bar 14 made of silicon or the like having the same shape as the bar-shaped body 1a for covering the upper surface 9 of the bar-shaped body 1a on which the electrodes 7 and the like are formed is prepared. It is arranged so as to be in close contact with 1a (see FIG. 4 (f)). Then, an n-electrode 11 electrically connected to the first semiconductor layer 3 is formed on the side surface 10 of the bar-shaped body 1a by forming a film of Al / Ti serving as an n-electrode material thereon by vapor deposition or the like. 4 (g)).
【００１４】次に、前記バー状体１ａの側面１０と被膜
１３が形成された底面にダイヤモンドポイント等による
ポイントスクライブを行った後、バー状体１ａをブレー
クして個々に分離することによって、図１に示すような
素子１ができあがる。Next, after performing a point scribing with a diamond point or the like on the side surface 10 and the bottom surface on which the coating 13 is formed of the bar-like body 1a, the bar-like body 1a is broken and separated individually. An element 1 as shown in FIG. 1 is completed.
【００１５】この素子１は、例えば図２に示すように、
金属フレーム２０のカップ部分２１に導電性接着剤２２
を介して固定され、ワイヤボンドによってリード２３か
らｐ電極７に金線２４を配線することによって、ＬＥＤ
表示器に組み込まれる。そして、金属フレーム２０を接
地し、リード２３に所定の正電位を印加することによっ
て、金線２４、ｐ電極７、透明電極６、第２半導体層
５、発光層４、第１半導体層３、ｎ電極１１、導電性接
着剤２２、の経路で電流を流すことができる。このよう
に、発光素子１は、絶縁性基板２の側面１０に第１半導
体層３に電気的に接続したｎ電極１１を設けているの
で、従来の導電性基板を備えるＬＥＤ素子と同様の手順
でＬＥＤ表示器に組み込むことができ、表示器の組立作
業性を従来と同等に保つことができる。This element 1 is, for example, as shown in FIG.
A conductive adhesive 22 is applied to the cup portion 21 of the metal frame 20.
And the gold wire 24 is wired from the lead 23 to the p-electrode 7 by wire bonding.
Built into the display. Then, by grounding the metal frame 20 and applying a predetermined positive potential to the lead 23, the gold wire 24, the p electrode 7, the transparent electrode 6, the second semiconductor layer 5, the light emitting layer 4, the first semiconductor layer 3, A current can flow through the path of the n-electrode 11 and the conductive adhesive 22. As described above, since the light emitting element 1 is provided with the n-electrode 11 electrically connected to the first semiconductor layer 3 on the side surface 10 of the insulating substrate 2, the same procedure as the LED element having the conventional conductive substrate is used. Thus, the LED display can be incorporated into the LED display, and the assembling workability of the display can be maintained at the same level as before.
【００１６】また、素子１はその上面９に、第２の半導
体層５、発光層４を貫通する絶縁用の溝１２を側面１０
に近接して設け、溝12を挟んで位置する第２の半導体層
５、発光層４を電気的に絶縁しているので、ｎ電極１１
を素子１の側面１０の全面に形成することができ、この
ｎ電極１１のパターニングなどの後工程を不要として作
業工数の削減を図ることができる。さらにまた、ｎ電極
１１の形成された素子側面１０と対面する側面８に近接
してｐ電極７を形成しているので、ｐｎ電極７，１１の
間隔を長く保って第１、第２の半導体層３，５を通過す
る電流の経路を広く確保することができる。On the upper surface 9 of the element 1, an insulating groove 12 penetrating the second semiconductor layer 5 and the light emitting layer 4 is formed on a side surface 10 thereof.
, And electrically insulates the second semiconductor layer 5 and the light emitting layer 4 located with the groove 12 interposed therebetween.
Can be formed on the entire side surface 10 of the element 1, and a post-process such as patterning of the n-electrode 11 is not required, so that the number of working steps can be reduced. Furthermore, since the p-electrode 7 is formed close to the side face 8 facing the element side face 10 on which the n-electrode 11 is formed, the first and second semiconductors are maintained while keeping the interval between the pn electrodes 7 and 11 long. A wide path for the current passing through the layers 3 and 5 can be secured.
【００１７】尚、前記溝１２は、電極６を設けた後に形
成することもできる。また、溝12は、ダイシングなどに
よって機械的に形成することもできる。The grooves 12 can be formed after the electrodes 6 are provided. Also, the groove 12 can be formed mechanically by dicing or the like.
【００１８】[0018]
【発明の効果】以上のように本発明によれば、絶縁性基
板型の半導体発光素子でありながら、表示器に組み込む
場合の組立作業性が良い半導体発光素子を提供すること
をができる。また、製造時の工数増加や精度の低下を防
ぐことができる半導体発光素子を提供することができ
る。As described above, according to the present invention, it is possible to provide a semiconductor light emitting device which is an insulated substrate type semiconductor light emitting device and has good assembling workability when incorporated into a display. In addition, it is possible to provide a semiconductor light emitting device capable of preventing an increase in man-hours during manufacturing and a decrease in accuracy.
【図１】本発明の発光素子の一実施例を示す斜視図あ
る。FIG. 1 is a perspective view showing one embodiment of a light emitting device of the present invention.
【図２】本発明の発光素子を組み込んだ表示器の要部断
面図である。FIG. 2 is a cross-sectional view of a main part of a display incorporating the light emitting device of the present invention.
【図３】本発明の発光素子の製造手順を示す説明図であ
る。FIG. 3 is an explanatory view showing a manufacturing procedure of the light emitting device of the present invention.
【図４】本発明の発光素子の製造手順を示す説明図であ
る。FIG. 4 is an explanatory view showing a manufacturing procedure of the light emitting device of the present invention.
１ 半導体発光素子 ２ サファイヤ基板（絶縁性基板） ３ 第１の半導体層 ４ 発光層 ５ 第２の半導体層 ７ ｐ電極 １１ ｎ電極（導電物質層） １２ 溝 REFERENCE SIGNS LIST 1 semiconductor light emitting element 2 sapphire substrate (insulating substrate) 3 first semiconductor layer 4 light emitting layer 5 second semiconductor layer 7 p electrode 11 n electrode (conductive material layer) 12 groove
Claims (2)
え、この第1の半導体層の上に発光層を挟んで第2の半導
体層を備える半導体発光素子において、この発光素子の
1つの側面に導電物質層を形成し、この側面と平行に素
子の表面から前記発光層を貫通して前記第1の半導体層
の途中までの深さの溝を形成したことを特徴とする半導
体発光素子。1. A semiconductor light emitting device comprising: a first semiconductor layer on an insulating substrate; and a second semiconductor layer on the first semiconductor layer with a light emitting layer interposed therebetween.
A semiconductor, wherein a conductive material layer is formed on one side surface, and a groove having a depth halfway through the first semiconductor layer is formed through the light emitting layer from the surface of the element in parallel with the side surface. Light emitting element.
え、この第1の半導体層の上に発光層を挟んで第2の半導
体層を備える半導体発光素子において、この発光素子の
上面の内、素子の１つの側面に近接した位置にワイヤボ
ンド用の電極を形成し、前記側面と対面する側面に導電
物質層を形成し、この側面と平行に素子の上面から前記
発光層を貫通して前記第1の半導体層の途中までの深さ
の溝を形成したことを特徴とする半導体発光素子。2. A semiconductor light emitting device comprising: a first semiconductor layer on an insulating substrate; and a second semiconductor layer on the first semiconductor layer with a light emitting layer interposed therebetween. Of these, an electrode for wire bonding is formed at a position close to one side surface of the device, a conductive material layer is formed on a side surface facing the side surface, and the light emitting layer penetrates from the upper surface of the device in parallel with the side surface. A groove having a depth halfway through the first semiconductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32383498A JP2000150958A (en) | 1998-11-13 | 1998-11-13 | Semiconductor light emitting device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32383498A JP2000150958A (en) | 1998-11-13 | 1998-11-13 | Semiconductor light emitting device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000150958A true JP2000150958A (en) | 2000-05-30 |
Family
ID=18159123
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32383498A Pending JP2000150958A (en) | 1998-11-13 | 1998-11-13 | Semiconductor light emitting device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000150958A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100999725B1 (en) | 2010-03-08 | 2010-12-08 | 엘지이노텍 주식회사 | Light emitting device, method for fabricating the light emitting device and light emitting device package |
| KR101021005B1 (en) | 2010-03-10 | 2011-03-09 | 엘지이노텍 주식회사 | Light emitting device, method for fabricating the light emitting device and light emitting device package |
| EP2390933A1 (en) * | 2010-05-24 | 2011-11-30 | Kabushiki Kaisha Toshiba | Semiconductor light emitting device |
| CN103296166A (en) * | 2012-02-24 | 2013-09-11 | 新世纪光电股份有限公司 | Light emitting diode assembly and flip chip type light emitting diode packaging assembly |
| US8772806B2 (en) | 2010-03-08 | 2014-07-08 | Lg Innotek Co., Ltd. | Light emitting device |
-
1998
- 1998-11-13 JP JP32383498A patent/JP2000150958A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100999725B1 (en) | 2010-03-08 | 2010-12-08 | 엘지이노텍 주식회사 | Light emitting device, method for fabricating the light emitting device and light emitting device package |
| US8772806B2 (en) | 2010-03-08 | 2014-07-08 | Lg Innotek Co., Ltd. | Light emitting device |
| KR101021005B1 (en) | 2010-03-10 | 2011-03-09 | 엘지이노텍 주식회사 | Light emitting device, method for fabricating the light emitting device and light emitting device package |
| EP2390933A1 (en) * | 2010-05-24 | 2011-11-30 | Kabushiki Kaisha Toshiba | Semiconductor light emitting device |
| US8729592B2 (en) | 2010-05-24 | 2014-05-20 | Kabushiki Kaisha Toshiba | Semiconductor light emitting device |
| CN103296166A (en) * | 2012-02-24 | 2013-09-11 | 新世纪光电股份有限公司 | Light emitting diode assembly and flip chip type light emitting diode packaging assembly |
| CN103296166B (en) * | 2012-02-24 | 2016-03-02 | 新世纪光电股份有限公司 | Light emitting diode assembly and flip chip type light emitting diode packaging assembly |
| CN105742436A (en) * | 2012-02-24 | 2016-07-06 | 新世纪光电股份有限公司 | Light emitting diode assembly and flip chip type light emitting diode packaging assembly |
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