JP2000150879A - Semiconductor and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method by which thinning of a silicide film can be prevented, a film be made uniform in thickness, and a silicide be made low in resistance. SOLUTION: This semiconductor device is provided with a gate polysilicon film 109, an oxide film 106 on the side of gate polysilicon which is lower in height that the side surface of the gate polysilcon film 109, a side wall 108 which is higher in height than the oxide film 106 and gate polysilicon film 109 and is formed on the side of the oxide film 106, and a silicide film 111 which is formed on the upper surfaces of the gate polysilicon film 109 and oxide film 106 while using the side wall 108 as a wall.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a structure of a MOS transistor having a silicide film having a uniform thickness and a low resistance, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, techniques in such a field include:
For example, there is one disclosed in Japanese Patent Application Laid-Open No. 9-23008.

[0003] With the miniaturization of semiconductor elements, high integration and high speed of LSI have been promoted. On the other hand, increase in gate, source, and drain resistance has become a problem due to miniaturization of the semiconductor element.

In order to solve this problem, attention has been paid to a so-called salicide process in which the resistance of the gate, source and drain can be simultaneously reduced.

[0005] However, etching for excessive sidewall formation and thinning of the sidewall due to miniaturization of the element cause silicide on the gate, source, and the like.
There is a disadvantage that the silicide on the drain is short-circuited.

In order to solve the problem, the following salicide process has been considered.

FIG. 6 is a sectional view showing a manufacturing process of such a conventional semiconductor device, and a salicide process will be described.

(1) First, as shown in FIG. 6 (a), an LOCO is
A 400 nm field oxide film 12 is formed by the S method to partition an active region. Next, the active region is thermally oxidized to form a 16-nm gate oxide film 13, then a 300-nm polysilicon film is deposited, and the polysilicon film is diffused in a 900 ° C. atmosphere of PoCl ₃ . After a 200 nm PSG film is further deposited, the polysilicon film and the PSG film are processed into a gate wiring pattern to form a PSG film 21 and a polysilicon film 14.

Next, the PSG film 21 and the polysilicon
Using the film 14 and the silicon oxide film 12 as a mask, P
⁺The ions are accelerated at an acceleration energy of 30 keV and 2 × 10¹³
cm ^-2Ion implantation into the Si substrate 11 at a dose of
N as D layer^-The diffusion layer 15 is formed.

(2) Next, as shown in FIG.
A 20 nm silicon nitride film is deposited on the entire surface of the Si substrate 11 by the CVD method, and the silicon nitride film 22 is deposited until the upper surface of the PSG film 21 and the surface of the N ⁻ diffusion layer 15 are completely exposed.
Is etched back to form side walls made of the silicon nitride film 22 on the side surfaces of the polysilicon film 14 and the PSG film 21.

(3) Next, as shown in FIG.
By immersing the i-substrate 11 in a diluted hydrofluoric acid solution, the PSG film 21 on the polysilicon film 14 is selectively removed,
The upper surface of the polysilicon film 14 is exposed. The etching rate of the PSG film 21 by the diluted hydrofluoric acid solution is nearly 10 times faster than that of the silicon oxide film 12 formed by thermal oxidation.
1 compared to the silicon nitride film 22 and the polysilicon film 14
Since the speed is more than 00 times, the PSG film 21 can be selectively removed as described above.

Then, using the polysilicon film 14, the silicon nitride film 22 and the silicon oxide film 12 as a mask,
The s ⁺ ions are accelerated at an acceleration energy of 50 keV and 3 × 10
^At a dose of ¹⁵ cm ^-2 , ions are implanted into the Si substrate 11, and high-speed annealing is performed at 1050 ° C. for 10 seconds in a nitrogen atmosphere to form an N ⁺ diffusion layer 17 as a source / drain diffusion layer.
To form

(4) Next, a Ti film having a thickness of 30 nm is
It is deposited on the entire surface of the i-substrate 11. Then, high-speed annealing is performed at 600 ° C. for 30 seconds in a nitrogen atmosphere, and the upper surface of the polysilicon film 14 and the surface of the N ⁺ diffusion layer 17 exposed from the silicon oxide film 12 and the silicon nitride film 22 are contacted with the Ti film. The reaction is performed to form a TiSi ₂ film. Thereafter, the Ti film remaining unreacted on the silicon oxide film 12 and the silicon nitride film 22 is selectively removed with ammonia and hydrogen peroxide, and high-speed annealing is performed again in nitrogen at 800 ° C. for 30 seconds. As shown in FIG. 6D, a low-resistance Ti is formed on the upper surface of the polysilicon film 14 and the surface of the N ⁺ diffusion layer 17.
An Si ₂ film 23 is formed.

[0014]

However, the above-described conventional manufacturing method has a disadvantage that silicidation is inhibited at the interface between the sidewall and the gate polysilicon and uniform silicide cannot be formed (Japanese Patent Laid-Open No. Hei 7 (1994) -107).
-45823 reference).

It is an object of the present invention to provide a semiconductor device which eliminates the above-mentioned problems, prevents formation of a thin silicide film, has a uniform film thickness and can form a low-resistance silicide, and a method of manufacturing the same. Aim.

[0016]

According to the present invention, there is provided a semiconductor device comprising: a gate polysilicon film;
A gate polysilicon side-surface oxide film having a height lower than the height of the side surface of the gate polysilicon film; and a height higher than the height of the gate polysilicon side-surface oxide film and formed on a side portion of the gate polysilicon side-surface oxide film. The semiconductor device includes a sidewall and a silicide film formed on the surface of the gate polysilicon film using the sidewall as a wall.

[2] In the semiconductor device according to [1], when the heights of the gate polysilicon film, sidewall, gate polysilicon side oxide film, and silicide film are Hg, Hsw, Hs, and Hts, respectively, Hg> H
s, Hsw> Hs, Hts ≧ Hg−Hs.

[3] In the method of manufacturing a semiconductor device, a step of etching the gate polysilicon film using the first insulating film as a mask, and a step of forming a second insulating film on a side surface of the gate polysilicon film; Forming a sidewall with a third insulating film; and forming a second insulating film on the side of the gate polysilicon film and all of the first insulating film of the mask.
Selectively removing an upper portion of the insulating film of the first embodiment and performing a heat treatment after depositing the metal film to form silicide on the surface of the gate polysilicon film and the surfaces of the source / drain diffusion layers. It was made.

[4] In the method of manufacturing a semiconductor device according to the above [3], the first insulating film and the second insulating film are silicon oxide films, and the third insulating film is a silicon nitride film. .

[5] In the method of manufacturing a semiconductor device according to [3], the first insulating film is a PSG film, a BSG film or a BPSG film, the second insulating film is a thermal oxide film, and the third insulating film is a third insulating film. The insulating film is an NSG film.

[6] In the method of manufacturing a semiconductor device, after the gate polysilicon film is etched, a first insulating film is formed on the side and upper surfaces of the gate polysilicon film; Forming a wall and removing or partially leaving the first insulating film on the upper surface of the gate polysilicon film at the time of forming the sidewall, leaving only the first insulating film on the side surface of the gate polysilicon film Forming a first side surface of the gate polysilicon film;
The step of selectively removing the upper part of the insulating film of the first embodiment and the step of forming a silicide on the surface of the gate polysilicon film and the surface of the source / drain diffusion layer by performing a heat treatment after depositing the metal film. It was done.

[7] In the method for manufacturing a semiconductor device according to the above [6], the first insulating film is a silicon oxide film, and the second insulating film is a silicon nitride film.

[8] In the method of manufacturing a semiconductor device according to the above [6], the first insulating film is a PSG film, a BSG film or a BPSG film, and the second insulating film is an NSG film.

[0024]

[9] The method for manufacturing a semiconductor device according to the above [3] or [6], wherein a metal particle is deposited by a sputtering method with high straightness of metal particles.

[10] The above

[9] In the method of manufacturing a semiconductor device according to the above, the sputtering method having high straightness
The collimated sputtering or the long throw sputtering is used.

[0026]

Embodiments of the present invention will be described below in detail.

FIG. 1 is a view for explaining a salicide process according to a first embodiment of the present invention, and is a process diagram schematically shown in a sectional view.

(1) First, as shown in FIG. 1A, a LOC is formed on a Si (100) substrate 101 by using a known technique.
A 400 nm field oxide film 102 is formed by the OS method to define an active region.

Next, the active region is thermally oxidized to 16n.
After forming the m gate oxide film 103, a 300 nm polysilicon film is deposited. Further, after depositing a 200 nm PSG film, the polysilicon film and the PSG film are processed into a gate wiring pattern to form a polysilicon film 10.
4. The PSG film 105 is formed. Next, by thermal oxidation
A 0 nm silicon oxide film 106 is formed on the side of the gate.

Next, using the PSG film 105, the polysilicon film 104 and the silicon oxide film 106 as masks, P ⁺ ions are accelerated at an acceleration energy of 30 keV and 2 × 1.
Ions are implanted into the Si substrate 101 at a dose of 0 ¹³ cm ^-2 to form an N ^- diffusion layer 107 as an LDD layer.

(2) Next, as shown in FIG.
A 20 nm silicon nitride film is formed on a Si substrate 101 by a CVD method.
Then, the entire surface of the silicon nitride film is etched back until the upper surface of the PSG film 105 and the surface of the N ⁻ diffusion layer 107 are completely exposed. Polysilicon film 104
And on the side surface of the PSG film 105.

(3) Next, as shown in FIG.
By immersing the i-substrate 101 in a diluted hydrofluoric acid solution, the PSG film 105 on the polysilicon film 104 is selectively removed, the upper surface of the polysilicon film 104 is exposed, and the wet etching is continued to form the polysilicon. The upper portion of the silicon oxide film 106 formed on the side surface of the film 104 is also removed to expose both ends of the upper portion of the polysilicon film 104.

The etching rate of the PSG film 105 by the diluted hydrofluoric acid solution depends on the field oxide film 1 formed by thermal oxidation.
02, which is nearly 10 times faster than the silicon oxide film 106 and 100 times or more faster than the sidewall (silicon nitride film) 108 and the polysilicon film 104, so that the PSG film 105 is selectively removed as described above. In addition, it is possible to remove only the upper portion of the silicon oxide film 106, but not the entirety. Assuming that the upper portion of the silicon oxide film 106 is removed by 300.degree.
After removing the SG film 105, a wet etching process may be performed for about 1 minute.

(4) Thereafter, as shown in FIG.
As ⁺ acceleration energy of 50keV ions and 3 × 1
At a dose of 0 ¹⁵ cm ^-2 , ions are implanted into the polysilicon film 104 and the Si substrate 101 at 1050 ° C. in a nitrogen atmosphere.
By performing high-speed annealing for 10 seconds, the gate polysilicon film 109, the source / drain diffusion layer (N ⁺ diffusion layer) 11
0 is formed.

(5) Next, as shown in FIG.
A 0 nm Ti film is deposited on the entire surface of the Si substrate 101. Then, high-speed annealing is performed at 600 ° C. for 30 seconds in a nitrogen atmosphere to form the gate polysilicon film 1 exposed from the field oxide film 102 and the sidewalls 108.
The Ti film reacts with the top surface of the substrate 09 and the surface of the source / drain diffusion layer 110 to form a TiSi ₂ film.

(6) Thereafter, the T remaining unreacted on the field oxide film 102 and the sidewalls 108
The i-film is selectively removed with aqueous ammonia, and again subjected to high-speed annealing at 800 ° C. for 30 seconds in nitrogen to form low-resistance TiSi _{2 on} the upper surface of the gate polysilicon film 109 and the surface of the N ⁺ diffusion layer 110. A film 111 is formed.

The characteristic feature of the above process is that both ends of the upper portion of the gate polysilicon film 109 are formed on the side wall 1.
08 and not exposed. Therefore, TiS is formed at both ends of the upper portion of the gate polysilicon film 109.
The i ₂ film 111 no longer becomes thinner, and the TiSi ₂ film 111
Are formed uniformly, resulting in low resistance.

Further, since the upper portion of the sidewall 108 is higher than the upper portion of the gate polysilicon film 109 and a groove is formed between the gate polysilicon film 109 and the sidewall 108, the gate, source, and drain due to silicide overgrowth are formed. There is no need to worry about short circuit between them.

As described above, according to the first embodiment, it is possible to prevent the silicide from being thinned at both ends of the upper portion of the gate polysilicon film, so that a silicide having a uniform thickness and low resistance is formed. Becomes possible.

Further, there is no fear of short-circuit between the gate, source and drain due to overgrowth of silicide.

In the above embodiment, Ti silicide has been described as an example, but it may be Co silicide or Ni silicide. Further, the PSG film as a gate etching mask may be another oxide film.

Further, formation of a silicide film in a gate polysilicon portion will be described in detail with reference to FIG.

FIG. 2 is a diagram for explaining a process of forming a silicide film in a gate polysilicon portion according to a second embodiment of the present invention, and is a process diagram schematically shown in a sectional view.

In this embodiment, the first type shown in FIG.
In the embodiment, the polysilicon film 104 and the silicon nitride film (side
Wall) 108, gate polysilicon side oxide film 106, T
iSi _TwoThe height of the film 111 is Hg, Hsw, H
s, Hts, Hg> Hs, Hsw> Hs, H
It is characterized by a structure where ts ≧ Hg−Hs.

As described above, according to the second embodiment, since the upper portion of the gate polysilicon film 109 and the sidewalls 108 are spatially separated from each other, the silicide is formed at both ends of the upper portion of the gate polysilicon film 109 during the subsequent silicide formation. Does not become thinner and silicide is formed uniformly, resulting in lower resistance. Further, the gate polysilicon film 1
Since a groove is formed between the gate electrode 09 and the side wall 108, there is no fear of a short circuit between the gate, source and drain due to overgrowth of the TiSi ₂ film 111.

In this embodiment, the side wall made of a silicon nitride film has been described, but this may be a silicon oxide film.

Next, a third embodiment of the present invention will be described.

This embodiment is the same as the first embodiment except for the metal sputtering step. In other words, in this embodiment, the metal is deposited by the sputtering method in which the metal particles have high rectilinearity. For example, it is assumed that a thin film of silicide is prevented by using collimated sputtering or long throw sputtering for forming a metal, and a low-resistance TiSi ₂ film is formed. That is, by using collimated sputtering or long-throw sputtering for forming Ti in the step of FIG. 1E shown in the first embodiment, thinning of silicide can be prevented, and a low-resistance TiSi ₂ film can be obtained. .

As described above, according to the third embodiment, the step coverage is improved because the collimated sputtering or the long throw sputtering is used for forming the Ti film. Therefore, it is possible to prevent the metal formed on the gate polysilicon film from being thinned.
It is possible to form a low-resistance TiSi ₂ film.

In this embodiment, Ti silicide has been described as an example, but it may be Co silicide or Ni silicide.

Next, a fourth embodiment of the present invention will be described.

FIG. 3 is a view for explaining a salicide process according to a fourth embodiment of the present invention, and is a process diagram schematically shown in a sectional view.

(1) First, as shown in FIG. 3A, a LOC is formed on a Si (100) substrate 201 by using a known technique.
A 400 nm field oxide film 202 is formed by the OS method to define an active region. Next, a 16 nm gate oxide film 203 is formed by thermally oxidizing the active region, and then a 300 nm polysilicon film is deposited. Further, after depositing a 200 nm PSG film, these polysilicon film and PSG film are processed into a gate wiring pattern.
A polysilicon film 204 and a PSG film 205 are formed.

Next, a 30-nm silicon oxide film 206 is formed on the side surface of the gate by thermal oxidation. These PSG film 205, polysilicon film 204 and silicon oxide film 20
6 is used as a mask, P ⁺ ions are implanted into the Si substrate 201 at an acceleration energy of 30 keV and a dose of 2 × 10 ¹³ cm ^−2.
Into the N ⁻ diffusion layer 207 as an LDD layer.
To form

(2) Next, a 220 nm NSG film (non-doped oxide film) is deposited on the entire surface of the Si substrate 201 by the CVD method, and as shown in FIG.
The entire surface of the NSG film is etched back until the upper surface of the NSG film and the surface of the N ⁻ diffusion layer 207 are completely exposed.
And on the side surface of the PSG film 205.

(3) Next, as shown in FIG.
By immersing the i-substrate 201 in a diluted hydrofluoric acid solution, the PSG film 205 on the polysilicon film 204 is selectively removed to expose the upper surface of the polysilicon film 204, and the wet etching is continued to continue the polysilicon film. The upper portion of the silicon oxide film 206 formed on the side surface of the polysilicon film 204 is also removed to expose both ends of the upper portion of the polysilicon film 204.

The etching rate of the PSG film 205 by the diluted hydrofluoric acid solution is determined by the silicon oxide film 20 formed by thermal oxidation.
6 and about 10 times faster than the NSG film 208 and 100 times or more faster than the polysilicon film 204, so that the PSG film 205 can be selectively removed as described above. Only the top, but not all, of 206 can be removed. Assuming that the upper portion of the silicon oxide film 206 is removed by 300 °, P
After the removal of the SG film 205, a wet etching process may be performed for about 1 minute.

(4) Thereafter, as shown in FIG.
As ⁺ acceleration energy of 50keV ions and 3 × 1
At a dose of 0 ¹⁵ cm ^-2 , ions are implanted into the polysilicon film 204 and the Si substrate 201 at 1050 ° C. in a nitrogen atmosphere.
By performing high-speed annealing for 10 seconds, the gate polysilicon film 209 and the source / drain diffusion layers (N ⁺ diffusion layers) 21 are formed.
0 is formed.

(5) Next, as shown in FIG.
A 0 nm Ti film is deposited on the entire surface of the Si substrate 201. Then, high-speed annealing is performed at 600 ° C. for 30 seconds in a nitrogen atmosphere, and the upper surface of the gate polysilicon film 209 and the surface of the source / drain diffusion layer 210 exposed from the sidewall 208 made of the silicon oxide film 202 and the NSG film. And a Ti film to form a TiSi ₂ film.

(6) Thereafter, the Ti film remaining unreacted on the side wall 208 made of the field oxide film 202 and the NSG film is selectively removed with ammonia and hydrogen peroxide, and again in nitrogen at 800.degree. A low-speed TiSi ₂ film 211 is formed on the upper surface of the gate polysilicon film 209 and the surface of the source / drain diffusion layer 210 by performing high-speed annealing for two seconds.

A feature of the above-described process of the fourth embodiment is that both ends of the upper portion of the gate polysilicon film 209 are exposed without being in contact with the sidewall 208.
Therefore, the TiSi ₂ film 211 does not become thinner at both ends above the gate polysilicon film 209, and the
_{Since the two} films 211 are formed uniformly, the resistance becomes low.

Since the upper portion of the sidewall 208 is higher than the upper portion of the gate polysilicon film 209 and a groove is formed between the gate polysilicon film 209 and the sidewall 208, the gate, source, and drain are formed by overgrowth of silicide. There is no need to worry about short circuit between them.

As described above, according to the fourth embodiment, it is possible to prevent the silicide from being thinned at both ends of the upper portion of the gate polysilicon film, so that the silicide having a uniform thickness and low resistance is formed. Becomes possible.

Further, there is no fear of short-circuit between the gate, source and drain due to overgrowth of silicide.

Further, by using an oxide film for the sidewall, unlike a nitride film, there is no need to worry about fluctuation of the threshold voltage due to diffusion of hydrogen.

In the above embodiment, Ti silicide has been described as an example, but it may be Co silicide or Ni silicide. Further, the PSG film as the gate etching mask may be another oxide film.

Next, a fifth embodiment of the present invention will be described.

FIG. 4 is a view for explaining a salicide process according to a fifth embodiment of the present invention, and is a process diagram schematically shown in a sectional view.

(1) First, as shown in FIG. 4A, a LOC is formed on a Si (100) substrate 301 by using a known technique.
A 400 nm field oxide film 302 is formed by the OS method to define an active region.

Next, the active region is thermally oxidized to 16n.
After forming the m gate oxide film 303, a 300 nm polysilicon film is deposited. Further, the polysilicon film is processed into a gate wiring pattern, and a polysilicon film 304 is formed. Next, a 30-nm silicon oxide film 305 is formed on the entire surface of the polysilicon film 304, that is, on the upper surface and side surfaces by thermal oxidation.

[0071] Next, these polysilicon film 304 and the silicon oxide film 305 as a mask, 3 P ⁺ ions
Ions are implanted into the Si substrate 301 at an acceleration energy of 0 keV and a dose of 2 × 10 ¹³ cm ⁻² to form an N ⁻ diffusion layer 306 as an LDD layer.

(2) Next, as shown in FIG.
A 20 nm silicon nitride film is formed on a Si substrate 301 by CVD.
The entire surface of the silicon nitride film is etched back until the surface of the N ^- diffusion layer 306 is completely exposed.
Is formed on the side surface of the polysilicon film 304.

(3) Next, as shown in FIG.
The silicon oxide film 3 formed on the side surface of the polysilicon film 304 by immersing the i-substrate 301 in a diluted hydrofluoric acid solution.
The upper portion of the polysilicon film 304 is removed to expose both ends of the upper portion of the polysilicon film 304.

Silicon oxide film 30 with diluted hydrofluoric acid solution
Since the etching rate of No. 5 is nearly 10 times faster than the side wall (silicon nitride film) 307, the upper portion of the silicon oxide film 305 can be selectively removed as described above. Assuming that the upper portion of the silicon oxide film 305 is removed by 300 °, a wet etching process may be performed for about 1 minute with a 5% HF solution.

(4) Thereafter, as shown in FIG.
As ⁺ ions acceleration energy and 3 × of 50keV
At a dose of 10 ¹⁵ cm ^-2, the polysilicon film 304 and the Si
Ions are implanted into the substrate 301 and 1050 in a nitrogen atmosphere.
The gate polysilicon film 308 and the source / drain diffusion layer (N ⁺ diffusion layer)
309 are formed.

(5) Next, as shown in FIG.
A 0 nm Ti film is deposited on the entire surface of the Si substrate 301. Then, high-speed annealing is performed at 600 ° C. for 30 seconds in a nitrogen atmosphere, and the upper surface of the gate polysilicon film 308 and the surface of the N ⁺ diffusion layer 309 exposed from the silicon oxide film 305 and the side wall (silicon nitride film) 307. And a Ti film to form a TiSi ₂ film.

(6) Thereafter, the Ti film remaining unreacted on the field oxide film 302 and the side wall (silicon nitride film) 307 is selectively removed with ammonia and hydrogen peroxide at 800 ° C. again in nitrogen. A 30-second high-speed anneal is performed to remove the upper surface of the gate polysilicon film 308 and N
^{+ A} low-resistance TiSi ₂ film 310 is formed on the surface of the diffusion layer 309.

The feature of the above-described process of this embodiment is that both ends of the upper portion of the gate polysilicon film 308 are exposed without being in contact with the sidewall 307.
Therefore, the TiSi ₂ film 310 does not become thinner at both ends above the gate polysilicon film 308, and the TiS
Since the i ₂ film 310 is formed uniformly, the resistance becomes low.

Further, since a groove is formed between the gate polysilicon film 308 and the side wall 307, there is no fear of short-circuiting between the gate and source and drain due to overgrowth of silicide.

As described above, according to the fifth embodiment, it is possible to prevent the silicide from being thinned at both ends of the upper portion of the gate polysilicon film, so that the silicide having a uniform thickness and low resistance can be formed. Becomes possible.

Further, there is no fear of short-circuit between the gate, source and drain due to overgrowth of silicide. Since no oxide film is deposited as a gate etching mask, the process is simplified.

In this embodiment, Ti silicide has been described as an example.
i silicide may be used.

Next, a sixth embodiment of the present invention will be described.

FIG. 5 is a view for explaining a salicide process according to a sixth embodiment of the present invention, and is a process diagram schematically shown in a sectional view.

(1) First, as shown in FIG. 5A, a LOC is formed on a Si (100) substrate 401 by using a known technique.
A field oxide film 402 of 400 nm is formed by the OS method to define an active region.

Next, the active region is thermally oxidized to 16n
After forming the m gate oxide film 403, a 300 nm polysilicon film is deposited and processed into a gate wiring pattern. Next, a 30 nm PSG film 405 is formed by CVD.
Is formed on the entire surface of the polysilicon film 404 serving as a gate, that is, on the upper surface and side surfaces.

(2) Next, as shown in FIG. 5B, using these polysilicon film 404 and PSG film 405 as a mask, P ⁺ ions are accelerated at an acceleration energy of 30 keV and 2 × 10 ¹³ cm ^−2. Ions are implanted into the Si substrate 401 at a dose of 3 to form an N ^- diffusion layer 406 as an LDD layer. Next, a 220 nm NSG film is deposited on the entire surface of the Si substrate 401 by the CVD method, and the entire surface of the NSG film is etched back until the surface of the N ^- diffusion layer 406 is completely exposed. A wall 407 is formed on a side surface of the polysilicon film 404.

(3) Next, as shown in FIG.
By immersing the Si substrate 401 in a diluted hydrofluoric acid solution, the upper portion of the PSG film 405 formed on the side surface of the polysilicon film 404 is removed, and both ends of the upper portion of the polysilicon film 404 are exposed. The etching rate of the PSG film 405 by the diluted hydrofluoric acid solution is nearly ten times faster than that of the side wall 407 made of the NSG film.
05 can be selectively removed. Assuming that the upper portion of the silicon film 405 is removed by 300 °, 1% H
For the F solution, wet etching may be performed for about 10 seconds.

(4) Thereafter, as shown in FIG.
As ⁺ ions acceleration energy and 3 × of 50keV
At a dose of 10 ¹⁵ cm ^-2, the polysilicon film 404 and S
Ions are implanted into the i-substrate 401 and 1050 in a nitrogen atmosphere.
The gate polysilicon film 408 and the source / drain diffusion layer (N ⁺ diffusion layer) are subjected to high-speed annealing at 10 ° C. for 10 seconds.
409 are formed.

(5) Next, as shown in FIG.
A 0 nm Ti film is deposited on the entire surface of the Si substrate 401. Then, high-speed annealing is performed at 600 ° C. for 30 seconds in a nitrogen atmosphere, and the upper surface of the gate polysilicon film 408 and the surface of the source / drain diffusion layer 409 exposed from the side wall 407 made of the silicon oxide film 405 and the NSG film. And a Ti film to form a TiSi ₂ film.

(6) Thereafter, the Ti film remaining unreacted on the side wall 407 made of the field oxide film 402 and the NSG film is selectively removed with ammonia and hydrogen peroxide at 800 ° C. and 30 ° C. again in nitrogen. By performing high-speed annealing for two seconds, a low-resistance TiSi ₂ film 410 is formed on the upper surface of the gate polysilicon film 408 and the surface of the source / drain diffusion layer 409.

The characteristic feature of the above-described process of the sixth embodiment is that both ends of the upper portion of the gate polysilicon film 408 are exposed without being in contact with the side walls 407.
Therefore, the TiSi ₂ film 410 does not become thin at both ends above the gate polysilicon film 408, and the TiSi ₂ film 410 becomes thin.
_{Since the two} films 410 are formed uniformly, the resistance becomes low.

Further, since the trench is formed between the gate polysilicon film 408 and the side wall 407, there is no fear of short-circuit between the gate, source and drain due to overgrowth of silicide.

As described above, according to the sixth embodiment, since the silicide at both ends of the upper portion of the gate polysilicon film is prevented from being thinned, it is possible to form a silicide having a uniform thickness and low resistance. It becomes possible.

Further, there is no fear of short-circuit between the gate, source and drain due to overgrowth of silicide.

Further, since no oxide film is deposited as a gate etching mask, the process is simplified.

Further, by using the NSG film for the sidewall, unlike the nitride film, there is no need to worry about fluctuation of the threshold voltage due to diffusion of hydrogen.

According to the above embodiment, Ti silicide has been described as an example.
i silicide may be used.

The present invention is not limited to the above embodiments, but various modifications can be made based on the spirit of the present invention, and these are not excluded from the scope of the present invention.

[0100]

As described above, according to the present invention, the following effects can be obtained.

(A) Since the silicide at both ends above the gate polysilicon film can be prevented from being thinned, the film thickness becomes uniform, and low-resistance silicide can be formed.

(B) There is no fear of short circuit between the gate, source and drain due to overgrowth of silicide.

(C) When the collimated sputtering or the long throw sputtering is used for forming the Ti film, the step coverage is improved.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a salicide process according to a first embodiment of the present invention.

FIG. 2 is a view illustrating a process of forming a silicide film in a gate polysilicon portion according to a second embodiment of the present invention.

FIG. 3 is a diagram illustrating a salicide process according to a fourth embodiment of the present invention.

FIG. 4 is a view for explaining a salicide process according to a fifth embodiment of the present invention.

FIG. 5 is a view for explaining a salicide process according to a sixth embodiment of the present invention.

FIG. 6 is a sectional view showing a manufacturing process of a conventional semiconductor device.

[Explanation of symbols]

101, 201, 301, 401 Si (100) substrate 102, 202, 302, 402 Field oxide film 103, 203, 303, 403 Gate oxide film 104, 204, 304, 404 Polysilicon film 105, 205, 405 PSG film 106 , 206, 305 Silicon oxide films 107, 207, 306, 406 N ^- diffusion layers 108, 208, 307, 407 Side walls 109, 209, 308, 408 Gate polysilicon films 110, 210, 309, 409 Source / drain diffusion layers (N ⁺ diffusion layer) 111, 211, 310, 410 TiSi ₂ film (silicide film)

Claims (10)

[Claims] 1. A semiconductor device, comprising: (a) a gate polysilicon film; and (b) a gate polysilicon side oxide film having a height lower than a height of a side surface of the gate polysilicon film.
(C) a sidewall which is higher than the height of the gate polysilicon side oxide film and is formed on a side of the gate polysilicon side oxide film; and (d) a surface of the gate polysilicon film using the sidewall as a wall. And a silicide film formed on the semiconductor device. 2. The semiconductor device according to claim 1, wherein said gate polysilicon film, side wall, gate polysilicon side-surface oxide film, and silicide film each have a height of H.
g, Hsw, Hs, Hts, Hg> Hs, H
A semiconductor device, wherein sw> Hs and Hts ≧ Hg−Hs. 3. A method for manufacturing a semiconductor device, comprising:
Etching the gate polysilicon film using the first insulating film as a mask; (b) forming a second insulating film on a side surface of the gate polysilicon film; and (c) forming a side surface by the third insulating film. Forming a wall; and (d)
Selectively removing all of the first insulating film of the mask and an upper portion of the second insulating film on the side surface of the gate polysilicon film; and (e) performing heat treatment after depositing the metal film. Forming a silicide on the surface of the gate polysilicon film and the surface of the source / drain diffusion layer. 4. The method for manufacturing a semiconductor device according to claim 3, wherein the first insulating film and the second insulating film are silicon oxide films, and the third insulating film is a silicon nitride film. Manufacturing method of a semiconductor device. 5. The method for manufacturing a semiconductor device according to claim 3, wherein said first insulating film is a PSG film, a BSG film or a BSG film.
A method for manufacturing a semiconductor device, wherein a PSG film, the second insulating film is a thermal oxide film, and the third insulating film is an NSG film. 6. A method for manufacturing a semiconductor device, comprising:
Forming a first insulating film on the side and top surfaces of the gate polysilicon film after etching the gate polysilicon film; (b) forming a sidewall with the second insulating film; and (c). When forming the sidewall, the first insulating film on the upper surface of the gate polysilicon film is removed or partially left, and the first insulating film on the side surface of the gate polysilicon film is removed.
(D) selectively removing an upper portion of the first insulating film on the side surface of the gate polysilicon film, and (e) performing a heat treatment after depositing the metal film. Forming a silicide on the surface of the gate polysilicon film and the surface of the source / drain diffusion layer. 7. The method of manufacturing a semiconductor device according to claim 6, wherein said first insulating film is a silicon oxide film, and said second insulating film is a silicon oxide film.
Wherein the insulating film is a silicon nitride film. 8. The method of manufacturing a semiconductor device according to claim 6, wherein said first insulating film is a PSG film, a BSG film or a BSG film.
A method for manufacturing a semiconductor device, wherein a PSG film and the second insulating film are NSG films. 9. The method of manufacturing a semiconductor device according to claim 3, wherein a metal particle is deposited by a sputtering method with high straightness of metal particles. 10. The method of manufacturing a semiconductor device according to claim 9, wherein a collimated sputtering or a long throw sputtering is used as the highly linear sputtering method.