JP3429208B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor equipment, and more particularly to a manufacturing method of a MOS transistor having a silicide film of the film thickness is less uniform resistance.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
For example, there is one as shown in Japanese Patent Laid-Open No. 9-23008.

Due to the miniaturization of semiconductor elements, high integration and high speed of LSI have been advanced. On the other hand, due to the miniaturization of this semiconductor element, an increase in gate, source, and drain resistance has become a problem.

Therefore, in order to solve this problem, attention has been paid to a so-called salicide process which can simultaneously reduce the resistance of the gate, the source and the drain.

However, due to excessive etching for forming the side wall and thinning of the side wall due to miniaturization of the element, silicide and source on the gate,
There is a drawback that the silicide on the drain is short-circuited.

Therefore, in order to solve the problem, the following salicide process has been considered.

FIG. 6 is a sectional view of the manufacturing process of such a conventional semiconductor device, and the salicide process will be described.

(1) First, as shown in FIG. 6 (a), LOCO is formed on a Si (100) substrate 11 by using a known technique.
A 400 nm field oxide film 12 is formed by the S method to partition the active region. Next, the active region is thermally oxidized to form a gate oxide film 13 having a thickness of 16 nm, a polysilicon film having a thickness of 300 nm is deposited, and the polysilicon film helin is diffused in a PoCl ₃ atmosphere at 900 ° C. Further, a PSG film having a thickness of 200 nm is deposited, and then these polysilicon film and PSG film are processed into a pattern of a gate wiring to form a PSG film 21 and a polysilicon film 14.

Next, using the PSG film 21, the polysilicon film 14, and the silicon oxide film 12 as a mask, P
⁺ Ions with an acceleration energy of 30 keV and 2 × 10 ¹³
LD by implanting ions into the Si substrate 11 at a dose of cm ^-2
An N ⁻ diffusion layer 15 as a D layer is formed.

(2) Next, as shown in FIG.
A 20 nm silicon nitride film is deposited on the entire surface of the Si substrate 11 by the CVD method, and the silicon nitride film 22 is formed until the upper surface of the PSG film 21 and the surface of the N ⁻ diffusion layer 15 are completely exposed.
Is etched back to form side walls of the silicon nitride film 22 on the side surfaces of the polysilicon film 14 and the PSG film 21.

(3) Next, as shown in FIG.
The PSG film 21 on the polysilicon film 14 is selectively removed by immersing the i substrate 11 in a dilute hydrofluoric acid solution,
The upper surface of the polysilicon film 14 is exposed. The etching rate of the PSG film 21 with the diluted hydrofluoric acid solution is about 10 times faster than that of the silicon oxide film 12 formed by thermal oxidation.
1 compared to the silicon nitride film 22 and the polysilicon film 14.
Since it is more than 00 times faster, the PSG film 21 can be selectively removed as described above.

After that, using the polysilicon film 14, the silicon nitride film 22 and the silicon oxide film 12 as a mask, A
Accelerating energy of s ⁺ ions at 50 keV and 3 × 10
Ions are implanted into the Si substrate 11 with a dose amount of ¹⁵ cm ⁻² , and rapid annealing is performed in a nitrogen atmosphere at 1050 ° C. for 10 seconds to form an N ⁺ diffusion layer 17 as a source / drain diffusion layer.
To form.

(4) Next, a Ti film with a thickness of 30 nm is added to the S film.
It is deposited on the entire surface of the i substrate 11. Then, high-speed annealing at 600 ° C. for 30 seconds is performed in a nitrogen atmosphere to remove the upper surface of the polysilicon film 14 exposed from the silicon oxide film 12 and the silicon nitride film 22, the surface of the N ⁺ diffusion layer 17, and the Ti film. The reaction is performed to form a TiSi ₂ film. After that, the Ti film remaining unreacted on the silicon oxide film 12 and the silicon nitride film 22 is selectively removed with ammonia hydrogen peroxide, and high-speed annealing is performed again in nitrogen at 800 ° C. for 30 seconds. As shown in FIG. 6D, Ti having a low resistance is formed on the upper surface of the polysilicon film 14 and the surface of the N ⁺ diffusion layer 17.
The Si ₂ film 23 is formed.

[0014]

However, the above-described conventional manufacturing method has a drawback that silicidation is hindered at the interface between the sidewall and the gate polysilicon, and uniform silicide is not formed (Japanese Patent Laid-Open No. 7-27242).
No. 45823).

The present invention eliminates the above-mentioned problems, and provides a semiconductor device and a method of manufacturing the same, which can prevent the thinning of the silicide, form a uniform film thickness, and form a low-resistance silicide. To aim.

[0016]

In order to achieve the above object, the present invention provides: [ 1 ] In a method of manufacturing a semiconductor device, a step of etching a gate polysilicon film using a first insulating film as a mask; By thermal oxidation on the side surface of the gate polysilicon film
The step of forming the formed second insulating film and the CVD method
A step of forming a side wall by a third insulating film deposited by the above method, and a step of forming all of the first insulating film of the mask and an upper part of the second insulating film on the side surface of the gate polysilicon film.
A step of selectively removing by wet etching and a step of forming a silicide on the surface of the gate polysilicon film and the surface of the source / drain diffusion layer by performing heat treatment after depositing the metal film Is.

[ 2 ] In the method of manufacturing a semiconductor device according to [ 1 ], the first insulating film and the second insulating film are silicon oxide films, and the third insulating film is a silicon nitride film. .

[ 3 ] In the method of manufacturing a semiconductor device according to [ 1 ], the first insulating film is a PSG film, a BSG film or a BPSG film, the second insulating film is a thermal oxide film, and the third insulating film is a third oxide film. The insulating film is an NSG film.

[4] In the method of manufacturing a semiconductor device, after the gate polysilicon film is etched, a step of forming a first insulating film formed by thermal oxidation on a side surface and an upper surface of the gate polysilicon film, and CVD. A step of forming a sidewall by a second insulating film deposited by a method, and when forming the sidewall, the first insulating film on the upper surface of the gate polysilicon film is removed by wet etching to remove the gate polysilicon film. By leaving only the first insulating film on the side surface, selectively removing the upper portion of the first insulating film on the side surface of the gate polysilicon film, and performing heat treatment after depositing the metal film, The step of forming silicide on the surface of the silicon film and the surface of the source / drain diffusion layer is performed.

[ 5 ] In the method of manufacturing a semiconductor device according to [ 4 ], the first insulating film is a silicon oxide film and the second insulating film is a silicon nitride film.

[ 6 ] In the method of manufacturing a semiconductor device according to [ 4 ] above, the first insulating film is a PSG film, a BSG film or a BPSG film, and the second insulating film is an NSG film.

[ 7 ] In the method for manufacturing a semiconductor device according to [ 1 ] or [ 4 ], a metal particle is deposited by a sputtering method which has a high rectilinear property of metal particles.

[ 8 ] In the method of manufacturing a semiconductor device according to the above [ 7 ], a collimated sputtering method or a long throw sputtering method is used as the sputtering method having high straightness.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below.

FIG. 1 is a diagram for explaining a salicide process showing a first embodiment of the present invention, and is a process diagram schematically showing a sectional view.

(1) First, as shown in FIG. 1A, the LOC is formed on the Si (100) substrate 101 using a known technique.
A 400 nm field oxide film 102 is formed by the OS method to partition the active region.

Next, the active region is thermally oxidized to 16n.
m gate oxide film 103 is formed, and then a 300 nm polysilicon film is deposited. Further, after depositing a PSG film having a thickness of 200 nm, these polysilicon film and PSG film are processed into a gate wiring pattern, and then the polysilicon film 10 is formed.
4. The PSG film 105 is formed. Then, 3 by thermal oxidation
A 0 nm silicon oxide film 106 is formed on the side surface of the gate.

Then, with the PSG film 105, the polysilicon film 104 and the silicon oxide film 106 as a mask, P ⁺ ions are accelerated with an acceleration energy of 30 keV and 2 × 1.
Ions are implanted into the Si substrate 101 at a dose of 0 ¹³ cm ⁻² to form an N ⁻ diffusion layer 107 as an LDD layer.

(2) Next, as shown in FIG.
A 20 nm silicon nitride film is formed on the Si substrate 101 by the CVD method.
Then, the entire surface of the silicon nitride film is etched back until the upper surface of the PSG film 105 and the surface of the N ⁻ diffusion layer 107 are completely exposed, and the sidewalls 108 made of this silicon nitride film are formed. Polysilicon film 104
And on the side surface of the PSG film 105.

(3) Next, as shown in FIG.
The PSG film 105 on the polysilicon film 104 is selectively removed by immersing the i substrate 101 in a dilute hydrofluoric acid solution to expose the upper surface of the polysilicon film 104, and wet etching is continued to continue the polysilicon etching. The upper part of the silicon oxide film 106 formed on the side surface of the film 104 is also removed to expose both ends of the upper part of the polysilicon film 104.

The etching rate of the PSG film 105 with the diluted hydrofluoric acid solution is the same as that of the field oxide film 1 formed by thermal oxidation.
02, which is nearly 10 times faster than the silicon oxide film 106 and 100 times faster than the sidewall (silicon nitride film) 108 and the polysilicon film 104. Therefore, the PSG film 105 is selectively removed as described above. In addition, only the upper portion of the silicon oxide film 106 can be removed instead of the entire portion. Assuming that the upper part of the silicon oxide film 106 is removed by 300 Å, the P content of the 5% HF solution becomes P.
After removing the SG film 105, a wet etching process may be continuously performed for about 1 minute.

(4) Then, as shown in FIG.
As ⁺ ions with acceleration energy of 50 keV and 3 × 1
Ions are implanted into the polysilicon film 104 and the Si substrate 101 at a dose amount of 0 ¹⁵ cm ^-2 , and at 1050 ° C. in a nitrogen atmosphere,
High-speed annealing for 10 seconds is performed to form the gate polysilicon film 109, the source / drain diffusion layer (N ⁺ diffusion layer) 11
Form 0.

(5) Next, as shown in FIG.
A 0 nm Ti film is deposited on the entire surface of the Si substrate 101. Then, high-speed annealing is performed at 600 ° C. for 30 seconds in a nitrogen atmosphere to expose the gate polysilicon film 1 exposed from the field oxide film 102 and the sidewall 108.
The upper surface of 09 and the surface of the source / drain diffusion layer 110 are reacted with the Ti film to form a TiSi ₂ film.

(6) After that, T which remains unreacted on the field oxide film 102 and the sidewall 108.
The i film is selectively removed with ammonia-hydrogen peroxide mixture, and high-speed annealing is performed again in nitrogen at 800 ° C. for 30 seconds to form TiSi ₂ having low resistance on the upper surface of the gate polysilicon film 109 and the surface of the N ⁺ diffusion layer 110. The film 111 is formed.

In the above process, it is characteristic that both end portions above the gate polysilicon film 109 are sidewalls 1.
It is exposed without touching 08. Therefore, TiS is formed on both ends of the upper portion of the gate polysilicon film 109.
Since the i ₂ film 111 is not thinned, the TiSi ₂ film 111
Are uniformly formed, resulting in low resistance.

Further, since the upper portion of the sidewall 108 is higher than the upper portion of the gate polysilicon film 109 and the groove is formed between the gate polysilicon film 109 and the sidewall 108, the gate, the source and the drain due to the overgrowth of the silicide. There is no need to worry about short circuits between them.

As described above, according to the first embodiment, it is possible to prevent thinning of the silicide at both ends of the upper portion of the gate polysilicon film, so that the film thickness becomes uniform and low resistance silicide is formed. Is possible.

Further, there is no fear of a short circuit between the gate, the source and the drain due to the overgrowth of the silicide.

In the above embodiment, Ti silicide is taken as an example, but it may be Co silicide or Ni silicide. Further, the PSG film as the gate etching mask may be another oxide film.

Further, formation of the silicide film in the gate polysilicon portion will be described in detail with reference to FIG.

FIG. 2 is a diagram for explaining a process of forming a silicide film of a gate polysilicon portion showing a second embodiment of the present invention, and is a process diagram schematically showing with a sectional view.

In this embodiment, the first shown in FIG.
In the embodiment, the polysilicon film 104, the silicon nitride film (side wall) 108, the gate polysilicon side oxide film 106, T
The height of the iSi ₂ film 111 is set to Hg, Hsw, and H, respectively.
s, Hts, Hg> Hs, Hsw> Hs, H
The structure is characterized by ts ≧ Hg−Hs.

As described above, according to the second embodiment, since the upper portion of the gate polysilicon film 109 and the sidewall 108 are spatially separated, the silicide is formed at both ends of the upper portion of the gate polysilicon film 109 during the subsequent silicide formation. Is not thinned and silicide is uniformly formed, resulting in low resistance. Further, the gate polysilicon film 1
Since the groove is formed between the 09 and the side wall 108, there is no fear of a short circuit between the gate and the source / drain due to overgrowth of the TiSi ₂ film 111.

In this embodiment, the sidewall made of the silicon nitride film has been described, but it may be a silicon oxide film.

Next, a third embodiment of the present invention will be described.

This embodiment is the same as the first embodiment except for the metal sputtering step. That is, in this embodiment, the metal deposition is performed by the sputtering method in which the metal particles are highly straightforward. For example, collimated sputtering or long throw sputtering is used for forming a metal film to prevent thinning of silicide and form a TiSi ₂ film having low resistance. That is, collimating sputtering or long throw sputtering is used for forming Ti in the step (e) of FIG. 1 shown in the first embodiment to prevent silicide thinning and obtain a TiSi ₂ film having low resistance. .

As described above, according to the third embodiment, since the collimated sputtering or the long throw sputtering is used for forming the Ti film, the step coverage is improved. Therefore, since it is possible to prevent thinning of the metal formed on the gate polysilicon film,
It becomes possible to form a TiSi ₂ film having a low resistance.

In this embodiment, Ti silicide has been described as an example, but it may be Co silicide or Ni silicide.

Next, a fourth embodiment of the present invention will be described.

FIG. 3 is a view for explaining a salicide process showing a fourth embodiment of the present invention, and is a process drawing schematically showing a sectional view.

(1) First, as shown in FIG. 3A, the LOC is formed on the Si (100) substrate 201 by using a known technique.
A 400 nm field oxide film 202 is formed by the OS method to partition the active region. Next, the active region is thermally oxidized to form a 16 nm gate oxide film 203, and then a 300 nm polysilicon film is deposited. Further, after depositing a PSG film of 200 nm, these polysilicon film and PSG film are processed into a gate wiring pattern,
A polysilicon film 204 and a PSG film 205 are formed.

Next, a 30 nm silicon oxide film 206 is formed on the side surface of the gate by thermal oxidation. These PSG film 205, polysilicon film 204 and silicon oxide film 20
6 is used as a mask and the Si substrate 201 is irradiated with P ⁺ ions at an acceleration energy of 30 keV and a dose amount of 2 × 10 ¹³ cm ^-2.
Is ion-implanted into the N ⁻ diffusion layer 207 as an LDD layer.
To form.

(2) Next, a 220 nm NSG film (non-doped oxide film) is deposited on the entire surface of the Si substrate 201 by the CVD method, and as shown in FIG.
Of the NSG film is etched back until the upper surface of the NSG film and the surface of the N ^- diffusion layer 207 are completely exposed.
And on the side surface of the PSG film 205.

(3) Next, as shown in FIG.
By immersing the i substrate 201 in a dilute hydrofluoric acid solution, the PSG film 205 on the polysilicon film 204 is selectively removed to expose the upper surface of the polysilicon film 204, and wet etching is continued to continue the polysilicon film. The upper portion of the silicon oxide film 206 formed on the side surface of the 204 is also removed to expose both ends of the upper portion of the polysilicon film 204.

The etching rate of the PSG film 205 with the diluted hydrofluoric acid solution is the same as that of the silicon oxide film 20 formed by thermal oxidation.
6 and the NSG film 208 are nearly 10 times faster and 100 times faster than the polysilicon film 204, the PSG film 205 can be selectively removed as described above, and the silicon oxide film can be removed. Only the top, but not all of 206, can be removed. Assuming that the upper portion of the silicon oxide film 206 is removed by 300 Å, the 5% HF solution causes P
After removing the SG film 205, a wet etching process may be continuously performed for about 1 minute.

(4) Then, as shown in FIG.
As ⁺ ions with acceleration energy of 50 keV and 3 × 1
Ion implantation is performed on the polysilicon film 204 and the Si substrate 201 at a dose of 0 ¹⁵ cm ^-2 , and the ion implantation is performed at 1050 ° C. in a nitrogen atmosphere.
A rapid anneal for 10 seconds is performed to form a gate polysilicon film 209 and a source / drain diffusion layer (N ⁺ diffusion layer) 21.
Form 0.

(5) Next, as shown in FIG.
A 0 nm Ti film is deposited on the entire surface of the Si substrate 201. Then, high-speed annealing is performed at 600 ° C. for 30 seconds in a nitrogen atmosphere, and the upper surface of the gate polysilicon film 209 and the surface of the source / drain diffusion layer 210 exposed from the sidewall 208 formed of the silicon oxide film 202 and the NSG film. Is reacted with the Ti film to form a TiSi ₂ film.

(6) After that, the Ti film remaining unreacted on the side wall 208 formed of the field oxide film 202 and the NSG film is selectively removed by ammonia hydrogen peroxide, and again in nitrogen at 800 ° C. and 30 ° C. A high-speed annealing is performed for a _second to form a low-resistance TiSi ₂ film 211 on the upper surface of the gate polysilicon film 209 and the surface of the source / drain diffusion layer 210.

What is characteristic of the above-described steps of the fourth embodiment is that both ends of the upper portion of the gate polysilicon film 209 are exposed without coming into contact with the sidewalls 208.
Therefore, the TiSi ₂ film 211 is not thinned at both ends above the gate polysilicon film 209, and the TiSi ₂ film 211 is not thinned.
_{Since the two} films 211 are uniformly formed, the resistance becomes low.

Further, since the upper portion of the sidewall 208 is higher than the upper portion of the gate polysilicon film 209 and the groove is formed between the gate polysilicon film 209 and the sidewall 208, the gate, the source and the drain due to the overgrowth of the silicide. There is no need to worry about short circuits between them.

As described above, according to the fourth embodiment, it is possible to prevent the thinning of the silicide at both ends of the upper portion of the gate polysilicon film, so that the film thickness becomes uniform and the low resistance silicide is formed. Is possible.

Further, there is no fear of a short circuit between the gate, the source and the drain due to the overgrowth of the silicide.

Furthermore, since the side wall is made of an oxide film, unlike the nitride film, there is no fear of fluctuation of the threshold voltage due to diffusion of hydrogen.

In the above embodiment, Ti silicide has been described as an example, but it may be Co silicide or Ni silicide. Further, the PSG film as the gate etching mask may be another oxide film.

Next, a fifth embodiment of the present invention will be described.

FIG. 4 is a view for explaining a salicide process showing a fifth embodiment of the present invention, and is a process drawing schematically showing a sectional view.

(1) First, as shown in FIG. 4A, the LOC is formed on the Si (100) substrate 301 by using a known technique.
A 400 nm field oxide film 302 is formed by the OS method to partition the active region.

Next, the active region is thermally oxidized to 16n.
m gate oxide film 303 is formed, and then a 300 nm polysilicon film is deposited. Further, the polysilicon film is processed into a gate wiring pattern to form a polysilicon film 304. Then, a 30 nm-thickness silicon oxide film 305 is formed on the entire surface of the polysilicon film 304, that is, on the upper surface and the side surface by thermal oxidation.

Next, using the polysilicon film 304 and the silicon oxide film 305 as masks, P ⁺ ions of 3
Ions are implanted into the Si substrate 301 with an acceleration energy of 0 keV and a dose amount of 2 × 10 ¹³ cm ⁻² to form an N ⁻ diffusion layer 306 as an LDD layer.

(2) Next, as shown in FIG.
Si substrate 301 with 20 nm silicon nitride film by CVD method
The silicon nitride film is deposited on the entire upper surface, and the entire surface of the silicon nitride film is etched back until the surface of the N ⁻ diffusion layer 306 is completely exposed.
Are formed on the side surfaces of the polysilicon film 304.

(3) Next, as shown in FIG.
The silicon oxide film 3 formed on the side surface of the polysilicon film 304 by immersing the i-substrate 301 in a dilute hydrofluoric acid solution
The upper part of 05 is removed to expose both ends of the upper part of the polysilicon film 304.

Silicon oxide film 30 formed by dilute hydrofluoric acid solution
Since the etching rate of No. 5 is about 10 times faster than that of the sidewall (silicon nitride film) 307, the upper portion of the silicon oxide film 305 can be selectively removed as described above. If the upper part of the silicon oxide film 305 is to be removed by 300 Å, a 5% HF solution may be subjected to wet etching for about 1 minute.

(4) Then, as shown in FIG.
As ⁺ ions with an acceleration energy of 50 keV and 3 ×
Polysilicon film 304 and Si at a dose of 10 ¹⁵ cm ^-2
Ion implantation is performed on the substrate 301, and 1050 is performed in a nitrogen atmosphere.
The gate polysilicon film 308 and the source / drain diffusion layer (N ⁺ diffusion layer) are subjected to high-speed annealing at 10 ° C. for 10 seconds.
309 is formed.

(5) Next, as shown in FIG.
A 0 nm Ti film is deposited on the entire surface of the Si substrate 301. Then, high-speed annealing is performed at 600 ° C. for 30 seconds in a nitrogen atmosphere, and the upper surface of the gate polysilicon film 308 exposed from the silicon oxide film 305 and the sidewall (silicon nitride film) 307 and the surface of the N ⁺ diffusion layer 309 are exposed. Is reacted with the Ti film to form a TiSi ₂ film.

(6) After that, the Ti film remaining unreacted on the field oxide film 302 and the side wall (silicon nitride film) 307 is selectively removed with ammonia hydrogen peroxide, and again in nitrogen at 800 ° C. A high-speed anneal for 30 seconds is performed, and the upper surface of the gate polysilicon film 308 and N
^A low resistance TiSi ₂ film 310 is formed on the surface of the ⁺ diffusion layer 309.

What is characteristic of the above steps of this embodiment is that both ends of the upper portion of the gate polysilicon film 308 are exposed without coming into contact with the sidewalls 307.
Therefore, the TiSi ₂ film 310 is not thinned at both ends above the gate polysilicon film 308, and the TiS ₂ film 310 is not thinned.
Since the i ₂ film 310 is uniformly formed, the resistance becomes low.

Further, since the groove is formed between the gate polysilicon film 308 and the sidewall 307, there is no fear of short circuit between the gate and the source / drain due to overgrowth of the silicide.

As described above, according to the fifth embodiment, it is possible to prevent the silicide from being thinned at both ends of the upper portion of the gate polysilicon film, so that the silicide having a uniform thickness and low resistance can be formed. Is possible.

Further, there is no fear of a short circuit between the gate and the source / drain due to the overgrowth of the silicide. Since no oxide film is deposited as a gate etching mask, the process is simplified.

In this embodiment, Ti silicide has been described as an example.
i-silicide may be used.

Next, a sixth embodiment of the present invention will be described.

FIG. 5 is a view for explaining a salicide process showing a sixth embodiment of the present invention, and is a process drawing schematically showing a sectional view.

(1) First, as shown in FIG. 5A, the LOC is formed on the Si (100) substrate 401 by using a known technique.
A 400 nm field oxide film 402 is formed by the OS method to partition the active region.

Next, the active region is thermally oxidized to 16n.
After forming the gate oxide film 403 of m, a polysilicon film of 300 nm is deposited and processed into a gate wiring pattern. Next, a 30 nm PSG film 405 is formed by the CVD method.
Are formed on the entire surface of the polysilicon film 404 to be the gate, that is, on the upper surface and side surfaces.

(2) Next, as shown in FIG. 5B, using the polysilicon film 404 and the PSG film 405 as a mask, the P ⁺ ions are accelerated with an energy of 30 keV and 2 × 10 ¹³ cm ^-2. Ions are implanted into the Si substrate 401 with a dose of 2 to form an N ⁻ diffusion layer 406 as an LDD layer. Next, a 220 nm NSG film is deposited on the entire surface of the Si substrate 401 by a CVD method, and the entire surface of the NSG film is etched back until the surface of the N ⁻ diffusion layer 406 is completely exposed. A wall 407 is formed on the side surface of the polysilicon film 404.

(3) Then, as shown in FIG.
By immersing the Si substrate 401 in a dilute hydrofluoric acid solution, the upper portion of the PSG film 405 formed on the side surface of the polysilicon film 404 is removed to expose both ends of the upper portion of the polysilicon film 404. Since the etching rate of the PSG film 405 with the diluted hydrofluoric acid solution is about 10 times faster than that of the sidewall 407 made of the NSG film, the PSG film 4 is not processed as described above.
The upper part of 05 can be selectively removed. If the upper part of the silicon film 405 is to be removed by 300Å, 1% H
The F solution may be subjected to wet etching for about 10 seconds.

(4) Then, as shown in FIG.
As ⁺ ions with an acceleration energy of 50 keV and 3 ×
With a dose amount of 10 ¹⁵ cm ^-2, the polysilicon film 404 and S
Ion implantation is performed on the i substrate 401, and 1050 is performed in a nitrogen atmosphere.
High-speed annealing at 10 ° C. for 10 seconds is performed to form gate polysilicon film 408, source / drain diffusion layer (N ⁺ diffusion layer)
409 is formed.

(5) Next, as shown in FIG.
A 0 nm Ti film is deposited on the entire surface of the Si substrate 401. Then, high-speed annealing is performed at 600 ° C. for 30 seconds in a nitrogen atmosphere, and the upper surface of the gate polysilicon film 408 and the surface of the source / drain diffusion layer 409 exposed from the sidewalls 407 made of the silicon oxide film 405 and the NSG film. Is reacted with the Ti film to form a TiSi ₂ film.

(6) After that, the Ti film remaining unreacted on the side wall 407 made of the field oxide film 402 and the NSG film is selectively removed with ammonia hydrogen peroxide, and again in nitrogen at 800 ° C. and 30 ° C. High-speed annealing is performed for a _second to form a low resistance TiSi ₂ film 410 on the upper surface of the gate polysilicon film 408 and the surface of the source / drain diffusion layer 409.

What is characteristic of the above-mentioned process of the sixth embodiment is that both ends of the upper portion of the gate polysilicon film 408 are exposed without coming into contact with the sidewalls 407.
As a result, the TiSi ₂ film 410 is not thinned at both ends above the gate polysilicon film 408.
_{Since the two} films 410 are uniformly formed, the resistance becomes low.

Further, since the groove is formed between the gate polysilicon film 408 and the sidewall 407, there is no fear of short circuit between the gate and the source / drain due to the overgrowth of the silicide.

As described above, according to the sixth embodiment, since the thinning of the silicide is prevented at both ends of the upper portion of the gate polysilicon film, the film thickness becomes uniform and the low resistance silicide can be formed. It will be possible.

Further, there is no fear of a short circuit between the gate and the source / drain due to the overgrowth of the silicide.

Further, since the oxide film as the gate etching mask is not deposited, the process is simplified.

Further, by using the NSG film as the sidewall, unlike the nitride film, there is no fear of fluctuation of the threshold voltage due to diffusion of hydrogen.

According to the above-described embodiment, Ti silicide has been described as an example.
i-silicide may be used.

The present invention is not limited to the above embodiments, and various modifications can be made based on the spirit of the present invention, and these modifications are not excluded from the scope of the present invention.

[0098]

As described in detail above, according to the present invention, the following effects can be obtained.

(A) Since it is possible to prevent the thinning of the silicide at both ends of the upper portion of the gate polysilicon film, the film thickness becomes uniform, and it is possible to form the silicide having a low resistance.

(B) There is no fear of a short circuit between the gate and the source / drain due to the overgrowth of the silicide.

(C) When collimated sputtering or long throw sputtering is used for forming the Ti film, the step coverage is improved.

[Brief description of drawings]

FIG. 1 is a diagram for explaining a salicide process showing a first embodiment of the present invention.

FIG. 2 is a diagram for explaining a process of forming a silicide film in a gate polysilicon portion showing a second embodiment of the present invention.

FIG. 3 is a diagram for explaining a salicide process showing a fourth embodiment of the present invention.

FIG. 4 is a diagram for explaining a salicide process showing a fifth embodiment of the present invention.

FIG. 5 is a diagram for explaining a salicide process showing a sixth embodiment of the present invention.

FIG. 6 is a cross-sectional view of a manufacturing process of a conventional semiconductor device.

[Explanation of symbols]

101, 201, 301, 401 Si (100) substrate 102, 202, 302, 402 Field oxide film 103, 203, 303, 403 Gate oxide film 104, 204, 304, 404 Polysilicon film 105, 205, 405 PSG film 106 , 206, 305 Silicon oxide films 107, 207, 306, 406 N ^- diffusion layers 108, 208, 307, 407 Side walls 109, 209, 308, 408 Gate polysilicon films 110, 210, 309, 409 Source / drain diffusion layers (N ⁺ diffusion layer) 111, 211, 310, 410 TiSi ₂ film (silicide film)

Claims (8)

(57) [Claims] 1. A step of: (a) etching the gate polysilicon film using the first insulating film as a mask; and (b) thermally oxidizing the side surfaces of the gate polysilicon film.
Forming a second insulating film formed, (c) forming a sidewall by a third insulating film deposited by CVD, (d) all of the first insulating layer of the mask And wet the upper part of the second insulating film on the side surface of the gate polysilicon film.
A step of selectively removing by etching, and (e) heat treatment after depositing the metal film,
A method of manufacturing a semiconductor device, comprising: forming a silicide on a surface of a gate polysilicon film and a surface of a source / drain diffusion layer. 2. The method for manufacturing a semiconductor device according to claim 1 , wherein the first insulating film and the second insulating film are silicon oxide films, and the third insulating film is a silicon nitride film. And a method for manufacturing a semiconductor device. 3. The method of manufacturing a semiconductor device according to claim 1 , wherein the first insulating film is a PSG film, a BSG film or B.
A method of manufacturing a semiconductor device, wherein a PSG film, the second insulating film is a thermal oxide film, and the third insulating film is an NSG film. 4. A method of manufacturing a semiconductor device, comprising: (a) etching a gate polysilicon film, and then forming a first insulating film formed by thermal oxidation on a side surface and an upper surface of the gate polysilicon film. , (B) a step of forming a sidewall by a second insulating film deposited by a CVD method, and (c) removing the first insulating film on the upper surface of the gate polysilicon film by wet etching when the sidewall is formed. Then , a step of leaving only the first insulating film on the side surface of the gate polysilicon film, and (d) a step of selectively removing the upper portion of the first insulating film on the side surface of the gate polysilicon film by wet etching, (E) A step of forming silicide on the surface of the gate polysilicon film and the surface of the source / drain diffusion layer by performing heat treatment after depositing the metal film. The method of manufacturing a semiconductor device characterized by subjecting. 5. The method of manufacturing a semiconductor device according to claim 4 , wherein the first insulating film is a silicon oxide film, and the second insulating film is a silicon oxide film.
The method of manufacturing a semiconductor device, wherein the insulating film is a silicon nitride film. 6. The method of manufacturing a semiconductor device according to claim 4 , wherein the first insulating film is a PSG film, a BSG film or B.
A method of manufacturing a semiconductor device, wherein the PSG film and the second insulating film are NSG films. 7. The method of claim 1 or 4 The method for manufacturing a semiconductor device according to the metal deposition, a method of manufacturing a semiconductor device, which comprises using a straight highly sputtering of the metal particles. 8. The method of manufacturing a semiconductor device according to claim 7 , wherein a collimated sputtering or a long throw sputtering method is used as the sputtering method having high straightness.