JP2000150679A - Semiconductor memory and fabrication thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase capacity between a floating gate electrode and a control gate electrode without lowering the reliability between them or increasing the memory size by making a trench in the floating gate electrode extending in the breadthwise direction thereof. SOLUTION: Since a trench 4a having recessed cross-section in the longitudinal direction of the gate is made on a floating gate electrode 4 in a semiconductor memory, surface area can be increased between the floating gate electrode 4 and a control gate electrode 6. Consequently, capacity between the floating gate electrode 4 and the control gate electrode 6 can be increased without making thin a second gate insulating film 5 or increasing overlap between the floating gate electrode 4 and a field oxide film 2 as required in prior art, and the reliability of gate insulating films 3, 5 can be ensured while reducing cell size.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device having a floating gate structure and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a nonvolatile semiconductor memory device having a floating gate structure is usually manufactured as follows.

That is, first, after forming a thick field oxide film on a semiconductor substrate, a channel region is formed, and a first gate insulating film (silicon film) is formed on the channel region.
Is formed, a first conductor layer serving as a floating gate electrode is formed on the first gate insulating film, and the first conductor layer on the field oxide film is etched using the resist pattern as a mask,
The length of the floating gate electrode in the gate width direction, usually the length in the direction perpendicular to the channel direction, is determined.
A gate insulating film is formed, and a second conductor layer serving as a control gate electrode is formed on the second gate insulating film.

In the multilayer electrode structure formed as described above, generally, the larger the coupling capacitance between the floating gate electrode and the control gate electrode, the more advantageous for the nonvolatile memory characteristics. It is required to increase the capacity.

[0005]

In the structure and manufacturing method of the conventional semiconductor memory device, in order to increase the capacitance, the thickness of the insulating film between the floating gate electrode and the control gate electrode must be reduced or the floating gate electrode must be thinned. It is necessary to increase the overlap between the gate electrode and the field oxide film to increase the area of the floating gate electrode. However, when the thickness of the insulating film between the floating gate electrode and the control gate electrode is reduced, reliability such as the withstand voltage of the insulating film is reduced, and increasing the overlap between the floating gate electrode and the field oxide film increases the memory cell size. There was a problem that would be.

The present invention solves the above-mentioned problem of the prior art. In a floating gate electrode type nonvolatile semiconductor memory device having a multi-layered electrode structure, an insulating film is formed between the electrodes. A semiconductor memory device capable of increasing the capacitance between the floating gate electrode and the control gate electrode without reducing the reliability of the insulating film between the floating gate electrode and the control gate electrode, or increasing the memory cell size; And a method for producing the same.

[0007]

In order to solve the above-mentioned problems, a semiconductor memory device according to the present invention comprises a semiconductor having a multilayer electrode structure including a floating gate electrode and a control gate electrode provided for the floating gate electrode. In the storage device, a groove extending in a width direction of the floating gate is formed in the floating gate electrode.

Further, in the method of manufacturing a semiconductor memory device according to the present invention, a step of forming an insulating film on a semiconductor substrate; a step of selectively removing the insulating film to form an opening; Forming a first gate insulating film on the surface of the substrate; forming a first conductor layer serving as a floating gate electrode on the first gate insulating film and on the insulating film; and forming a groove in the first conductor layer And forming a second gate insulating film on the first conductive layer, and forming a second conductive layer serving as a control gate electrode on the second gate insulating film.

According to the semiconductor memory device and the manufacturing method of the present invention, the surface area between the floating gate electrode and the control gate electrode can be increased by forming the groove in the gate width direction of the floating gate electrode. The capacitance between the floating gate electrode and the control gate electrode can be increased without reducing the thickness of the second gate insulating film or increasing the overlap between the floating gate electrode and the field oxide film as in the prior art. It is possible to easily secure the reliability of the insulating film and reduce the cell size.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view in the longitudinal direction of a gate in a memory cell of a nonvolatile semiconductor memory device for explaining an embodiment of the present invention, and FIG. 2 is a plan view showing a main part in the memory cell of the embodiment. is there.

1 and 2, reference numeral 1 denotes a silicon substrate;
2 is a field oxide film, 3 is a first gate insulating film, 4 is a floating gate electrode made of polysilicon, 5 is a second gate insulating film, 6 is a control gate electrode made of polysilicon,
7 is an interlayer insulating film, 8 is a source region, 9 is a drain region,
Reference numeral 10 denotes an aluminum wiring.

In the present semiconductor memory device, unlike the conventional device, the trench 4a is formed on the floating gate electrode 4 so that the sectional shape of the floating gate electrode 4 in the longitudinal direction of the gate is concave. The structure has a large surface area between the electrode 4 and the control gate electrode 6.

Next, a method of manufacturing the semiconductor memory device according to the present embodiment will be described. FIGS. 3 to 7 are explanatory diagrams of main steps showing an example of a method for manufacturing the semiconductor memory device shown in FIGS.

First, as shown in FIG.
A field oxide film 2 is formed on the substrate. Next, an insulating film 11 is formed by a CVD method, and a resist film 12 having an opening pattern is formed on the insulating film 11.

Next, as shown in FIG. 4, the insulating film 11 is selectively removed using the pattern of the resist film 12 as a mask to expose the surface of the semiconductor substrate 1 and to form a region for forming a floating gate electrode. The resist film 12 is removed to form the opening A.

Next, as shown in FIG. 5, a first gate insulating film 3 is formed in the portion of the opening A, and a first gate insulating film 3 serving as a floating gate electrode is formed.
A silicon film (first conductor layer) 4 is grown by a CVD method. The first silicon film 4 may be polycrystalline or amorphous. At this time, a fine groove 4a long in the gate width direction of the first silicon film 4 is formed in a self-aligned manner due to the step of the insulating film 11 in the opening A portion. That is, in the first silicon film 4 in the portion of the opening A, a groove 4a as small as about 1/2 of the film thickness is formed.

Next, the first silicon film 4 on the field oxide film 2 is etched using a resist pattern (not shown) as a mask to determine the length of the first silicon film 4 in the gate width direction. Silicon oxide-silicon nitride-
A second gate insulating film 5 such as a silicon oxide composite film (ONO film) is formed, and a second silicon film (second conductor layer) 6 serving as a control gate electrode is formed on the second gate insulating film 5.
The second silicon film 6 may be polycrystalline or amorphous similarly to the first silicon film 4.

Next, as shown in FIG. 6, a resist 13 is formed on the second silicon film 6 at a position overlapping the opening A of the insulating film 11, and using the resist 13 as a mask, a resist 13 is formed. The 2 gate insulating film 5, the first silicon film 4, and the insulating film 11 are sequentially anisotropically dry-etched in a self-aligned manner to form a memory cell gate electrode as shown in FIG.

Since the subsequent steps are known, detailed description is omitted, but the source region 8 and the drain region 9 are formed by ion-implanting arsenic using the gate electrodes 4 and 6 as a mask, as in the prior art. I do. Thereafter, an interlayer insulating film is formed on the gate electrodes 4 and 6, a contact hole is formed in the interlayer insulating film, and an aluminum wiring, passivation and the like are formed thereon to complete the nonvolatile semiconductor memory device.

As described above, in the semiconductor memory device of the present embodiment, since the floating gate electrode 4 has the narrow recess (groove) 4a extending in the channel width direction of the memory transistor, the control gate electrode 6 And the coupling capacity between them can be increased. The size of the capacitance can be adjusted by adjusting the area of the floating gate electrode 4 by adjusting the depth of the groove 4a. This corresponds to adjusting the depth of the opening A in the insulating film 11 of FIG. 4 in terms of the manufacturing method.

A plurality of grooves 4a of the floating gate electrode 4 can be formed in the channel length direction. But groove 4a
Is not only complicated in the formation process, but also the gate surface area does not increase so much as compared with the case of providing in the channel width direction.

Since the floating gate electrode 4 is a part of the memory transistor, its gate length is close to the dimension of the design rule (rule), that is, close to the minimum dimension that can be formed by photolithography. design.
Therefore, the width of the groove 4a is a fine width equal to or less than the limit of the photolithography (less than the minimum dimension in the design rule).

In the manufacturing method of this embodiment, the floating gate electrode 4 is formed by utilizing the step of the opening A of the insulating film 11 shown in FIG.
There is an advantage that the groove 4a can be easily formed in a self-aligned manner substantially at the center of the groove 4a.

[0025]

As described above, according to the semiconductor memory device structure and the method of manufacturing the same of the present invention, the capacitance increases due to the increase in the surface area between the floating gate electrode and the control gate electrode. It is not necessary to reduce the thickness of the insulating film between the floating gate electrode and the control gate electrode and increase the overlap between the floating gate electrode and the field oxide film to increase the reliability. This is effective for reducing the memory cell size.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a memory cell of a nonvolatile semiconductor memory device in a gate longitudinal direction for describing one embodiment of the present invention;

FIG. 2 is a plan view showing a main part of the memory cell according to the embodiment;

FIG. 3 is an explanatory view of a first step in a method for manufacturing the semiconductor memory device shown in FIGS. 1 and 2;

FIG. 4 is an explanatory view of a second step in the method for manufacturing the semiconductor memory device shown in FIGS. 1 and 2;

FIG. 5 is an explanatory view of a third step in the method for manufacturing the semiconductor memory device shown in FIGS. 1 and 2;

FIG. 6 is an explanatory view of a fourth step in the method for manufacturing the semiconductor memory device shown in FIGS. 1 and 2;

FIG. 7 is an explanatory view of a fifth step in the method for manufacturing the semiconductor memory device shown in FIGS. 1 and 2;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 silicon substrate 2 field oxide film 3 first gate insulating film 4 floating gate electrode 4a made of first silicon film 4a groove of floating gate electrode 5 second gate insulating film 6 control gate electrode made of second silicon film 7 interlayer insulating film 8 Source region 9 drain region 10 aluminum wiring 11 insulating film 12 resist film 13 resist A opening

Claims (6)

[Claims] In a semiconductor memory device having a multi-layer electrode structure including a floating gate electrode and a control gate electrode provided for the floating gate electrode, a groove extending in a width direction of the floating gate is formed in the floating gate electrode. A semiconductor memory device characterized by being formed. 2. The semiconductor memory device according to claim 1, wherein the width of said groove is substantially the minimum dimension specified by design. 3. The semiconductor memory device according to claim 1, wherein said groove is formed substantially at the center of said floating gate electrode. 4. The floating gate electrode according to claim 1, wherein at least one groove is formed in said floating gate electrode.
13. The semiconductor memory device according to claim 1. 5. A method for manufacturing a semiconductor memory device according to claim 1, wherein: a step of forming an insulating film on the semiconductor substrate; and a step of selectively removing the insulating film to form an opening. Forming a first gate insulating film on the surface of the semiconductor substrate in the opening, forming a first conductor layer serving as a floating gate electrode on the first gate insulating film and on the insulating film; Forming a groove in one conductive layer, forming a second gate insulating film on the first conductive layer, and forming a second conductive layer serving as a control gate electrode on the second gate insulating film And a method for manufacturing a semiconductor memory device. 6. In the step of forming a first conductive layer to be a floating gate electrode on the first gate insulating film and on the insulating film, a groove is formed in the first conductive layer in the opening in a self-aligned manner. 6. The method according to claim 5, wherein the method is performed.