JP2000138259A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JP2000138259A
JP2000138259A JP30880698A JP30880698A JP2000138259A JP 2000138259 A JP2000138259 A JP 2000138259A JP 30880698 A JP30880698 A JP 30880698A JP 30880698 A JP30880698 A JP 30880698A JP 2000138259 A JP2000138259 A JP 2000138259A
Authority
JP
Japan
Prior art keywords
wiring board
semiconductor chip
electrodes
semiconductor device
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP30880698A
Other languages
Japanese (ja)
Inventor
Shoji Miyagawa
尚司 宮川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP30880698A priority Critical patent/JP2000138259A/en
Publication of JP2000138259A publication Critical patent/JP2000138259A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of positioning by recognizing collectively the electrodes of a semiconductor chip and electrodes of a wiring board by an image recognizing means at the time of assembling a semiconductor device, wherein the semiconductor chip is mounted on the wiring board and the electrodes of them are connected with each other. SOLUTION: A wiring board 11, on which a semiconductor chip 10 is mounted, is composed of transparent or semitransparent mica. Electrodes 12 of the semiconductor chip 10 and electrodes 13 of the wiring board 11 are recognized collectively by an image recognizing camera 17 which is arranged on the side opposite with respect to the semiconductor chip 10, interposing the wiring board 11. Positions of the semiconductor chip 10 and the wiring board 11 are adjusted on the bais of the image recognization, and assembling is performed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体装置およびそ
の製造方法に係り、とくに半導体チップを絶縁材料から
成る配線板上にマウントして成る半導体装置およびその
製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a semiconductor chip mounted on a wiring board made of an insulating material and a method of manufacturing the same.

【0002】[0002]

【従来の技術】チップサイズパッケージ(CPS)やボ
ールグリッドアレー(BGA)等から成る半導体パッケ
ージ構造の半導体装置が広く用いられるようになってい
る。このような半導体装置において、半導体チップをフ
ェイスダウンさせて配線板上にマウントするフリップチ
ップ方式による半導体パッケージ構造の製造の際には、
半導体チップの電極と配線板の電極との位置合わせを行
なうようにしている。すなわち画像認識カメラ等により
それぞれの電極の位置を個別に認識し、双方の認識デー
タを組合わせて位置調整を行なうようにしていた。
2. Description of the Related Art Semiconductor devices having a semiconductor package structure including a chip size package (CPS) and a ball grid array (BGA) have been widely used. In such a semiconductor device, when manufacturing a semiconductor package structure by a flip chip method in which a semiconductor chip is face down and mounted on a wiring board,
The alignment of the electrodes of the semiconductor chip and the electrodes of the wiring board is performed. That is, the position of each electrode is individually recognized by an image recognition camera or the like, and the position adjustment is performed by combining the two recognition data.

【0003】これを図5によって説明すると、半導体チ
ップ1と配線板2とによって半導体装置が組立てられる
ようになっている。ここで半導体チップ1には予め電極
5が形成されている。また配線板2は例えばガラスエポ
キシ基板、セラミック基板等の絶縁材料から成る配線板
であって、その上には配線と電極6とがそれぞれ形成さ
れている。
[0005] Referring to FIG. 5, a semiconductor device can be assembled with a semiconductor chip 1 and a wiring board 2. Here, the electrodes 5 are formed on the semiconductor chip 1 in advance. The wiring board 2 is a wiring board made of an insulating material such as a glass epoxy board and a ceramic board, on which wirings and electrodes 6 are respectively formed.

【0004】半導体チップ1と配線板2とを互いに位置
合わせする場合には、図5に示すようにこれらの半導体
チップ1の電極5が形成されている表面と配線板2の電
極6が形成されている面とを向い合わせ、それらの間に
画像認識カメラ3を挿入し、この画像認識カメラ3によ
って上方の半導体チップ1の電極5および下方の配線板
2の電極6をそれぞれ画像認識し、双方の画像データを
組合わせ、必要に応じて半導体チップ1または配線板2
の位置を移動させて位置調整を行なうようにしている。
なお他の方式においても、それぞれ半導体チップ1と配
線板2の電極5、6を画像認識し、双方の認識データを
組合わせて位置合わせを行ない、このような状態で電極
5、6の接続を行なうようにしている。
When the semiconductor chip 1 and the wiring board 2 are aligned with each other, the surface of the semiconductor chip 1 on which the electrodes 5 are formed and the electrodes 6 of the wiring board 2 are formed as shown in FIG. The image recognition camera 3 is inserted between them, and the image recognition camera 3 recognizes the image of the electrode 5 of the upper semiconductor chip 1 and the electrode 6 of the lower wiring board 2 respectively. Of the semiconductor chip 1 or the wiring board 2 if necessary.
Is moved to adjust the position.
In other methods, the electrodes 5 and 6 of the semiconductor chip 1 and the wiring board 2 are image-recognized, and the positions of the electrodes 5 and 6 are aligned by combining the two recognition data. I do it.

【0005】[0005]

【発明が解決しようとする課題】図5に示すように、半
導体チップ1と配線板2との間に挿入された画像認識カ
メラ3によって半導体チップ1と配線板2の画像認識を
行なうようにした位置決めによれば、認識データの組合
わせを非常に精度よく調整する必要があり、また個別に
認識を行なうことで認識カメラ部が複数個必要になり、
複雑な構造になってしまう問題がある。
As shown in FIG. 5, image recognition of the semiconductor chip 1 and the wiring board 2 is performed by an image recognition camera 3 inserted between the semiconductor chip 1 and the wiring board 2. According to the positioning, it is necessary to adjust the combination of the recognition data very accurately, and by performing individual recognition, a plurality of recognition camera units are required,
There is a problem that the structure becomes complicated.

【0006】また半導体チップ1と配線板2とを互いに
結合した後における半導体チップ1の電極5と配線板2
の電極6の位置ずれや接続不良等の接続状態の確認は、
電極5、6が内部へ隠れてしまうために直接確認を行な
うことができない。このためにX線透過による解析や、
破壊による解析を行なうしかなく、実際に使用される半
導体装置をそのままの状態で簡便にかつ正確に確認を行
なうことができないという問題があった。
Further, after the semiconductor chip 1 and the wiring board 2 are connected to each other, the electrode 5 of the semiconductor chip 1 and the wiring board 2
Confirmation of the connection state such as the displacement of the electrode 6 and the connection failure
Since the electrodes 5 and 6 are hidden inside, direct confirmation cannot be performed. For this reason, analysis by X-ray transmission,
There has been a problem that analysis by destruction has to be performed, and it is not possible to simply and accurately confirm a semiconductor device actually used as it is.

【0007】本発明はこのような問題点に鑑みてなされ
たものであって、半導体チップと配線板との間に画像認
識カメラを挿入することなくしかも両者の画像認識を行
なうことができ、また組立てた後においても、半導体チ
ップと配線板の相互の位置ずれ等の電極接続部の不良の
確認が容易に行ない得るようにした半導体装置およびそ
の製造方法を提供することを目的とする。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and it is possible to perform image recognition between a semiconductor chip and a wiring board without inserting an image recognition camera between the two. It is an object of the present invention to provide a semiconductor device and a method of manufacturing the same, which can easily confirm a defect of an electrode connection portion such as a mutual displacement between a semiconductor chip and a wiring board even after assembly.

【0008】[0008]

【課題を解決するための手段】半導体装置に関する発明
は、半導体チップを絶縁材料から成る配線板上にマウン
トして成る半導体装置において、前記配線板が透明また
は半透明であることを特徴とする半導体装置に関するも
のである。ここで前記配線板が透明または半透明のマイ
カから成るものであってよい。また前記半導体チップの
電極と前記配線板の電極とが互いに接続されていてよ
い。
According to the present invention, there is provided a semiconductor device comprising a semiconductor chip mounted on a wiring board made of an insulating material, wherein the wiring board is transparent or translucent. It concerns the device. Here, the wiring board may be made of transparent or translucent mica. Further, the electrode of the semiconductor chip and the electrode of the wiring board may be connected to each other.

【0009】製造方法に関する発明は、半導体チップを
絶縁材料から成る配線板上にマウントして前記半導体チ
ップの電極と前記配線板上の電極とを互いに接続するよ
うにした半導体装置の製造方法において、前記配線板を
透明または半透明な材料によって製作するとともに、前
記配線板に対して前記半導体チップとは反対側から画像
認識手段を用いて前記半導体チップの電極と前記配線板
の電極とを画像認識し、該画像認識に基いて前記半導体
チップと前記配線板の相互の位置ずれを補正することを
特徴とする半導体装置の製造方法に関するものである。
The present invention relates to a method of manufacturing a semiconductor device, wherein a semiconductor chip is mounted on a wiring board made of an insulating material and an electrode of the semiconductor chip is connected to an electrode on the wiring board. The wiring board is made of a transparent or translucent material, and the electrodes of the semiconductor chip and the electrodes of the wiring board are image-recognized using image recognition means from the side opposite to the semiconductor chip with respect to the wiring board. The present invention also relates to a method for manufacturing a semiconductor device, comprising correcting a mutual displacement between the semiconductor chip and the wiring board based on the image recognition.

【0010】本発明の好ましい態様は、チップサイズパ
ッケージ、ボールグリッドアレー等のパッケージ構造の
半導体装置の配線板として、外観が透明もしくは半透明
のマイカ等の基板を使用した半導体装置に関するもので
ある。このような半導体装置によれば、半導体チップを
配線板上にマウントして双方の電極同士の位置合わせを
行なう際に、配線板の電極と半導体チップの電極とを配
線板に対して半導体チップとは反対側に位置する画像認
識カメラによって同時に認識することができ、位置合わ
せを容易にすることが可能になる。またこのことから、
半導体搭載装置における認識カメラの簡素化が図られる
ことになる。また半導体チップを配線板上にマウントし
て組立てた後に、半導体チップの搭載位置のずれ等に基
く電極部の接続の不良の確認を外部から容易に行なうこ
とが可能になる。
A preferred embodiment of the present invention relates to a semiconductor device using a transparent or translucent substrate such as mica as a wiring board of a semiconductor device having a package structure such as a chip size package and a ball grid array. According to such a semiconductor device, when the semiconductor chip is mounted on the wiring board and the two electrodes are aligned, the electrode of the wiring board and the electrode of the semiconductor chip are connected to the semiconductor chip with respect to the wiring board. Can be simultaneously recognized by the image recognition camera located on the opposite side, and alignment can be facilitated. Also from this,
The recognition camera in the semiconductor mounting device can be simplified. Further, after mounting the semiconductor chip on the wiring board and assembling it, it is possible to easily check the connection failure of the electrode portion based on the shift of the mounting position of the semiconductor chip from the outside.

【0011】またこのような半導体パッケージ構造を利
用して、半導体チップをパッケージにすることなく直接
回路基板へ搭載するベアチップ実装方式への応用が可能
になる。また配線板に受動素子を1個あるいは2個以上
内蔵したマイカ基板を用いた半導体装置とすることが可
能である。
By utilizing such a semiconductor package structure, application to a bare chip mounting method in which a semiconductor chip is directly mounted on a circuit board without forming a package becomes possible. Further, a semiconductor device using a mica substrate in which one or two or more passive elements are incorporated in a wiring board can be provided.

【0012】このような発明の態様によれば、とくに半
導体チップを配線板上にマウントして製造する際に、配
線板の電極と半導体チップの電極とを同時に画像認識す
ることができるために、位置合わせを容易に行なうこと
が可能になる。そしてこのことから、半導体チップの搭
載装置における位置合わせのためのカメラ部の簡素化が
図られるようになる。また半導体チップを配線板に搭載
した後に、搭載位置ずれ等の電極部接続良否確認が容易
に行ない得るようになる。
According to this aspect of the invention, particularly when the semiconductor chip is mounted on the wiring board and manufactured, the electrodes of the wiring board and the electrodes of the semiconductor chip can be simultaneously image-recognized. Positioning can be easily performed. This simplifies the camera section for alignment in the semiconductor chip mounting device. Further, after the semiconductor chip is mounted on the wiring board, it is possible to easily confirm whether or not the electrode portion is connected properly, such as a mounting position shift.

【0013】配線板に用いられるマイカ材は従来より一
般的に用いられているガラスエポキシ等の有機基板より
も耐熱温度が高いことから、製造上の制約が減少して容
易に作製または使用することができる。またマイカ材は
表面の平坦性に優れることから、半導体チップとの安定
な接続が可能になる。さらにマイカ材は、熱膨張係数が
半導体チップとほぼ同程度で非常に小さいことにより、
温度変化において半導体チップとの膨張差が少なく、接
続部の寿命に対して有利に作用する。
Since the mica material used for a wiring board has a higher heat resistance temperature than an organic substrate such as glass epoxy which has been generally used in the past, it is easy to manufacture or use the material because of reduced manufacturing restrictions. Can be. In addition, since the mica material has excellent surface flatness, stable connection with a semiconductor chip can be achieved. Furthermore, the mica material has a very small thermal expansion coefficient, almost the same as a semiconductor chip,
The difference in expansion between the semiconductor chip and the semiconductor chip due to temperature change is small, and this has an advantageous effect on the life of the connection portion.

【0014】また配線板として軽量なマイカを用いるこ
とによって、半導体装置および電子回路全体の軽量化が
図られることになる。さらに配線板に安価なマイカ材を
使用することによって、半導体装置の低コスト化が図ら
れる。
By using a lightweight mica as the wiring board, the weight of the semiconductor device and the entire electronic circuit can be reduced. Further, by using an inexpensive mica material for the wiring board, the cost of the semiconductor device can be reduced.

【0015】[0015]

【発明の実施の形態】図1は本発明の一実施の形態に係
る半導体装置の製造に用いられる半導体チップを示して
いる。半導体チップ10の表面には、各端子を構成する
電極5が形成されている。
FIG. 1 shows a semiconductor chip used for manufacturing a semiconductor device according to an embodiment of the present invention. Electrodes 5 constituting each terminal are formed on the surface of the semiconductor chip 10.

【0016】図2はこのような半導体チップ10と組合
わされる配線板11を示している。配線板11はマイカ
(雲母)から構成される基板であって、その表面には導
電性材料によって配線が施されるとともに、上記半導体
チップ10の電極12と対応するように電極13が形成
されている。
FIG. 2 shows a wiring board 11 combined with such a semiconductor chip 10. The wiring board 11 is a substrate made of mica (mica). The surface of the wiring board 11 is provided with wiring by a conductive material, and the electrodes 13 are formed so as to correspond to the electrodes 12 of the semiconductor chip 10. I have.

【0017】ここで半導体チップ10を上下反転(フェ
イスダウン)させ、図4に示すようにその電極12と配
線板11の電極13との位置合わせをし、半導体チップ
10を配線板11上へ搭載する。半導体装置は半導体チ
ップ10と配線板11とによって構成された半導体パッ
ケージであって、必要に応じて半導体チップ10の電極
12と配線板11の電極13とを導電性接着剤等で接続
し、あるいはまた封止樹脂等によって補強を行なうよう
にしている。なお配線板11の下面に形成された電極2
0が半導体パッケージの電極となり、このような電極が
回路基板の接続用ランドに接続されるようになってい
る。
Here, the semiconductor chip 10 is turned upside down (face down), the electrodes 12 and the electrodes 13 of the wiring board 11 are aligned as shown in FIG. 4, and the semiconductor chip 10 is mounted on the wiring board 11. I do. The semiconductor device is a semiconductor package composed of a semiconductor chip 10 and a wiring board 11, and the electrodes 12 of the semiconductor chip 10 and the electrodes 13 of the wiring board 11 are connected with a conductive adhesive or the like as necessary, or Further, reinforcement is performed by a sealing resin or the like. The electrode 2 formed on the lower surface of the wiring board 11
0 is an electrode of the semiconductor package, and such an electrode is connected to the connection land of the circuit board.

【0018】本実施の形態の半導体装置の特徴は、配線
板11にマイカ(雲母)基板を使用した構造を有するこ
とである。板状のマイカへ銀導体等でパターン配線をし
て回路板として使用する。必要に応じて積層して多層配
線基板としてもよい。配線板11の回路板としての構造
は従来からの回路板と同様の構造である。マイカの外観
は透明もしくは半透明であることを利用し、配線板11
をマイカ基板によって構成することによって、半導体チ
ップ10の電極12と配線板11の電極13との位置合
わせが容易になるとともに、搭載後の接続部の良否確認
も容易になる利点をもたらす。
A feature of the semiconductor device of the present embodiment is that it has a structure using a mica (mica) substrate for the wiring board 11. It is used as a circuit board by performing pattern wiring on a plate-like mica with a silver conductor or the like. It may be laminated as necessary to form a multilayer wiring board. The structure of the wiring board 11 as a circuit board is the same as a conventional circuit board. Making use of the fact that the appearance of mica is transparent or translucent,
Is composed of a mica substrate, whereby the alignment between the electrode 12 of the semiconductor chip 10 and the electrode 13 of the wiring board 11 is facilitated, and the quality of the connection portion after mounting is easily checked.

【0019】図3は半導体チップ10と配線板11との
位置合わせの構成の1例を示している。そしてここで配
線板11としてマイカ基板が用いられている。
FIG. 3 shows an example of a configuration for positioning the semiconductor chip 10 and the wiring board 11. Here, a mica substrate is used as the wiring board 11.

【0020】マイカ基板を配線板11に使用した際に
は、図3に示すように半導体チップ10の電極12が形
成されている面と配線板11の電極13が形成されてい
る面とを互いに向い合わせ、配線板11に対して半導体
チップ10とは反対側であって下側の位置に画像認識カ
メラ17を設置する。
When the mica substrate is used for the wiring board 11, the surface of the semiconductor chip 10 on which the electrodes 12 are formed and the surface of the wiring board 11 on which the electrodes 13 are formed, as shown in FIG. The image recognition camera 17 is installed at a position opposite to and below the semiconductor chip 10 with respect to the wiring board 11.

【0021】このような配置によれば、画像認識カメラ
17によって透明な配線板11を介してその上の電極1
3を画像認識することができるばかりでなく、透明な配
線板11を介して半導体チップ10の電極12を画像認
識することができる。すなわち画像認識カメラ17によ
って透明な配線板11を通してこの配線板11の電極1
3と半導体チップ10の電極12とを一括して認識する
ことができ、これによって容易に位置合わせを行なうこ
とができるとともに、厳密な調整が必要となる特別の認
識データの組合わせが不要になる利点をもたらす。
According to such an arrangement, the electrode 1 on the transparent wiring board 11 is interposed by the image recognition camera 17 via the transparent wiring board 11.
In addition to the image recognition of the electrode 3, the electrode 12 of the semiconductor chip 10 can be image-recognized via the transparent wiring board 11. That is, the electrode 1 of the wiring board 11 is passed through the transparent wiring board 11 by the image recognition camera 17.
3 and the electrodes 12 of the semiconductor chip 10 can be collectively recognized, whereby the alignment can be easily performed, and a combination of special recognition data requiring strict adjustment is not required. Bring benefits.

【0022】またこのような半導体チップ10と配線板
11との組合わせから成る半導体装置によれば、その組
立て後において半導体チップ10の電極部12と配線板
11の電極部13の位置ずれや接続不良等の接続良否確
認が、従来は直接的にはできず、X線透過による解析や
破壊検査によって行なうようにしていたが、本構造を採
用することによって、透明または半透明なマイカ基板1
1を通して接続部を直接観察することができ、容易に接
続良否確認を行なうことができる。
Further, according to the semiconductor device comprising such a combination of the semiconductor chip 10 and the wiring board 11, after the assembly, the position of the electrode portion 12 of the semiconductor chip 10 and the position of the electrode portion 13 of the wiring board 11 are shifted or connected. Conventionally, it is not possible to directly confirm the connection quality such as a defect by performing analysis or destructive inspection by X-ray transmission, but by adopting this structure, the transparent or translucent mica substrate 1
1, the connection portion can be directly observed, and the quality of the connection can be easily confirmed.

【0023】また配線板11を構成するマイカ基板に、
1個または2個以上の受動素子を内蔵することによっ
て、受動素子を内蔵した半導体装置を組立てることがで
き、半導体チップと受動素子との間の配線を短くして回
路電気特性を向上し、電子回路の軽薄短小化を達成でき
るようになる。
Further, the mica substrate constituting the wiring board 11
By incorporating one or more passive elements, it is possible to assemble a semiconductor device incorporating the passive elements, shorten the wiring between the semiconductor chip and the passive elements, improve the circuit electrical characteristics, and improve the electronic performance. This makes it possible to achieve a lighter and smaller circuit.

【0024】[0024]

【発明の効果】本願に含まれる一発明は、半導体チップ
を絶縁材料から成る配線板上にマウントして成る半導体
装置において、配線板が透明または半透明であることを
特徴とするものである。
According to one aspect of the present invention, there is provided a semiconductor device having a semiconductor chip mounted on a wiring board made of an insulating material, wherein the wiring board is transparent or translucent.

【0025】従ってこのような透明または半透明の配線
板を通して、半導体チップと配線板との接続部を配線板
に対して半導体チップとは反対側から光学的に認識する
ことが可能になり、このために組立ての際における画像
認識が容易に行なわれることになる。また組立てた後に
おいても、透明または半透明の配線板を通して接続部の
良否確認を容易に行なうことが可能になる。
Therefore, through such a transparent or translucent wiring board, the connection between the semiconductor chip and the wiring board can be optically recognized from the side opposite to the semiconductor chip with respect to the wiring board. Therefore, image recognition at the time of assembly can be easily performed. Further, even after assembly, it is possible to easily confirm the quality of the connection portion through the transparent or translucent wiring board.

【0026】配線板が透明または半透明のマイカから成
る構成によれば、このようなマイカから成る配線板によ
って、接続部を配線板を通して確認できるようになる。
According to the structure in which the wiring board is made of transparent or translucent mica, the connection portion can be confirmed through the wiring board by the wiring board made of such mica.

【0027】半導体チップの電極と配線板の電極とが互
いに接続されている構成によれば、このような半導体チ
ップの電極と配線板の電極とを透明または半透明の配線
板を通して位置合わせを行なうことができ、あるいはま
た組立てた後における接続の良否判断を行なうことが可
能になる。
According to the configuration in which the electrodes of the semiconductor chip and the electrodes of the wiring board are connected to each other, the electrodes of the semiconductor chip and the electrodes of the wiring board are aligned through a transparent or translucent wiring board. Alternatively, the quality of the connection after assembly can be determined.

【0028】製造方法に関する発明は、半導体チップを
絶縁材料から成る配線板上にマウントして半導体チップ
の電極と配線板上の電極とを互いに接続するようにした
半導体装置の製造方法において、配線板を透明または半
透明な材料によって製作するとともに、配線板に対して
半導体チップとは反対側から画像認識手段を用いて半導
体チップの電極と配線板の電極とを画像認識し、該画像
認識に基いて半導体チップと配線板の相互の位置ずれを
補正するようにしたものである。
The present invention relates to a method of manufacturing a semiconductor device, wherein a semiconductor chip is mounted on a wiring board made of an insulating material and electrodes of the semiconductor chip and electrodes on the wiring board are connected to each other. Is made of a transparent or translucent material, and the electrodes of the semiconductor chip and the electrodes of the wiring board are image-recognized using image recognition means from the side opposite to the semiconductor chip with respect to the wiring board. In addition, the mutual displacement between the semiconductor chip and the wiring board is corrected.

【0029】従ってこのような製造方法によれば、透明
または半透明な配線板に対して半導体チップとは反対側
に配された画像認識手段によって半導体チップの電極と
配線板の電極とを一括して画像認識し、このような画像
認識に基いて半導体チップと配線板の相互の位置ずれを
補正し、半導体チップの電極と配線板の電極とを正しく
接続することが可能になる。
Therefore, according to such a manufacturing method, the electrodes of the semiconductor chip and the electrodes of the wiring board are integrated by the image recognition means arranged on the side opposite to the semiconductor chip with respect to the transparent or translucent wiring board. The semiconductor chip and the wiring board are corrected for mutual positional deviation based on the image recognition, and the electrodes of the semiconductor chip and the electrodes of the wiring board can be correctly connected.

【図面の簡単な説明】[Brief description of the drawings]

【図1】半導体チップの縦断面図である。FIG. 1 is a longitudinal sectional view of a semiconductor chip.

【図2】配線板の縦断面図である。FIG. 2 is a longitudinal sectional view of a wiring board.

【図3】画像認識カメラによる画像認識を示す斜視図で
ある。
FIG. 3 is a perspective view showing image recognition by an image recognition camera.

【図4】組立てられた半導体装置の縦断面図である。FIG. 4 is a longitudinal sectional view of the assembled semiconductor device.

【図5】従来の半導体装置の製造の際における画像認識
を示す斜視図である。
FIG. 5 is a perspective view showing image recognition in manufacturing a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1‥‥半導体チップ、2‥‥配線板、3‥‥画像認識カ
メラ、5‥‥電極、6‥‥電極、10‥‥半導体チッ
プ、11‥‥配線板、12‥‥電極、13‥‥電極、1
7‥‥画像認識カメラ、20‥‥電極
1 ‥‥ semiconductor chip, 2 ‥‥ wiring board, 3 ‥‥ image recognition camera, 5 ‥‥ electrode, 6 ‥‥ electrode, 10 ‥‥ semiconductor chip, 11 ‥‥ wiring board, 12 ‥‥ electrode, 13 ‥‥ electrode , 1
7mm image recognition camera, 20mm electrode

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】半導体チップを絶縁材料から成る配線板上
にマウントして成る半導体装置において、 前記配線板が透明または半透明であることを特徴とする
半導体装置。
1. A semiconductor device comprising a semiconductor chip mounted on a wiring board made of an insulating material, wherein the wiring board is transparent or translucent.
【請求項2】前記配線板が透明または半透明のマイカか
ら成ることを特徴とする請求項1に記載の半導体装置。
2. The semiconductor device according to claim 1, wherein said wiring board is made of transparent or translucent mica.
【請求項3】前記半導体チップの電極と前記配線板の電
極とが互いに接続されていることを特徴とする請求項1
に記載の半導体装置。
3. An electrode of the semiconductor chip and an electrode of the wiring board are connected to each other.
3. The semiconductor device according to claim 1.
【請求項4】半導体チップを絶縁材料から成る配線板上
にマウントして前記半導体チップの電極と前記配線板上
の電極とを互いに接続するようにした半導体装置の製造
方法において、 前記配線板を透明または半透明な材料によって製作する
とともに、 前記配線板に対して前記半導体チップとは反対側から画
像認識手段を用いて前記半導体チップの電極と前記配線
板の電極とを画像認識し、 該画像認識に基いて前記半導体チップと前記配線板の相
互の位置ずれを補正することを特徴とする半導体装置の
製造方法。
4. A method for manufacturing a semiconductor device, wherein a semiconductor chip is mounted on a wiring board made of an insulating material so that electrodes of the semiconductor chip and electrodes on the wiring board are connected to each other. It is made of a transparent or translucent material, and image-recognizing the electrodes of the semiconductor chip and the electrodes of the wiring board using image recognition means from the side opposite to the semiconductor chip with respect to the wiring board, A method of manufacturing a semiconductor device, comprising: correcting a mutual displacement between the semiconductor chip and the wiring board based on recognition.
JP30880698A 1998-10-29 1998-10-29 Semiconductor device and its manufacture Pending JP2000138259A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30880698A JP2000138259A (en) 1998-10-29 1998-10-29 Semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30880698A JP2000138259A (en) 1998-10-29 1998-10-29 Semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JP2000138259A true JP2000138259A (en) 2000-05-16

Family

ID=17985544

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30880698A Pending JP2000138259A (en) 1998-10-29 1998-10-29 Semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JP2000138259A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100709006B1 (en) * 2001-04-13 2007-04-18 앰코 테크놀로지 코리아 주식회사 Method for manufacturing semiconductor package
CN113013285A (en) * 2021-01-26 2021-06-22 中国科学院上海技术物理研究所 Process method for correcting errors of reverse welding process system of focal plane detector

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100709006B1 (en) * 2001-04-13 2007-04-18 앰코 테크놀로지 코리아 주식회사 Method for manufacturing semiconductor package
CN113013285A (en) * 2021-01-26 2021-06-22 中国科学院上海技术物理研究所 Process method for correcting errors of reverse welding process system of focal plane detector

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