JP2007157949A - Low-temperature calcination multilayer ceramic substrate - Google Patents

Low-temperature calcination multilayer ceramic substrate Download PDF

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JP2007157949A
JP2007157949A JP2005349994A JP2005349994A JP2007157949A JP 2007157949 A JP2007157949 A JP 2007157949A JP 2005349994 A JP2005349994 A JP 2005349994A JP 2005349994 A JP2005349994 A JP 2005349994A JP 2007157949 A JP2007157949 A JP 2007157949A
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low
ceramic substrate
multilayer ceramic
substrate
temperature fired
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Hajime Tomokage
肇 友景
Komei Hirai
孔明 平井
Shigekatsu Kono
成克 河野
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FUKUOKA PREF GOV SANGYO KAGAKU
HIRAI SEIMITSU KOGYO CORP
Fukuoka Industry Science and Technology Foundation
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FUKUOKA PREF GOV SANGYO KAGAKU
HIRAI SEIMITSU KOGYO CORP
Fukuoka Industry Science and Technology Foundation
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a low-temperature calcination multilayer ceramic substrate, capable of making substrate wiring high density and of simplifying a manufacturing process. <P>SOLUTION: The low-temperature calcination multilayer ceramic substrate has a recess 14, formed by low-temperature calcination on a substrate body 1 with a wiring patterns 11a, 12a, via holes 11b, 12b, and passive elements disposed thereon as a plurality of layers; an electrode 16 connected to the wiring patterns 11a, 12a, and the via holes 11b, 12b inside the recess 14; and an IC chip 3, mounted so as to be flip-chip bonded 31 onto the wiring pattern 11a on the uppermost layer of the substrate body 1. These are all constituted as a SiP (System in a Package). Accordingly, the system can be integrated by a simple manufacturing process, with high densified patterning of the substrate wiring. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、低温焼成多層セラミック基板(LTCC;Low Temperature Co-fired Ceramics)を基板本体として用いた低温焼成多層セラミック基板に関し、特に基板本体内に接続コネクタを内蔵した低温焼成多層セラミック基板に関する。   The present invention relates to a low-temperature fired multilayer ceramic substrate using a low-temperature fired multilayer ceramic substrate (LTCC) as a substrate body, and more particularly to a low-temperature fired multilayer ceramic substrate in which a connector is built in the substrate body.

従来、背景技術に係る低温焼成セラミック多層回路基板は、熱伝導性や耐熱性、化学的耐久性が有機材料基板より優れていることから、有機材料基板に代わるものとしてその利用が拡大してきている。また、電子機器の小型化、多様化に伴い高密度配線、高密度実装が可能な基板として広く使用されるようになってきた。さらに、今後は半導体ベアチップ実装基板としてその需要は高まると予想され、微細な配線が容易で、かつ信頼性が高い、という特徴を有することから、特に低温焼成セラミック多層回路基板の製造方法が必要になってくると考えられる。   Conventionally, the low-temperature fired ceramic multilayer circuit board according to the background art is superior in its thermal conductivity, heat resistance, and chemical durability to the organic material board, and its use is expanding as an alternative to the organic material board. . In addition, as electronic devices have become smaller and more diversified, they have been widely used as substrates capable of high-density wiring and high-density mounting. In addition, the demand for semiconductor bare chip mounting substrates is expected to increase in the future, and since it has the feature that fine wiring is easy and high in reliability, a method for manufacturing a low-temperature fired ceramic multilayer circuit board is particularly necessary. It is thought to become.

また、従来の低温焼成多層セラミック基板以外にある程度の高密度実装を可能とするものとして複合モジュール基板又は複合回路基板がある。これらの高密度実装ができる回路基板では、回路自体が微小化されるのに対してコネクタの微小化が困難である。特に、高密度実装された回路基板では、一つの基板当たりの素子数及び回路数が増大するに伴って、この各素子及び各回路の入出力端子数も増大することとなる。   In addition to the conventional low-temperature fired multilayer ceramic substrate, there is a composite module substrate or a composite circuit substrate that enables high-density mounting to some extent. In these circuit boards capable of high-density mounting, the circuit itself is miniaturized, but it is difficult to miniaturize the connector. In particular, in a circuit board mounted with high density, as the number of elements and circuits per board increase, the number of input / output terminals of each element and each circuit also increases.

このような入出力端子数の増大に対応するコネクタ内蔵モジュールとして特開2005−79318号公報に開示されるものがあり、図9に示す。同図において従来のコネクタ内蔵モジュールは、配線パターン104が設けられた電気絶縁層101と、1つ以上の能動部品及び受動部品から選ばれる少なくとも一つの電子部品103を電気絶縁層101に内蔵しているコネクタ内蔵モジュールであって、配線パターン104と電気接続し、かつ外部の電極に電気接続するための1つ以上のコネクタ102を内蔵し、このコネクタ102には、外部配線挿入部105が設けられている構成である。   As a module with a built-in connector corresponding to such an increase in the number of input / output terminals, there is one disclosed in Japanese Patent Laid-Open No. 2005-79318, which is shown in FIG. In the figure, a conventional connector built-in module includes an electric insulating layer 101 provided with a wiring pattern 104 and at least one electronic component 103 selected from one or more active components and passive components. One or more connectors 102 for electrically connecting the wiring pattern 104 and electrically connecting to external electrodes are built in, and the connector 102 is provided with an external wiring insertion portion 105. It is the composition which is.

この構成に基づき従来のコネクタ内蔵モジュールは、外部への信号の接続のために、ノイズの発生の少ない高密度実装が可能なコネクタ内蔵モジュールとこれを用いた複合モジュール及び回路基板とすることができることとなる。
特開2005−79318号公報
Based on this configuration, a conventional module with a built-in connector can be a module with a built-in connector capable of high-density mounting with little noise generation, a composite module and a circuit board using the same, for signal connection to the outside. It becomes.
JP-A-2005-79318

前記各背景技術は以上のように構成されていたことから、入出力端子を内蔵するコネクタ内蔵モジュールをLTCCで製作しようとすると電気絶縁層101とコネクタ102とを別途に形成し、各形成された電気絶縁層101にコネクタ102を組付けてコネクタ内蔵モジュールを構成しなければならず、電気絶縁層101をLTCCとして焼成する工程、コネクタ102を作成する工程及びこれらを組付ける工程を各々必要とすることとなり製造工程が複雑化し、製品コストを低減できないという課題を有していた。   Since each of the above background arts is configured as described above, when trying to manufacture a connector built-in module with built-in input / output terminals by LTCC, the electrical insulating layer 101 and the connector 102 are separately formed, and each formed A connector built-in module must be constructed by assembling the connector 102 to the electrical insulating layer 101, and a process of firing the electrical insulating layer 101 as LTCC, a process of creating the connector 102, and a process of assembling them are required. As a result, the manufacturing process becomes complicated, and the product cost cannot be reduced.

特に、前記背景技術における電気絶縁層101にコネクタ102を組付ける組付け工程は高密度実装を前提とする回路基板の電気絶縁層101自体が微小化されており、この微小化された電気絶縁層101にさらに微細化されたコネクタ102を組付けなければならず、この組付け作業に極めて高い精度が要求されるという課題を有する。また、電気絶縁層101がコネクタ102とは別途に製作されることから、コネクタ102が取付けられる電気絶縁層101の側面における基板配線の高密度化ができないという課題を有する。   In particular, in the assembly process for assembling the connector 102 to the electrical insulation layer 101 in the background art, the electrical insulation layer 101 itself of the circuit board premised on high-density mounting is miniaturized, and this miniaturized electrical insulation layer The connector 102 that is further miniaturized must be assembled to the 101, and this assembly work has a problem that extremely high accuracy is required. In addition, since the electrical insulating layer 101 is manufactured separately from the connector 102, there is a problem that the density of the substrate wiring on the side surface of the electrical insulating layer 101 to which the connector 102 is attached cannot be increased.

本発明は前記課題を解消するためになされたもので、基板配線の高密度化と共に製造工程を簡略化できる低温焼成多層セラミック基板を提供することを目的とする。   The present invention has been made to solve the above problems, and an object of the present invention is to provide a low-temperature fired multilayer ceramic substrate capable of simplifying the manufacturing process as well as increasing the density of substrate wiring.

本発明に係る低温焼成多層セラミック基板は、配線パターンが複数の層として形成される基板本体からなる低温焼成多層セラミック基板において、前記基板本体の側端面に凹部又は段差部を形成し、当該凹部又は段差部に前記配線パターン又はビアと接続される電極を配設されるものである。   The low-temperature fired multilayer ceramic substrate according to the present invention is a low-temperature fired multilayer ceramic substrate comprising a substrate body in which a wiring pattern is formed as a plurality of layers, wherein a concave portion or a step portion is formed on a side end surface of the substrate body. An electrode connected to the wiring pattern or via is disposed on the stepped portion.

このように本発明においては、配線パターンが複数の層として形成される基板本体の側端面に凹部又は段差部を形成し、当該凹部内又は段差部に前記配線パターン又はビアと接続される電極を配設されることから、基板本体と凹部内又は段差部に配設される電極からなるコネクタとを簡易な製造工程で一体形成できると共に、基板配線を高密度化できる。   Thus, in the present invention, a recess or a step portion is formed on the side end surface of the substrate body on which the wiring pattern is formed as a plurality of layers, and an electrode connected to the wiring pattern or the via is formed in the recess or the step portion. Thus, the board body and the connector made of electrodes arranged in the recess or the stepped portion can be integrally formed by a simple manufacturing process, and the board wiring can be densified.

また、本発明に係る低温焼成多層セラミック基板は必要に応じて、電極が、基板本体の側端面に形成される凹部の内側面又は段差部の表面に前記配線パターンから延出して形成されるものである。   In addition, the low-temperature fired multilayer ceramic substrate according to the present invention is formed by extending the wiring pattern from the wiring pattern on the inner surface of the recess or the surface of the stepped portion formed on the side end surface of the substrate body as necessary. It is.

このように本発明においては、基板本体に複数の層として形成される配線パターンを基板本体の側端面に形成される凹部の内側面又は段差部の表面にまで延出させ、この延出した配線パターンで電極を形成しているので、基板本体の低温焼成と同時にコネクタを微細且つ高密度に形成できると共に、基板配線を高密度化できる。   Thus, in the present invention, the wiring pattern formed as a plurality of layers on the substrate body is extended to the inner surface of the recess or the surface of the stepped portion formed on the side end surface of the substrate body, and this extended wiring Since the electrodes are formed in a pattern, the connectors can be formed finely and with high density simultaneously with the low-temperature firing of the substrate body, and the substrate wiring can be made dense.

また、本発明に係る低温焼成多層セラミック基板は必要に応じて、凹部の底面又は段差部の側面に前記配線パターンに到達する深さの細線状の取付穴が形成され、前記電極が細線状の針体として形成され、当該針体を低温焼成された基板本体の取付穴に挿通固定されるものである。   In addition, the low-temperature fired multilayer ceramic substrate according to the present invention is provided with a thin wire-like mounting hole having a depth reaching the wiring pattern on the bottom surface of the concave portion or the side surface of the step portion, if necessary, and the electrode has a thin wire shape. It is formed as a needle body, and the needle body is inserted and fixed in an attachment hole of a substrate body that is fired at a low temperature.

このように本発明においては、基板本体の側端面に形成された凹部の低面又は段差部の側面に形成された取付穴に細線状の針体からなる電極を配線パターンに到達するまで挿通してコネクタ部を形成するようにしているので基板本体と凹部内又は段差部に配設される電極からなるコネクタとを簡易な製造工程で一体形成できると共に、基板配線を高密度化できる。   As described above, in the present invention, the electrode made of a fine needle is inserted into the mounting hole formed on the lower surface of the concave portion or the side surface of the step portion formed on the side end surface of the substrate body until the wiring pattern is reached. Thus, the connector portion is formed, so that the substrate main body and the connector formed of the electrode disposed in the recess or the step portion can be integrally formed by a simple manufacturing process, and the substrate wiring can be densified.

また、本発明に係る低温焼成多層セラミック基板は必要に応じて、電極が、複数層の配線パターンのうち対応する中間層の一の配線パターンに接続され、当該一の配線パターン以外の他の配線パターンをビアホールにより一の配線パターンを介して接続されるものである。   Further, in the low-temperature fired multilayer ceramic substrate according to the present invention, if necessary, the electrode is connected to one wiring pattern of the corresponding intermediate layer among the plurality of wiring patterns, and other wirings other than the one wiring pattern. The patterns are connected through a single wiring pattern by via holes.

このように本発明においては、電極が、複数層の配線パターンのうち対応する中間層の一の配線パターンに接続され、当該一の配線パターン以外の他の配線パターンをビアホールにより一の配線パターンを介して接続されることから、複数の層に各々形成されるいずれの配線パターンもビアホールを介してコネクタに接続できることとなり、基板本体と凹部内又は段差部に配設される電極からなるコネクタとを簡易な製造工程で一体形成できると共に、基板配線を高密度化できる。   Thus, in the present invention, an electrode is connected to one wiring pattern of a corresponding intermediate layer among a plurality of wiring patterns, and one wiring pattern other than the one wiring pattern is connected to one wiring pattern by a via hole. Therefore, any wiring pattern formed in each of the plurality of layers can be connected to the connector via the via hole, and the connector composed of the substrate body and the electrode disposed in the recess or the stepped portion is provided. It can be formed integrally with a simple manufacturing process, and the substrate wiring can be densified.

また、本発明に係る低温焼成多層セラミック基板は必要に応じて、基板本体を相互に、複数連結して単一の基板を構成するものである。
このように本発明においては、基板本体を相互に、複数連結して単一の基板を構成することにより、基板として大きく形成できる。特に、複数の基板本体が各々異なる機能を有する場合には、連結した基板が多機能基板として構成でき、また各基板本体が同一又は異なる機能を有する場合であっても相互に補完的又は相乗的に機能を向上させることができる。
Further, the low-temperature fired multilayer ceramic substrate according to the present invention comprises a single substrate by connecting a plurality of substrate bodies to each other as required.
As described above, in the present invention, a plurality of substrate bodies are connected to each other to form a single substrate, whereby a large substrate can be formed. In particular, when a plurality of board bodies have different functions, the connected boards can be configured as a multifunction board, and even if each board body has the same or different functions, they are complementary or synergistic to each other. The function can be improved.

(本発明の第1の実施形態)
以下、本発明の第1の実施形態に係る低温焼成多層セラミック基板を図1ないし図3に基づいて説明する。この図1は本実施形態に係る低温焼成多層セラミック基板の概略構成斜視図、図2は図1に記載する低温焼成多層セラミック基板のA−A線断面図、図3は図1に記載する低温焼成多層セラミック基板の製造工程説明図を示す。
(First embodiment of the present invention)
Hereinafter, a low-temperature fired multilayer ceramic substrate according to a first embodiment of the present invention will be described with reference to FIGS. 1 is a schematic perspective view of a low-temperature fired multilayer ceramic substrate according to the present embodiment, FIG. 2 is a cross-sectional view taken along the line AA of the low-temperature fired multilayer ceramic substrate shown in FIG. 1, and FIG. The manufacturing process explanatory drawing of a baking multilayer ceramic substrate is shown.

前記各図において本実施形態に係る低温焼成多層セラミック基板は、複数の層として配線パターン11a、12a、ビア11b、12b及び受動素子が配設される基板本体1及びこの基板本体1の側端面に凹部14が低温焼成にて形成され、この凹部14内に前記配線パターン11a、12a又はビア11b、12bと接続する電極16が形成され、前記基板本体1の最上層でICチップ3を配線パターン11aにフリップチップボンディング31されるように実装されてSiP(System in a Package)として構成される。   In each of the drawings, the low-temperature fired multilayer ceramic substrate according to the present embodiment includes a substrate body 1 on which wiring patterns 11a, 12a, vias 11b, 12b and passive elements are arranged as a plurality of layers, and a side end surface of the substrate body 1. A recess 14 is formed by low-temperature firing, and an electrode 16 connected to the wiring patterns 11a, 12a or vias 11b, 12b is formed in the recess 14, and the IC chip 3 is connected to the wiring pattern 11a on the uppermost layer of the substrate body 1. It is mounted so as to be flip-chip bonded 31 and configured as a SiP (System in a Package).

前記基板本体1は、配線パターン11a、12a、ビア11b、12b及び受動素子が各々配設されるセラミック基板11、12(本実施形態において模式的に二層に簡略化して記載する。)を順次積層し、この積層した状態で低温焼成される。前記電極16は、凹部14の低面に配線パターン12aに到達する深さの細穴状の取付穴16aが基板本体1の低温焼成と同時に形成され、この基板本体1が低温焼成された後の取付穴16aの細線状の導電針体16bを配線パターン12aに接触させた状態で挿通固定して構成される。   The substrate main body 1 sequentially includes ceramic substrates 11 and 12 (represented schematically in two layers in this embodiment, simplified) in which wiring patterns 11a and 12a, vias 11b and 12b, and passive elements are respectively disposed. Laminated and fired at a low temperature in this laminated state. The electrode 16 is formed with a thin hole-like attachment hole 16a having a depth reaching the wiring pattern 12a on the lower surface of the recess 14 at the same time as the substrate body 1 is fired at low temperature. The thin wire-like conductive needle body 16b of the mounting hole 16a is inserted and fixed while being in contact with the wiring pattern 12a.

前記電極16に接続される接続プラグ2は、凹部14の凹溝形状に対応する外形寸法で形成されるプラグ本体21と、このプラグ本体21の先端に導電針体16bに嵌合する挿通穴とし、この挿通穴の内側面を導電材で形成される接触部22と、この接触部22に導体芯線23が接続されるケーブル24とを備える構成である。   The connection plug 2 connected to the electrode 16 has a plug main body 21 formed with an external dimension corresponding to the concave groove shape of the concave portion 14, and an insertion hole that fits the conductive needle body 16 b at the tip of the plug main body 21. The contact portion 22 is formed of a conductive material on the inner side surface of the insertion hole, and the cable 24 has a conductor 24 connected to the contact portion 22.

次に、前記構成に基づく本実施形態に係る低温焼成多層セラミック基板の形成動作及び接続プラグ2との接続動作について説明する。まず、低温焼成多層セラミック基板の形成動作について、下層のセラミック基板12は端部に凹部14に対応する切欠き部14bが形成されると共に、表面に配線パターン12a、ビア12b、さらに受動素子等(図示を省略する。)が形成される(図3(A)を参照)。また、上層のセラミック基板11は、端部に凹部14に対応する切欠き部14aが形成されると共に、表面に配線パターン11a、ビア11b及び及び取付穴16a、さらに受動素子等(図示を省略する。)が形成される(図3(A)を参照)。   Next, the formation operation of the low-temperature fired multilayer ceramic substrate and the connection operation with the connection plug 2 according to this embodiment based on the above configuration will be described. First, regarding the formation operation of the low-temperature fired multilayer ceramic substrate, the lower ceramic substrate 12 has a notch 14b corresponding to the recess 14 at the end, and a wiring pattern 12a, a via 12b, a passive element, etc. (Not shown) is formed (see FIG. 3A). The upper ceramic substrate 11 has a notch 14a corresponding to the recess 14 at the end, a wiring pattern 11a, a via 11b, a mounting hole 16a on the surface, and a passive element (not shown). .) Is formed (see FIG. 3A).

前記セラミック基板12上にセラミック基板11を図3(B)に示すように積層し、この積層した状態で低温(例えば、900℃以下)により焼成して一体化する。この低温焼成により各セラミック基板11、12に各々形成された配線パターン11a、12a、ビア11b、12b、受動素子を銅(Cu)、銀(Ag)等の低融点の金属が用いられたとしても同等に焼成して一体化できる。   The ceramic substrate 11 is laminated on the ceramic substrate 12 as shown in FIG. 3B, and in this laminated state, it is fired and integrated at a low temperature (for example, 900 ° C. or less). Even if a low melting point metal such as copper (Cu) or silver (Ag) is used for the wiring patterns 11a and 12a, the vias 11b and 12b formed on the ceramic substrates 11 and 12 by the low temperature firing, and the passive elements, respectively. It can be fired equally and integrated.

このように一体化された基板本体1は、図3(C)に示すように取付穴16aに導電針体16bが挿通されて凹部14内に電極16が形成されると共に、上面の配線パターン11aの電極端子部分とICチップ3の入出力端子部分に形成されたバンプとをフリップチップボンディング31により接合する。
このように形成された低温焼成多層セラミック基板の基板本体1は、図3(D)に示すように、凹部14に接続プラグ2のプラグ本体21を挿し込むと共に、導電針体16bを接触部22の挿通接触させて接続動作を完了する。
As shown in FIG. 3C, the substrate body 1 integrated in this way has the conductive needle body 16b inserted through the mounting hole 16a to form the electrode 16 in the recess 14, and the wiring pattern 11a on the upper surface. These electrode terminal portions and bumps formed on the input / output terminal portions of the IC chip 3 are joined by flip chip bonding 31.
As shown in FIG. 3D, the substrate main body 1 of the low-temperature fired multilayer ceramic substrate formed in this way inserts the plug main body 21 of the connection plug 2 into the concave portion 14 and connects the conductive needle body 16b to the contact portion 22. The connecting operation is completed by inserting through.

(本発明の第2の実施形態)
本発明の第2の実施形態に係る低温焼成多層セラミック基板を図4及び図5に基づいて説明する。この図4は本実施形態に係る低温焼成多層セラミック基板の概略構成斜視図、図5は図4に記載する低温焼成多層セラミック基板のB−B線断面図を示す。
(Second embodiment of the present invention)
A low-temperature fired multilayer ceramic substrate according to a second embodiment of the present invention will be described with reference to FIGS. 4 is a schematic perspective view of the low-temperature fired multilayer ceramic substrate according to this embodiment, and FIG. 5 is a cross-sectional view taken along the line BB of the low-temperature fired multilayer ceramic substrate shown in FIG.

前記各図において本実施形態に係る低温焼成多層セラミック基板は、前記第1の実施形態に係る低温焼成多層セラミック基板と同様に、複数の層として配線パターン11a、12a、13a、ビア11b、12b、13b及び受動素子が配設される基板本体1及びこの基板本体1の側端面に凹部14が低温焼成にて形成され、この凹部14内に前記配線パターン11a、12a、13a又はビア11b、12b、13bと接続する電極17が形成され、前記基板本体1の最上層でICチップ3を配線パターン11aにフリップチップボンディング31されるように実装されてSiPとして構成される。また、前記基板本体1は、第1の実施形態の場合と異なりセラミック基板11、12、13の三層に簡略化して構成され、同様にこの積層された状態で低温焼成される。   In each of the drawings, the low-temperature fired multilayer ceramic substrate according to the present embodiment is similar to the low-temperature fired multilayer ceramic substrate according to the first embodiment, as wiring layers 11a, 12a, 13a, vias 11b, 12b, 13b and the substrate body 1 on which the passive elements are disposed, and a recess 14 is formed in the side end surface of the substrate body 1 by low-temperature firing, and the wiring patterns 11a, 12a, 13a or the vias 11b, 12b, An electrode 17 connected to 13b is formed, and the IC chip 3 is mounted on the wiring pattern 11a on the uppermost layer of the substrate body 1 so as to be flip-chip bonded 31 to form an SiP. Further, unlike the case of the first embodiment, the substrate body 1 is configured to be simplified to three layers of ceramic substrates 11, 12, and 13 and similarly fired at a low temperature in this laminated state.

前記電極17は、基板本体1の凹部14における対向する側面に配線パターン12a、13aを延出させた露出部分として構成され、また配線パターン12a、13aと連結するビア11b、12b、13bに接続される胴体部分として構成される。この電極17に接続される接続プラグ5は、凹部14の凹溝形状に対応する外形寸法で形成されるプラグ本体51と、このプラグ本体51の先端両側面に短冊状の導電材で形成される接触部52と、この接触部52に導体芯線53が接続されるケーブル54とを備える構成である。   The electrode 17 is configured as an exposed portion in which the wiring patterns 12a and 13a are extended on opposite side surfaces of the concave portion 14 of the substrate body 1, and is connected to vias 11b, 12b and 13b connected to the wiring patterns 12a and 13a. It is configured as a body part. The connection plug 5 connected to the electrode 17 is formed of a plug main body 51 formed with an outer dimension corresponding to the concave groove shape of the concave portion 14, and a strip-shaped conductive material on both side surfaces of the tip end of the plug main body 51. The configuration includes a contact portion 52 and a cable 54 to which a conductor core wire 53 is connected.

次に、前記構成に基づく本実施形態に係る低温焼成多層セラミック基板の形成動作及び接続プラグ5との接続動作について説明する。まず、本実施形態に係る低温焼成多層セラミック基板の形成動作について、最下層のセラミック基板13は表面に配線パターン13a、ビア13b及びこの配線パターン13aを延出させて短冊状の導電材で露出部分となる電極17が形成される。また、中層セラミック基板12は端部をセラミック基板13の長さより接続プラグ5のプラグ本体51が嵌合する寸法だけ短く形成されると共に、表面に配線パターン12a、ビア12b、さらに受動素子等(図示を省略する。)が形成される。また、上層部のセラミック基板11は、裏面端部にセラミック基板12のセラミック基板12の配線パターン12aと接触する短冊状の導電材で露出部分となる電極17が形成されると共に、表面に配線パターン11a、ビア11b及び取付穴16a、さらに受動素子等(図示を省略する。)が形成される。   Next, the formation operation of the low-temperature fired multilayer ceramic substrate and the connection operation with the connection plug 5 according to this embodiment based on the above configuration will be described. First, regarding the formation operation of the low-temperature fired multilayer ceramic substrate according to the present embodiment, the lowermost ceramic substrate 13 has a wiring pattern 13a, a via 13b, and an exposed portion of a strip-shaped conductive material extending from the wiring pattern 13a on the surface. An electrode 17 is formed. Further, the middle layer ceramic substrate 12 is formed so that the end thereof is shorter than the length of the ceramic substrate 13 by the dimension that the plug main body 51 of the connection plug 5 is fitted, and the wiring pattern 12a, via 12b, passive elements, etc. Is omitted). The upper layer ceramic substrate 11 has an electrode 17 that is an exposed portion formed of a strip-shaped conductive material in contact with the wiring pattern 12a of the ceramic substrate 12 of the ceramic substrate 12 at the back end portion, and the wiring pattern on the surface. 11a, vias 11b, mounting holes 16a, and passive elements (not shown) are formed.

前記セラミック基板13の上にセラミック基板12を積層し、さらにこのセラミック基板12の上にセラミック基板11を積層し、前記第1の実施形態と同様にこの積層された状態で低温(例えば、900℃以下)により焼成して一体化する。上面の配線パターン11aの電極端子部分と、ICチップ3の入出力端子部分に形成されたバンプとをフリップチップボンディング31により接合する。   A ceramic substrate 12 is laminated on the ceramic substrate 13, and further a ceramic substrate 11 is laminated on the ceramic substrate 12. In the laminated state as in the first embodiment, a low temperature (for example, 900 ° C.) is used. The following is fired and integrated. The electrode terminal portion of the wiring pattern 11 a on the upper surface and the bump formed on the input / output terminal portion of the IC chip 3 are joined by flip chip bonding 31.

このように形成された低温焼成多層セラミック基板の基板本体1は、図5に示すように、凹部14に接続プラグ5のプラグ本体51を挿し込むことにより、この凹部14内に対向する二つの電極17に接続プラグ5の各接触部52を接触させて接続動作を完了する。   As shown in FIG. 5, the substrate body 1 of the low-temperature fired multilayer ceramic substrate formed in this way has two electrodes facing each other in the recess 14 by inserting the plug body 51 of the connection plug 5 into the recess 14. 17, the contact portions 52 of the connection plug 5 are brought into contact with each other to complete the connection operation.

(本発明の第3の実施形態)
本発明の第3の実施形態に係る低温焼成多層セラミック基板を図6に基づいて説明する。この図6は本実施形態に係る低温焼成多層セラミック基板の概略構成斜視図を示す。
同図において本実施形態に係る低温焼成多層セラミック基板は、前記第2の実施形態に係る低温焼成多層セラミック基板の凹部14とは異なり、短冊状の導電材からなる電極17を段差状の平面部に露出させる段部18で構成され、この電極17が下層のセラミック基板12に形成される配線パターン12aから延出した導電材として形成される。
(Third embodiment of the present invention)
A low-temperature fired multilayer ceramic substrate according to a third embodiment of the present invention will be described with reference to FIG. FIG. 6 shows a schematic perspective view of the low-temperature fired multilayer ceramic substrate according to this embodiment.
In the figure, the low-temperature fired multilayer ceramic substrate according to the present embodiment is different from the recess 14 of the low-temperature fired multilayer ceramic substrate according to the second embodiment in that the electrode 17 made of a strip-shaped conductive material is provided with a stepped planar portion. The electrode 17 is formed as a conductive material extending from the wiring pattern 12 a formed on the lower ceramic substrate 12.

また、前記電極17は、上層のセラミック基板11の配線パターンから段部18の表面に沿って段差状に引き廻すように段部18の平面部まで延出させる構成とすることもできる。この場合には、段部18の段差状の平面部及び起立部の両面で電極17を構成することができることとなり、より確実に各低温焼成多層セラミック基板相互間の接続が可能となる。   Further, the electrode 17 may be configured to extend from the wiring pattern of the upper ceramic substrate 11 to the flat portion of the step portion 18 so as to be stepped along the surface of the step portion 18. In this case, the electrode 17 can be formed on both the stepped flat surface portion and the upright portion of the step portion 18, and the low-temperature fired multilayer ceramic substrates can be more reliably connected to each other.

次に、本実施形態に係る低温焼成多層セラミック基板の基板本体1を他の低温焼成多層セラミック基板の基板本体4に接続する場合には、基板本体1の段部18と基板本体4の両側突出部41を係合させ、この段部18の平面部及び起立部に形成される電極17と突出部41の下面及び内側面に形成される電極41aを接触させる。また、基板本体1と同一形状の他の基板本体を接続する場合も、前記基板本体4の場合と同様に各々重ね合わせて基板本体1の段部18と他の基板本体の両側突出部(19に相当する。)を係合させることにより実行される。   Next, when the substrate body 1 of the low-temperature fired multilayer ceramic substrate according to the present embodiment is connected to the substrate body 4 of another low-temperature fired multilayer ceramic substrate, the step portion 18 of the substrate body 1 and both side protrusions of the substrate body 4 are projected. The portion 41 is engaged, and the electrode 17 formed on the flat portion and the upright portion of the stepped portion 18 is brought into contact with the electrode 41 a formed on the lower surface and the inner side surface of the protruding portion 41. Also, when connecting another substrate body having the same shape as the substrate body 1, as in the case of the substrate body 4, they are overlapped with each other so that the stepped portion 18 of the substrate body 1 and both side protrusions (19 It is executed by engaging.

(本発明の他の実施形態)
本発明の他の実施形態に係る低温焼成多層セラミック基板を図7及び図8に基づいて説明する。この図7は、本発明の他の実施形態に係る低温焼成多層セラミック基板の外観斜視図及び連結態様断面図、図8は本発明の他の実施形態に係る低温焼成多層セラミック基板の外観斜視図及び連結態様展開図を示す。
(Other embodiments of the present invention)
A low-temperature fired multilayer ceramic substrate according to another embodiment of the present invention will be described with reference to FIGS. 7 is an external perspective view and a cross-sectional view of a low temperature fired multilayer ceramic substrate according to another embodiment of the present invention, and FIG. 8 is an external perspective view of a low temperature fired multilayer ceramic substrate according to another embodiment of the present invention. And a connection mode development view is shown.

前記図7に記載の低温焼成多層セラミック基板は、前記各実施形態における基板本体1と同様に基板本体10が形成され、この基板本体10の一側端側に凹部14が形成されると共に他側端側に凸部15が形成され、この凹部14内に形成される電極17bとこの電極17bに対応する位置の前記凸部15外側に電極17aが形成される構成である。前記凹部14及び凸部15は、各基板本体10が相互に連結した場合に嵌合して、電極17aと電極17bとが密着状態で接触するように形成される。   In the low-temperature fired multilayer ceramic substrate shown in FIG. 7, a substrate body 10 is formed in the same manner as the substrate body 1 in each of the above embodiments, and a recess 14 is formed on one side end side of the substrate body 10 and the other side. A convex portion 15 is formed on the end side, and an electrode 17b is formed in the concave portion 14, and an electrode 17a is formed outside the convex portion 15 at a position corresponding to the electrode 17b. The concave portion 14 and the convex portion 15 are formed so as to be fitted when the substrate bodies 10 are connected to each other so that the electrode 17a and the electrode 17b are in close contact with each other.

このように複数の基板本体10を一軸方向に連続して連結することにより、小さな基板本体10により基板として大きく形成できる(図7(B)を参照)。特に、複数の基板本体10が各々異なる機能を有する場合には、連結した基板が多機能基板として構成でき、また各基板本体10が同一又は異なる機能を有する場合であっても相互に補完的又は相乗的に機能を向上させることができる。   In this way, by connecting a plurality of substrate bodies 10 continuously in a uniaxial direction, the substrate can be formed larger by a small substrate body 10 (see FIG. 7B). In particular, when the plurality of substrate bodies 10 have different functions, the connected substrates can be configured as a multifunction substrate, and even if the substrate bodies 10 have the same or different functions, The function can be improved synergistically.

前記図8に記載の低温焼成多層セラミック基板は、前記図7記載の低温焼成多層セラミック基板の一軸方向への複数の基板本体10の連結に加え、この一軸(x軸方向)に直交する他軸方向(y軸方向)へも複数の基板本体10を連結する構成である。このx軸・y軸の交点に位置する基板本体100は、図8(A)に示すように、方形状基板の相隣る各二つの側端面に凹部14及び凸部15を形成し、この凹部14内に電極17bを形成すると共に凸部15外側に電極17aを形成して構成される。   The low-temperature fired multilayer ceramic substrate shown in FIG. 8 is connected to a plurality of substrate bodies 10 in one axial direction of the low-temperature fired multilayer ceramic substrate shown in FIG. 7, and the other axis orthogonal to this one axis (x-axis direction). In this configuration, a plurality of substrate bodies 10 are also connected in the direction (y-axis direction). As shown in FIG. 8A, the substrate body 100 located at the intersection of the x-axis and the y-axis is formed with concave portions 14 and convex portions 15 on two adjacent side end surfaces of the rectangular substrate. An electrode 17b is formed in the concave portion 14 and an electrode 17a is formed outside the convex portion 15.

この基板本体100を中心としてx軸方向及びy軸方向へ前記図7に記載の基板本体10を図8(B)に示すように順次連結して展開することができる。このようにx・y軸の二軸方向に複数の基板本体10を連結することにより、より大規模な多機能基板を簡易且つ確実に形成することができる。   With the substrate body 100 as the center, the substrate body 10 shown in FIG. 7 can be sequentially connected and developed in the x-axis direction and the y-axis direction as shown in FIG. 8B. Thus, by connecting a plurality of substrate bodies 10 in the biaxial directions of the x and y axes, a larger-scale multifunction substrate can be easily and reliably formed.

本発明の第1の実施形態に係る低温焼成多層セラミック基板の概略構成斜視図である。1 is a schematic configuration perspective view of a low-temperature fired multilayer ceramic substrate according to a first embodiment of the present invention. 図1に記載する低温焼成多層セラミック基板のA−A線断面図である。It is the sectional view on the AA line of the low-temperature baking multilayer ceramic substrate described in FIG. 図1に記載する低温焼成多層セラミック基板の製造工程説明図図である。It is explanatory drawing of the manufacturing process of the low-temperature baking multilayer ceramic substrate described in FIG. 本発明の第2の実施形態に係る低温焼成多層セラミック基板の概略構成斜視図である。It is a schematic perspective view of a low-temperature fired multilayer ceramic substrate according to a second embodiment of the present invention. 図4に記載する低温焼成多層セラミック基板のB−B線断面図である。FIG. 5 is a cross-sectional view of the low-temperature fired multilayer ceramic substrate shown in FIG. 4 taken along the line BB. 本発明の第3の実施形態に係る低温焼成多層セラミック基板の概略構成斜視図である。It is a schematic structure perspective view of the low-temperature baking multilayer ceramic substrate which concerns on the 3rd Embodiment of this invention. 本発明の他の実施形態に係る低温焼成多層セラミック基板の外観斜視図及び連結態様断面図である。It is the external appearance perspective view and connection aspect sectional drawing of the low-temperature baking multilayer ceramic substrate which concerns on other embodiment of this invention. 本発明の他の実施形態に係る低温焼成多層セラミック基板の外観斜視図及び連結態様展開図である。It is the external appearance perspective view and connection mode expansion | deployment figure of the low-temperature baking multilayer ceramic substrate which concerns on other embodiment of this invention. 従来の高密度実装を可能とするコネクタ内蔵モジュールの断面図である。It is sectional drawing of the module with a built-in connector which enables the conventional high-density mounting.

符号の説明Explanation of symbols

1、4、10、100 基板本体
11a、12a、13a 配線パターン
11b、12b、13b ビア
14 凹部
14a、14b 切欠き部
15 凸部
16、17、17a、17b、41a 電極
16a 取付穴
16b 導電針体
18 段部
19、41 突出部
2、5 接続プラグ
21、51 プラグ本体
22、52 接触部
23、53 導体芯線
24、54 ケーブル
3 ICチップ
31 フリップチップボンディング
1, 4, 10, 100 Substrate body 11a, 12a, 13a Wiring pattern 11b, 12b, 13b Via 14 Recess 14a, 14b Notch 15 Protrusion 16, 17, 17a, 17b, 41a Electrode 16a Mounting hole 16b Conductive needle body 18 Steps 19, 41 Protruding part 2, 5 Connection plug 21, 51 Plug body 22, 52 Contact part 23, 53 Conductor core wire 24, 54 Cable 3 IC chip 31 Flip chip bonding

Claims (5)

配線パターンが複数の層として形成される基板本体からなる低温焼成多層セラミック基板において、
前記基板本体の側端面に凹部又は段差部を形成し、当該凹部又は段差部に前記配線パターン又はビアと接続される電極を配設されることを
特徴とする低温焼成多層セラミック基板。
In a low-temperature fired multilayer ceramic substrate comprising a substrate body in which a wiring pattern is formed as a plurality of layers
A low-temperature fired multilayer ceramic substrate, wherein a concave portion or a step portion is formed on a side end surface of the substrate body, and an electrode connected to the wiring pattern or the via is disposed in the concave portion or the step portion.
前記請求項1に記載の低温焼成多層セラミック基板において、
前記電極が、基板本体の側端面に形成される凹部の内側面又は段差部の表面に前記配線パターンから延出して形成されることを
特徴とする低温焼成多層セラミック基板。
In the low-temperature fired multilayer ceramic substrate according to claim 1,
The low-temperature fired multilayer ceramic substrate, wherein the electrode is formed to extend from the wiring pattern on an inner surface of a recess or a surface of a stepped portion formed on a side end surface of a substrate body.
前記請求項1に記載の低温焼成多層セラミック基板において、
前記凹部の底面又は段差部の側面に前記配線パターンに到達する深さの細線状の取付穴が形成され、
前記電極が細線状の針体として形成され、当該針体を低温焼成された基板本体の取付穴に挿通固定されることを
特徴とする低温焼成多層セラミック基板。
In the low-temperature fired multilayer ceramic substrate according to claim 1,
A thin wire-like mounting hole reaching the wiring pattern is formed on the bottom surface of the recess or the side surface of the stepped portion,
A low-temperature fired multilayer ceramic substrate, wherein the electrode is formed as a fine-line needle body, and the needle body is inserted and fixed in a mounting hole of a substrate body fired at a low temperature.
前記請求項1ないし3のいずれかに記載の低温焼成多層セラミック基板において、
前記電極が、複数層の配線パターンのうち対応する中間層の一の配線パターンに接続され、当該一の配線パターン以外の他の配線パターンをビアホールにより一の配線パターンを介して接続されることを
特徴とする低温焼成多層セラミック基板。
In the low-temperature fired multilayer ceramic substrate according to any one of claims 1 to 3,
The electrode is connected to one wiring pattern of a corresponding intermediate layer among a plurality of wiring patterns, and other wiring patterns other than the one wiring pattern are connected via one wiring pattern by via holes. A low temperature fired multilayer ceramic substrate.
前記請求項1ないし4のいずれかに記載の低温焼成多層セラミック基板において、
前記基板本体を相互に、複数連結して単一の基板を構成することを
特徴とする低温焼成多層セラミック基板。
In the low-temperature fired multilayer ceramic substrate according to any one of claims 1 to 4,
A low-temperature fired multilayer ceramic substrate, wherein a plurality of the substrate bodies are connected to each other to form a single substrate.
JP2005349994A 2005-12-02 2005-12-02 Low-temperature calcination multilayer ceramic substrate Pending JP2007157949A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015531545A (en) * 2012-09-17 2015-11-02 コミッサリア ア レネルジー アトミーク エ オ エナジーズ アルタナティブス Cap for device with groove and chip, device equipped with cap, assembly of device and wiring element, and manufacturing method thereof
CN105811753A (en) * 2016-03-17 2016-07-27 电子科技大学 Low temperature co-fired ceramic (LTCC) DC-DC converter substrate resistant to high current

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015531545A (en) * 2012-09-17 2015-11-02 コミッサリア ア レネルジー アトミーク エ オ エナジーズ アルタナティブス Cap for device with groove and chip, device equipped with cap, assembly of device and wiring element, and manufacturing method thereof
US9888573B2 (en) 2012-09-17 2018-02-06 Commissariat A L'energie Atomique Et Aux Energies Alternatives Cap for a chip device having a groove, device provided with said cap, assembly consisting of the device and a wire element, and manufacturing method thereof
JP2019033266A (en) * 2012-09-17 2019-02-28 コミッサリア ア レネルジー アトミーク エ オ エナジーズ アルタナティブス Cap for groove-attached and chip-attached device, cap-equipped device, assembly of device and wiring element, and manufacturing method thereof
CN105811753A (en) * 2016-03-17 2016-07-27 电子科技大学 Low temperature co-fired ceramic (LTCC) DC-DC converter substrate resistant to high current

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