JP2000134586A - Image information conversion device and image display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate the output image signals of higher resolution compared with the input image signals in various formats. SOLUTION: The output image signals of double number of pixels are produced at different pixel positions of both vertical and horizontal directions by an LSI 101A of a pixel generation device for class sorting adaptive processing. In the same way, the output image signals of high resolution are produced by an LSI 101B. The line frequency of ever output image signal is quadrupled by the line memories 6A, 6B, 16A and 16B. A selector 7A selects the image data which are generated at every pixel position. A progressive signal having double number of both horizontal and vertical pixels on an interlace signal having double number of horizontal pixels and quadruple number of vertical pixels can be taken out at an output terminal 122 of the selector 74.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image information conversion device and an image display device suitable for use in, for example, a television receiver.

[0002]

2. Description of the Related Art There has been known an image processing apparatus which linearly interpolates an input image signal to double the number of pixels (the number of lines) in a vertical direction. Such an image processing apparatus can be applied to, for example, converting an interlace system to a progressive system. This conversion is performed to reduce line flicker caused by the interlace system. For example, in a graphics image, there is a problem that line flicker is conspicuous. When displaying a graphics image, the progressive system can achieve higher image quality than the interlace system.

A conventional image information conversion apparatus of this type performs a motion determination process on an input 525i signal (interlaced signal of 525 scanning lines), and performs inter-frame interpolation when there is no motion. If there is motion, intra-field interpolation is performed. The inter-field interpolation forms a signal of a new line using the signal of the line of the previous field, and the intra-field interpolation forms a signal of the new line by averaging the signals of the upper and lower lines of the same field.

[0004]

In the conventional image information conversion apparatus, since the positions of pixels formed by interpolation are fixed, in order to generate pixels at other spatiotemporal positions, the image information conversion apparatus meets the purpose. It is necessary to configure a dedicated device. Therefore, even if a plurality of conventional image information conversion devices are combined,
There is a problem that a function of generating a pixel at another spatiotemporal position cannot be realized. Therefore, when the conventional image information conversion device is designed as an LSI (Large Scale Integrated Circuit), the image information conversion function cannot be extended even if a plurality of LSIs are used.

[0005] Further, the conventional image information conversion apparatus merely performs vertical interpolation based on an input image signal, and therefore the resolution does not become higher than that of the base SD signal. Also, the line created with the average value has a problem that the difference in resolution between the existing line and the interpolation line is noticeable because the vertical resolution is deteriorated as compared with the existing line. Furthermore, when there is noise in the image signal, and when the average value of the upper and lower lines is used, random noise is added, and noise is reduced in the created line. As a result, the created line in which the noise has been reduced and the existing line in which the noise has been reduced appear alternately, and the image quality deteriorates. Further, there is a problem that when the interpolation method (still image processing and moving image processing) is switched based on the result of the motion detection, the image quality is greatly deteriorated when the motion detection is erroneous.

Accordingly, an object of the present invention is to provide an image information conversion device and an image display device capable of realizing a plurality of functions and preventing image quality deterioration.

[0007]

According to a first aspect of the present invention, there is provided an image information conversion apparatus for generating an output image signal having a larger number of pixels than the number of pixels of an input image signal. Generating a first output image signal in which the number of pixels in the horizontal direction is twice the number of input pixels in a first pixel position, and in a second pixel position vertically different from the first pixel position, A plurality of pixel generation devices for generating a second output image signal in which the number of pixels in the horizontal direction is twice the number of input pixels, and first and second pixels of the plurality of pixel generation devices, respectively.
, The third and fourth output image signals having the line frequency or the field frequency of the output image signal N times (N is an integer of 2 or more) are generated, and the third and fourth output image signals of the plurality of pixel generation devices are respectively generated. And an output processing device that generates an output image signal by selectively synthesizing the output image signals of the first and second pixel positions. The first and second signal generators respectively generate pixel values of the output image signal of the first and second pixels, and the first and second signal generators respectively surround the first and second pixel positions. A class determining unit that forms class information based on a plurality of first pixels of a located input image signal, and a prediction coefficient that is acquired in advance is stored for each class information, and the class information from the class determining unit is input. Be done By the above, a memory unit that outputs a prediction coefficient, a plurality of second pixels of an input image signal located around each of the first and second pixel positions, and a linear estimation expression of a prediction coefficient from the memory unit And a pixel value generation unit that generates pixels.

According to a fourth aspect of the present invention, in the image information conversion apparatus which generates an output image signal having a larger number of pixels than the number of pixels of the input image signal, the number of pixels in the horizontal direction is input to the first pixel position. A first output image signal having twice the number of pixels is generated, and the number of pixels in the horizontal direction is set to twice the number of input pixels at a second pixel position different from the first pixel position in the horizontal direction. The number of pixels in the horizontal direction is increased by selectively synthesizing a plurality of pixel generation devices for generating a second output image signal and the first and second output image signals of each of the plurality of pixel generation devices. An output processing device that generates an increased output image signal, wherein each of the plurality of pixel generation devices generates pixel values of the first and second output image signals at the first and second pixel positions, respectively. From the first and second signal generators , A first signal generator and a second signal generator each determine a class based on a plurality of first pixels of an input image signal located around each of the first and second pixel positions. Unit, a memory unit that stores a prediction coefficient obtained in advance for each class information, and outputs a prediction coefficient by inputting class information from the class determination unit, and a first and second pixel positions. An image information conversion apparatus comprising: a plurality of second pixels of an input image signal located around each of the pixels; and a pixel value generation unit configured to generate a pixel by a linear estimation expression of a prediction coefficient from a memory unit. It is.

According to a fifth aspect of the present invention, there is provided an image information converting apparatus for generating an output image signal having a larger number of pixels than the number of pixels of an input image signal. A first output image signal having twice the number of pixels is generated, and the number of pixels in the vertical direction is twice the number of input pixels in a second pixel position that is different from the first pixel position in the vertical direction. The number of pixels in the vertical direction is increased by selectively synthesizing a plurality of pixel generation devices for generating a second output image signal and the first and second output image signals of each of the plurality of pixel generation devices. An output processing device that generates an increased output image signal, wherein each of the plurality of pixel generation devices generates pixel values of the first and second output image signals at the first and second pixel positions, respectively. From the first and second signal generators , A first signal generator and a second signal generator each determine a class based on a plurality of first pixels of an input image signal located around each of the first and second pixel positions. Unit, a memory unit that stores a prediction coefficient obtained in advance for each class information, and outputs a prediction coefficient by inputting class information from the class determination unit, and a first and second pixel positions. An image information conversion apparatus comprising: a plurality of second pixels of an input image signal located around each of the pixels; and a pixel value generation unit configured to generate a pixel by a linear estimation expression of a prediction coefficient from a memory unit. It is.

According to a sixth aspect of the present invention, an image information conversion device is provided between an input image signal source and a display device, and the image information conversion device outputs an output image signal having a larger number of pixels than the input image signal. An image information conversion device configured to generate a first output image signal in which the number of pixels in the horizontal direction is twice the number of input pixels at a first pixel position, A plurality of pixel generators for generating a second output image signal in which the number of pixels in the horizontal direction is twice the number of input pixels at a second pixel position different in the vertical direction and a plurality of pixel generators Generating the third and fourth output image signals in which the line frequency or the field frequency of each of the first and second output image signals is N times (N is an integer of 2 or more), The third and fourth of the respective devices
And an output processing device that generates an output image signal by selectively synthesizing the first and second pixel positions of the first and second pixel positions. And first and second signal generators for respectively generating pixel values of the output image signal of the first and second pixel positions. Each of the first and second signal generators is located around each of the first and second pixel positions. A class determining unit that forms class information based on a plurality of first pixels of the input image signal to be stored, and a prediction coefficient that is obtained in advance is stored for each class information, and the class information from the class determining unit is input. A memory unit that outputs a prediction coefficient, a plurality of second pixels of an input image signal located around each of the first and second pixel positions, and a linear estimation expression of the prediction coefficient from the memory unit By An image display device characterized by having a pixel value generating unit that generates a pixel.

According to the image information conversion device of the first aspect, the image information conversion function can be extended by the number of pixel generation devices to be combined and the configuration of the output processing device. An input image signal, for example, a 525i signal can be converted to a 1050p signal, a 525i signal can be converted to a 2100i signal, and the field frequency can be doubled. Further, the pixels of the output image signal are generated by the classification adaptive processing. The class classification adaptive processing detects a class based on a plurality of pixels of an input image signal, and creates a pixel value of the output image signal using an estimated prediction formula that is optimal for each class. can do.
Since the image display device of the present invention has such an image information conversion device between the input image signal source and the display device, it is possible to display an image in which the number of pixels is increased as compared with the input image signal. .

According to a fourth aspect of the present invention, the number of pixels in the horizontal direction can be increased only by using a pixel generation device that forms an output image signal having an increased number of pixels only in the horizontal direction. According to the fifth aspect of the present invention, the number of pixels in only the vertical direction can be increased by using a pixel generation device that forms an output image signal in which the number of pixels is increased only in the vertical direction.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below. The pixel generation device used in this embodiment generates pixels by a class classification adaptive process. To facilitate understanding of the present invention, first, an example of a pixel generation device that doubles the number of pixels in the horizontal and vertical directions by class classification adaptive processing will be described.

The classification adaptive processing is different from the conventional processing for forming a high-resolution signal by interpolation processing. That is, the class classification adaptive processing has storage means for performing class division according to a three-dimensional (spatio-temporal) distribution of a video signal level as an input signal and storing a prediction coefficient value obtained by learning in advance for each class. This is a method of outputting an optimum estimated value by an operation based on a prediction formula, and the resolution can be increased to be higher than that of the input video signal by the class classification adaptive processing.

In one example of this pixel generating apparatus, as shown in FIG. 1, an input video signal (525i signal) is supplied to a region extracting section 1 and includes a plurality of pixels required for class classification and prediction calculation. The area is cut out. The output of the region cutout unit 1 is supplied to class detection circuits 2 and 12, and prediction tap selection circuits 3 and 13. The class detection circuits 2 and 12 detect a class corresponding to the level distribution pattern of the input pixels near the output pixel to be created. The class detection circuits 2 and 12 may detect a motion class. In this example, a first pixel position close to the line existing in the input image signal and a second pixel far from the line existing in the input image signal at a pixel position different from the first pixel position in the vertical direction. An output pixel is generated at each position. Therefore, a configuration for generating a pixel at the first pixel position M and a configuration for generating a pixel at the second pixel position S are provided in parallel.

The classes detected by the class detection circuits 2 and 12 are supplied to prediction tap selection circuits 3 and 13 and prediction coefficient memories 4 and 14, respectively. The prediction coefficients corresponding to the class are read from the prediction coefficient memories 4 and 14, and the read prediction coefficients are supplied to the product-sum operation circuits 5 and 15. The prediction tap selection circuits 3 and 13 are configured to select a prediction tap to be used according to a class. When the prediction coefficients of each class are obtained in advance by learning, both the prediction coefficients and the prediction tap position information to be used are obtained. The prediction tap selection circuits 3 and 13 are provided with memories in which prediction tap position information is stored for each class. The prediction tap position information read from the memory corresponding to the class is supplied to a tap switching selector, and the selector selectively outputs prediction taps. The prediction taps from the prediction tap selection circuits 3 and 13 are supplied to the product-sum operation circuits 5 and 15.

The product-sum operation circuits 5 and 15 calculate the data of the output video signal by using a linear estimation formula of the prediction tap (pixel of the 525i signal) and the prediction coefficient. Product-sum operation circuit 5
Is the pixel value at the first pixel position M (first output image signal)
Is output, and the product-sum operation circuit 15 outputs the pixel value (second output image signal) at the second pixel position S. At the same time, the product-sum operation circuits 5 and 15 output twice as many pixels in the horizontal direction. Line memories 6, 16 and selector 7 described later
The configuration for generating the first and second output image signals, such as the area cutout unit 101, is configured as the LSI 101, except for the output processing unit consisting of.

The pixel value at the first pixel position M from the product-sum operation circuit 5 is supplied to the line memory 6, and the product-sum operation circuit 15
Is supplied to the line memory 16 from the second pixel position S. The line memories 6 and 16 perform line double-speed processing, that is, line double-speed processing that doubles the line frequency. Outputs of the line memories 6 and 16 are input to a selector 7 that can be switched for each line. The selector 7 is
The outputs of the line memories 6 and 16 are alternately selected to generate an output video signal (a 525p signal or a 1050i signal).

FIG. 2 shows the line double speed processing using an analog waveform. The data of the pixel positions M and S are simultaneously generated by the product-sum operation circuits 5 and 15.
The data at the pixel position M includes a1, a2, a3,.
And the data at the pixel position S include b
1, b2, b3,... Are included. The line memories 6 and 16 store the data of each line by 1 /
2 and the compressed data is alternately selected by the selector 7 to provide line-sequential output (a0, b0,
a1, b1,...) are formed.

Although not shown, an output video signal is supplied to a CRT display. The synchronization system of the CRT display is configured so that an output video signal can be displayed. As the input video signal, a broadcast signal or a playback signal of a playback device such as a VTR is supplied. That is, this example can be incorporated in a television receiver.

FIG. 3 shows an arrangement of pixels of an input image signal (525i signal) and an output image signal by enlarging a part of an image of one field. The output image signal is, for example, a 525p signal. The pixel position M is set to the same position as a line existing in the input image signal, and the pixel position S is set to an intermediate position between lines existing in the input image signal. In FIG. 3, a large dot is a pixel of the 525i signal, a pixel at a pixel position M at which a small black dot is output, and a pixel position S at which a small white dot is output.
Pixel. This relationship is the same in other drawings other than FIG.

FIG. 3A shows a pixel arrangement in an odd field of a certain frame (F), and FIG. 3B shows a pixel arrangement in another field (even field). In the other fields (even fields), the lines of the 525i signal are spatially shifted by 0.5 lines. As can be seen from FIG. 3, the pixel position M at the same position as the line of the 525i signal
And 525i signal, a pixel value is formed at an intermediate pixel position S between the upper and lower lines, and the number of pixels in each line in the horizontal direction is doubled. Therefore, the product-sum operation circuit 5,
By means of 15, data of four pixels of the 525p signal are simultaneously generated.

The output image signal (525p
A specific example of the class tap used in the class detection circuits 2 and 12 and the prediction tap selected in the prediction tap selection circuits 3 and 13 when forming the signal) will be described. 4 and 5 show the class detection circuits 2, 1
2 shows an example of a space class tap used in 2.
4 and 5 show the odd field o (denoted as F-1 / o) of the temporally continuous frame F-1, the even field (F-1 / e) of F-1, F / o, F / E shows an arrangement of pixels in the vertical direction.

As shown in FIG. 4, the space class tap for predicting the pixel values of the pixel positions M and S of the field F / o is the field F / e following the field F / o.
, Input pixels T1 and T2 spatially adjacent to the pixel of the 525p signal to be created, and the field F / o
And input pixels T3, T4, and T5 near the pixel of the 525p signal to be created, and input pixels T6 and T7 of the previous field F-1 / e. When predicting the pixel values of the pixel positions M and S of the field F / e, as shown in FIG. 5, the pixels and the space of the 525p signal included in the field F / o next to the field F / e to be created are to be created. Input pixels T1 and T2 at near positions, input pixels T3, T4, and T5 included in the field F / e and near the pixel of the 525p signal to be created, and input pixels T6 and T6 of the previous field F / o. T7. Note that when predicting the pixel value at the pixel position M, the pixel at T7 may not be selected as a class tap, and when predicting the pixel value at the pixel position S, the pixel at T4 may not be selected as a class tap. Further, a plurality of input pixels in the horizontal direction may be used as the space class tap.

The class detection circuits 2 and 12 detect the level distribution pattern of the space class tap. In this case, in order to prevent the number of classes from becoming enormous, processing is performed to compress the input data of 8 bits for each pixel into data having a smaller number of bits. As an example, ADRC (Adaptive D
The dynamic range coding compresses the data of the input pixel of the space class tap. As information compression means, DPCM (prediction coding), VQ
A compression means such as (vector quantization) may be used.

Originally, ADRC is a VTR (Video Tape R)
ecoder) is an adaptive requantization method developed for high-efficiency coding. However, since a local pattern of a signal level can be efficiently represented by a short word length, in this example, ADRC is used.
Is used to generate codes for spatial class classification. ADR
C is the dynamic range of the spatial class tap DR,
Assuming that the bit allocation is n, the data level of the pixel of the space class tap is L, and the requantization code is Q, a value between the maximum value MAX and the minimum value MIN is equalized by the specified bit length by the following equation (1). And requantization is performed.

DR = MAX−MIN + 1 Q = {(L−MIN + 0.5) × 2 / DR} (1) where {} indicates a truncation process.

It should be noted that the motion class may be used together, and the space class and the motion class may be integrated to detect the class. In this case, the space class tap may be switched according to the motion class. Description of a specific example of the prediction tap will be omitted. The prediction tap is the same as the above-described space class tap, but is selected based on prediction tap position information corresponding to the class in order to improve prediction accuracy.

In the prediction coefficient memories 4 and 14, the prediction coefficients obtained by learning the relationship between the pattern of the 525i signal and the 525p signal are stored for each class. The prediction coefficient is obtained by converting the 525i signal into 52
This is information for converting to a 5p signal. The method for obtaining the prediction coefficient will be described later.

The prediction coefficient of the class is read from the address corresponding to the class in the prediction coefficient memories 4 and 14.
This prediction coefficient is supplied to the product-sum operation circuits 5 and 15.
Product-sum operation circuit 5, the prediction taps (pixel values) from the prediction tap selection circuit 3, 13 T1, T2, and · · · Ti, prediction coefficients w _1, w _2, linear combination of · · · wi The pixel value at the pixel position M is calculated by performing the operation of Expression (Expression (2)). The product-sum operation circuit 15 similarly calculates the pixel value at the pixel position S. However, different prediction coefficients are used between the pixel positions M and S.

L1 = w ₁ T1 + w ₂ T2 +... + WiTi (2) As described above, the prediction coefficients are obtained in advance for each class by learning, and are stored in the prediction coefficient memories 4 and 14. An operation is performed based on the input prediction taps and the read prediction coefficients, and output data corresponding to the input data is formed and output. It is possible to output a progressive video signal of image quality.

Next, creation (learning) of prediction coefficients will be described with reference to FIG. In order to obtain the prediction coefficients by learning, first, an interlaced video signal (for example, a 525i signal) in which the number of pixels in each of the horizontal direction and the vertical direction is reduced to か ら by a decimation filter 31 from a progressive signal (for example, a 525p signal) To form The input video signal and the output video signal of the thinning filter 31 are used as a learning pair.

FIG. 7 shows the spatial relationship of pixels between the input signal (progressive image) of the thinning filter 31 and its output signal (interlace image). The even-numbered lines of the image of the odd-numbered field of the progressive image are thinned out, and the pixels of the odd-numbered lines are alternately thinned in the horizontal direction. In the even-numbered fields of the progressive image, odd-numbered lines are thinned out, and in the even-numbered lines, the number of pixels is alternately thinned out in the horizontal direction. By changing the characteristics of the thinning filter 31, the characteristics of the learning can be changed, and thereby the image quality of the image obtained by the conversion can be controlled.

The interlaced video signal from the thinning filter 31 is supplied to a prediction tap area cutout section 32 and a class tap area cutout section 33. The class tap from the class tap area cutout unit 33 is supplied to the class detection circuits 34 and 35. The prediction tap region cutout unit 32 outputs a prediction tap for creating each of the pixel positions M and S. The class detection circuits 34 and 35
The class detection circuits 2, 1 in the signal conversion device shown in FIG.
Similarly to 2, the data of the spatial class tap is compressed by ADRC to generate class information. Class detection circuit 3
4 and 35 independently detect the class for each of the pixel positions M and S.

The prediction taps from the prediction tap area cutout unit 32 are supplied to normal equation addition circuits 36 and 37.
For explanation of the normal equation adding circuits 36 and 37, learning of a conversion formula from a plurality of input pixels to output pixels and signal conversion using the prediction formula will be described. Hereinafter, for the sake of explanation, a more generalized case of performing prediction using n pixels will be described. X ₁ the level of the input pixels selected as prediction taps, respectively, ‥‥, and x _n, when the output pixel level and y, the prediction for each class coefficients w _1, ‥‥, w _n
Is set as an n-tap linear estimation equation. This is shown in the following equation (3). Learning ago, w _i is undetermined coefficients.

Y = w ₁ x ₁ + w ₂ x ₂ + ‥‥ + w _n x _n (3) Learning is performed on a plurality of signal data for each class. When the number of data is m, the following equation (4) is set according to the equation (3).

Y _k = w ₁ x _k1 + w ₂ x _k2 + ‥‥ + w _n x _kn (4) (k = 1,2, ‥‥ m) When m> n, the prediction coefficients w _i and ‥‥ w _n Is not uniquely determined, the element of the error vector e is defined by the following equation (5), and a prediction coefficient that minimizes the equation (6) is obtained. This is a so-called least squares solution.

[0038] _{e k = y k - {w} 1 x k1 + w 2 x k2 + ‥‥ + w n x kn} (5) (k = 1,2, ‥‥ m)

[0039]

(Equation 1)

Here, the partial differential coefficient based on w _{i in} equation (6) is obtained. What is necessary is just to find each coefficient w _i so that the following equation (7) is set to `0`.

[0041]

(Equation 2)

Hereinafter, X _ij , Y as in equations (8) and (9)
_{When i} is defined, equation (7) is obtained by using equation (10) using a matrix.
Is rewritten to

[0043]

(Equation 3)

[0044]

(Equation 4)

[0045]

(Equation 5)

This equation is generally called a normal equation. Each of the normal equation addition circuits 36 and 37 in FIG. 6 attempts to create the class information supplied from the class detection circuits 34 and 35 and the two sets of prediction taps supplied from the prediction tap area cutout unit 32. The normal equation is added using the pixels (teacher signal) of the progressive image.

After the input of data of a sufficient number of frames for learning is completed, the normal equation adding circuits 36 and 37 output normal equation data to the prediction coefficient determining section 38. The prediction coefficient determination unit 38 solves w _i using a general matrix solution such as a sweeping method of a normal equation, and calculates a prediction coefficient. The prediction coefficient determination unit 38 writes the calculated prediction coefficients into the prediction coefficient memories 39 and 40.

As a result of the learning as described above, in each of the prediction coefficient memories 39 and 40, an estimate statistically closest to the true value for estimating the target pixel y of the progressive image is estimated for each class. The possible prediction coefficients are stored. The prediction coefficients stored in the prediction coefficient memories 39 and 40 are stored in the prediction coefficient memories 4 and
14 is loaded.

The number of prediction taps output by the prediction tap area cutout unit 32 is larger than the number of prediction taps used in the pixel generation device. Therefore, the prediction coefficient determination unit 38 obtains more prediction coefficients for each class. From the obtained prediction coefficients, the prediction coefficients of the number to be used are selected in ascending order of the absolute value. The selected prediction coefficients are stored at addresses corresponding to the classes in the memories 39 and 40, respectively. Therefore, a prediction tap is selected for each class, and the selected position information of the prediction tap is stored in a memory (not shown) for each class.
Is stored in By such a prediction tap selection process, it is possible to select a prediction tap suitable for each class.

With the above processing, the learning of the prediction coefficient for creating the progressive image data from the interlaced image data is completed by the linear estimation formula.

The pixel generating apparatus described above creates pixels of an output image signal at a first pixel position M and a second pixel position S which are different from each other in the vertical direction, and simultaneously creates a pixel in the horizontal direction at each pixel position. A pixel having twice the number of pixels is created. Therefore, the number of pixels can be doubled in the vertical and horizontal directions. In FIG. 1, portions other than the line memories 6 and 16 and the selector 7 are realized as an LSI 101.

That is, the device shown in FIG. 1 can be represented as a block diagram shown in FIG. In FIG. 8, 1
Reference numeral 11 denotes an input terminal to which an input SD signal is supplied;
Reference numeral 1 denotes an output terminal from which an output image signal whose number of pixels is doubled in the vertical and horizontal directions is extracted. A relatively large-capacity memory, such as a line memory and a field memory, required by the area extracting circuit 1 is externally connected to the LSI 101.

As described above, the configurations shown in FIGS. 1 and 8 can generate the pixels of the output image signal at the pixel positions shown in FIGS. 9, 10, 11, and 12. FIG.
Indicates the pixel position of the input image signal (525i signal) and the pixel position of the output image signal (525p signal) in the vertical and horizontal directions. 9A and 9B are:
The positional relationship between two temporally consecutive fields is shown. FIG. 10 shows the pixel position of the input image signal (525i signal) and the pixel position of the output image signal (525p signal) in the vertical direction and the time direction.

FIG. 11 shows an input image signal (525i signal).
And the pixel position of the output image signal (1050i signal) in the vertical direction and the time direction. FIG. 11A and FIG.
Indicates the positional relationship between the fields. FIG. 12 shows the pixel position of the input image signal (525i signal) and the output image signal (105i).
0i signal) in the vertical direction and the time direction.

In the present invention, the function of image information conversion is changed and extended by using a plurality of LSIs 101 and changing the configuration of an output processing circuit connected thereafter. Hereinafter, a first embodiment of the present invention will be described with reference to FIG. In the first embodiment, two LSIs 101A and 101B are used.
Line memories 6A and 16A for LSI 101A
Is connected to the line memory 6B for the LSI 101B.
And 16B are connected.

The LSI 101A has pixel positions M-1 and S
−1, and the LSI 101B generates output pixels at pixel positions M-2 and S-2, respectively.
These pixel positions are different from each other in the vertical direction. The LSIs 101A and 101B correspond to the LSI 1 described above.
01 has the same configuration as that of FIG. However, the settings of the prediction taps and the class taps and the coefficients stored in the prediction coefficient memory are optimal in correspondence with the pixel position of the output pixel generated by each.

Output image signals of M-1 and S-1 at pixel position 1B of LSI 101A are supplied to line memories 6A and 16A. Line memories 6A and 16
A generates an output with the line frequency quadrupled. For example, the line frequency is quadrupled by writing one line of data and reading it out at four times the speed. In addition, LSI
The output image signals of M-2 and S-2 at the pixel position 1B of 101B are supplied to the line memories 6B and 16B. The line memories 6B and 16B generate outputs whose line frequency is quadrupled. 4 line memories 6
A, 16A, 6B and 16B output data from selector 7A
Is input to The selector 7A selects the output of each line memory in order of M-1, M-2, S-1, and S-2 for each quadruple line cycle and outputs the output to the output terminal 122.

According to the first embodiment, the line memory 6
A, 16A, 6B, and 16B make the line frequency 4
Therefore, the progressive signal (105) in which the number of vertical pixels (the number of lines) is twice as large as that of the input signal (525i signal).
0p signal) or an interlace signal (2100i signal) in which the number of vertical pixels is four times the input signal.

FIG. 14 shows an example of the positional relationship between an input pixel and an output pixel expressed in the vertical direction and the time direction. LSI1
01A selects a class tap and a prediction tap from the input image signal (525i signal), and performs a product-sum operation of the pixel value of the prediction tap and the prediction coefficient, and in the vertical direction, at an interval of half the original line interval, and Pixel values are generated at twice the pixel positions M-1 and S-1 in the horizontal direction. L of the other
The SI 101B generates pixel values at pixel positions M-1 and S-1 and intermediate pixel positions M-1 and S-1 in the vertical direction, respectively. In both the odd field and the even field, the vertical positions of the generated pixels are the same. Therefore, the output image signal is a progressive scanning signal (1050p signal) in which the number of lines is doubled.

The pixel positions M-1 and S-1 of the pixel generated by the LSI 101A and the pixel positions M-2 and S-2 of the pixel generated by the LSI 101B are, as shown in FIG. Thus, by shifting in the vertical direction, an output image signal of an interlace system, that is, a 2100i signal can be generated.

The pixel generating apparatus shown in FIG. 1 can generate a field doubled output signal by providing a field memory in the output processing section. That is, as shown in FIG. 16, the output image signals of the pixel positions M and S of the LSI 101 are written into the field memories 131 and 132, and the field memories 131 and 1 are written.
32 is read out at a frequency twice as high as the original field frequency, and the selector 7B selects the read-out output of the field memories 131 and 132 to obtain a field double speed signal whose field frequency is doubled at the output terminal 123. be able to.

The selection operation of the selector 7B is switched at twice the field frequency (60 × 2 = 120 Hz).
That is, when a field including the pixel position M generated from the A field is selected, next, the pixel at the pixel position S generated from the A field is selected, and then the pixel at the pixel position S generated from the B field is selected. Select, then B
A field consisting of pixel positions M generated from the field is selected. Therefore, as shown in FIG. 17, the output image signal is obtained by doubling the field frequency of the input image signal (525i signal / 60 Hz) (525i signal / 12 Hz).
0 Hz). As can be seen from FIG. 17, since the pixel positions M and S of the A field and the pixel positions M and S of the B field are different in space-time arrangement, different coefficients may be used for the A field and the B field. is necessary.

As shown in FIG. 18, according to the second embodiment of the present invention, a line doubling process using a line memory is performed.
The output processing unit has both the field doubling processing by the field memory.

In the second embodiment, two LSIs 101
A and 101B are used. LSI 101A and 1
01B is supplied with input image signals from input terminals 111A and 111B. This input image signal is the same signal. Output of LSI 101A (M-1 and S-
Field memories 131A and 132A are connected to 1), respectively.
Are connected to line memories 6C and 16C, respectively. Similarly, the output of the LSI 101B (M-2 and S
-2) are connected to the field memories 131B and 132B, respectively.
Are connected to line memories 6D and 16D, respectively.

As described above, the field memories 131A to 132B perform the field doubling process, and the line memories 6C to 16D perform the line doubling process. Each output data of the line memories 6C and 16C is input to the selector 7C, and each output data of the line memories 6D and 16D is input to the selector 7D. Selectors 7C and 7D are controlled at twice the line frequency. Further, the outputs of the selectors 7C and 7D are input to the selector 7E,
The output data of E is taken out to the output terminal 124. The selector 7E is controlled at twice the field frequency.

FIG. 19 shows the output image signal generated by the configuration of FIG. 18 in the vertical direction and the time direction. The selector 7C doubles the field frequency,
The pixels at the pixel positions M-1 and S-1 are selected. Selector 7
D has the field frequency doubled and selects the pixels at pixel positions M-2 and S-2. The selector 7E outputs the output (M) of the selector 7C at the timing of the original field in time.
-1 and S-1) and select 1/120 of the original field.
The output (M-2 and S-2) of the selector 7D is selected at a timing after seconds. Thereby, as shown in FIG. 19, an output image signal (1050p / 120Hz) having twice the number of vertical pixels and twice the field frequency can be formed. Similarly, (1050i / 120Hz) can also be formed. It should be noted that the number of horizontal pixels is twice as large as in the first embodiment described above.

In the above-described embodiment, one pixel generation device doubles both the number of vertical pixels and the number of horizontal pixels. However, the pixel generation device that doubles the number of pixels only in the vertical direction or only in the horizontal direction is used. By combining two LSIs of the device, the number of pixels only in the vertical direction or only in the horizontal direction can be quadrupled.

The above-described embodiment of the present invention can be implemented by, for example,
By providing between a display device such as a T display and an input signal source, an image having a higher resolution than the resolution of the input signal source can be displayed.

[0069]

According to the present invention, an original input image signal can be obtained by combining a plurality of pixel generating devices having a function of doubling the number of vertical pixels and performing a line double speed and / or a field double speed in an output processing unit. , Various output image signals having a higher resolution can be generated. Further, since the pixel generation device generates pixels by the class classification adaptive processing, the resolution can be increased more than the input, unlike the linear interpolation, and both the still image and the moving image can have high image quality. .

[Brief description of the drawings]

FIG. 1 is a block diagram of an example of a pixel generation device used in the present invention.

FIG. 2 is a waveform chart for explaining a line-sequential conversion operation.

FIG. 3 is a schematic diagram illustrating a positional relationship between pixels of an input image and pixels of an output image in an example of a pixel generation device.

FIG. 4 is a schematic diagram illustrating a positional relationship between an input pixel and an output pixel and an example of a space class tap.

FIG. 5 is a schematic diagram illustrating an example of a positional relationship between an input pixel and an output pixel and a space class tap.

FIG. 6 is a block diagram illustrating an example of a configuration at the time of learning for acquiring a prediction coefficient.

FIG. 7 is a schematic diagram for explaining pixel thinning processing during learning.

FIG. 8 is a block diagram of an overall configuration of a pixel generation device.

FIG. 9 is a schematic diagram illustrating an example of a positional relationship between pixels of an input image and pixels of an output image.

FIG. 10 is a schematic diagram illustrating an example of a positional relationship between pixels of an input image and pixels of an output image.

FIG. 11 is a schematic diagram for explaining another example of the positional relationship between the pixels of the input image and the pixels of the output image.

FIG. 12 is a schematic diagram illustrating another example of the positional relationship between the pixels of the input image and the pixels of the output image.

FIG. 13 is a block diagram of the first embodiment of the present invention.

FIG. 14 is a schematic diagram illustrating an example of a positional relationship between pixels of an input image and pixels of an output image according to the first embodiment of the present invention.

FIG. 15 is a schematic diagram for explaining another example of the positional relationship between the pixels of the input image and the pixels of the output image according to the first embodiment of the present invention.

FIG. 16 is a block diagram of a pixel generation device used in a second embodiment of the present invention.

FIG. 17 is a schematic diagram illustrating an example of a positional relationship between pixels of an input image and pixels of an output image.

FIG. 18 is a block diagram of a second embodiment of the present invention.

FIG. 19 is a schematic diagram illustrating an example of a positional relationship between pixels of an input image and pixels of an output image according to the second embodiment of the present invention.

[Explanation of symbols]

2, 12: class detection circuit, 3, 13: prediction tap selection circuit, 4, 14: prediction coefficient memory, 5, 1
5... Product-sum operation circuit, 101, 101A, 101B
..LSI of pixel generation device, 6, 6A-6D, 16A-
16D: line memory, 7, 7A to 7E: selector, 131, 131A, 131B, 132, 132
A, 132B ... field memory

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Nobuyuki Asakura, Inventor 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (72) Inventor Masashi Uchida 6-35, Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (72) Inventor Takuo Morimura 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation (72) Inventor Kazutaka Ando 6-35, Kita-Shinagawa, Shinagawa-ku, Tokyo Soni -Inside the Corporation (72) Hideo Nakaya, Inventor 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation Inside (72) Inventor Tsutomu Watanabe 6-35, 7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Soni Inside (72) Inventor Ken Ken Inoue 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation (72) Inventor Wataru Niizuma 6-35, Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation Inside Term (Reference) 5C059 KK00 LA06 LB15 LB18 MA19 MA28 SS05 TA08 TA29 TA58 TA69 TB08 TB14 TC02 TC12 TD13 TD14 TD15 UA33 5C063 AA01 BA04 BA09 CA01 CA05 CA07 CA11 CA34

Claims (11)

[Claims] 1. An image information conversion apparatus which generates an output image signal having a larger number of pixels than the number of pixels of an input image signal, wherein the number of pixels in the horizontal direction is 2 at the first pixel position.
A first output image signal that is doubled is generated, and a second pixel position in the second pixel position that is different from the first pixel position in the vertical direction has a horizontal pixel number twice the input pixel number. A plurality of pixel generation devices for generating an output image signal; and a line frequency or a field frequency of each of the first and second output image signals of each of the plurality of pixel generation devices is N times (N is 2 or more). Integers) are generated, and the third and fourth output image signals of the plurality of pixel generation devices are selectively combined to generate an output image signal. An output processing device that generates the pixel values of the first and second output image signals at the first and second pixel positions, respectively. From the second signal generator The each of the first and second signal generating unit, based on the plurality of first pixel of the input image signal located around each of the first and second pixel positions,
A class determination unit that forms class information; and a prediction coefficient that is obtained in advance is stored for each class information;
A memory unit that outputs a prediction coefficient when the class information is input from the class determination unit; and a plurality of second image signals of an input image signal located around each of the first and second pixel positions. An image information conversion device comprising: a pixel; and a pixel value generation unit that generates a pixel by a linear estimation expression of a prediction coefficient from the memory unit. 2. The device according to claim 1, further comprising a first and a second pixel generation device, wherein the output processing device is supplied with the first and second output image signals of the first pixel generation device. A first and a second line memory for respectively outputting an output image signal whose line frequency is quadrupled, and the first and second output image signals of the second pixel generation device are supplied. A third and a fourth line memory for respectively outputting an output image signal quadrupled, and a selection for sequentially selecting the output image signals of the first, second, third and fourth line memories for each line Means for forming an output image signal having twice the number of pixels in the horizontal direction and four times the number of pixels in the vertical direction by the selection means. 3. The device according to claim 1, further comprising a first and a second pixel generation device, wherein the output processing device is supplied with the first and second output image signals of the first pixel generation device. A first and a second field memory for respectively outputting an output image signal whose field frequency is doubled, and a first selection for sequentially selecting the output image signals of the first and the second field memories line by line. Means, and third and fourth field memories to which the first and second output image signals of the second pixel generation device are supplied and output the output image signals whose field frequency is doubled, respectively. Second selecting means for sequentially selecting the output image signals of the third and fourth field memories line by line;
And a third selecting means for selecting an output of the selecting means for each field. From the third selecting means, the number of pixels in the horizontal direction is twice,
An image information conversion apparatus characterized in that an output image signal is formed which has four times the number of pixels in the vertical direction and has twice the field frequency. 4. An image information conversion apparatus which generates an output image signal having a larger number of pixels than the number of pixels of an input image signal, wherein the number of pixels in the horizontal direction is 2 at the first pixel position.
A first output image signal that is doubled is generated, and a second pixel position in the horizontal direction that is different from the first pixel position in the horizontal direction has a second pixel number in the horizontal direction that is twice the number of input pixels. A plurality of pixel generating devices for generating an output image signal; and selectively synthesizing the first and second output image signals of each of the plurality of pixel generating devices.
An output processing device that generates an output image signal having a larger number of pixels in the horizontal direction, wherein each of the plurality of pixel generation devices has the first and second pixel positions at the first and second pixel positions. The first and second signal generators each generate a pixel value of an output image signal, and each of the first and second signal generators is located around each of the first and second pixel positions. Based on the plurality of first pixels of the input image signal located
A class determination unit that forms class information; and a prediction coefficient that is obtained in advance is stored for each class information;
A memory unit that outputs a prediction coefficient when the class information is input from the class determination unit; and a plurality of second image signals of an input image signal located around each of the first and second pixel positions. An image information conversion device comprising: a pixel; and a pixel value generation unit that generates a pixel by a linear estimation expression of a prediction coefficient from the memory unit. 5. An image information conversion apparatus which generates an output image signal having a larger number of pixels than the number of pixels of an input image signal, wherein the number of pixels in the vertical direction is two at the first pixel position.
A first output image signal that is doubled is generated, and a second pixel position in the vertical direction that is different from the first pixel position in the vertical direction is set to a second pixel number that is twice the number of input pixels in the vertical direction. A plurality of pixel generating devices for generating an output image signal; and selectively synthesizing the first and second output image signals of each of the plurality of pixel generating devices.
An output processing device that generates an output image signal having a larger number of pixels in the vertical direction, wherein each of the plurality of pixel generation devices includes the first and second pixel positions at the first and second pixel positions. The first and second signal generators each generate a pixel value of an output image signal, and each of the first and second signal generators is located around each of the first and second pixel positions. Based on the plurality of first pixels of the input image signal located
A class determination unit that forms class information; and a prediction coefficient that is obtained in advance is stored for each class information;
A memory unit that outputs a prediction coefficient when the class information is input from the class determination unit; and a plurality of second image signals of an input image signal located around each of the first and second pixel positions. An image information conversion device comprising: a pixel; and a pixel value generation unit that generates a pixel by a linear estimation expression of a prediction coefficient from the memory unit. 6. An image information conversion device is provided between an input image signal source and a display device, wherein the image information conversion device generates an output image signal having a larger number of pixels than the number of pixels of the input image signal. An image information conversion device according to claim 1, wherein the number of pixels in the horizontal direction is equal to two of the number of input pixels at the first pixel position.
A first output image signal that is doubled is generated, and a second pixel position in the second pixel position that is different from the first pixel position in the vertical direction has a horizontal pixel number twice the input pixel number. A plurality of pixel generation devices for generating an output image signal; and a line frequency or a field frequency of each of the first and second output image signals of each of the plurality of pixel generation devices is N times (N is 2 or more). Integers) are generated, and the third and fourth output image signals of the plurality of pixel generation devices are selectively combined to generate an output image signal. An output processing device that generates the pixel values of the first and second output image signals at the first and second pixel positions, respectively. From the second signal generator The each of the first and second signal generating unit, based on the plurality of first pixel of the input image signal located around each of the first and second pixel positions,
A class determination unit that forms class information; and a prediction coefficient that is obtained in advance is stored for each class information;
A memory unit that outputs a prediction coefficient when the class information is input from the class determination unit; and a plurality of second image signals of an input image signal located around each of the first and second pixel positions. An image display device comprising: a pixel; and a pixel value generation unit that generates a pixel by a linear estimation expression of a prediction coefficient from the memory unit. 7. The apparatus according to claim 1, wherein the first pixel position is closer to a pixel position of an input image signal than the second pixel position. 8. The method according to claim 1, wherein, when the pixel is generated by the linear estimation formula, an error between a generated value and a true value of the pixel is minimized. An apparatus for determining the class information by learning in advance for each of the class information. 9. The device according to claim 1, wherein each of the plurality of pixel generation devices generates an interlace signal. 10. The device according to claim 1, wherein each of the plurality of pixel generation devices generates a progressive signal. 11. The device according to claim 1, wherein each of the plurality of pixel generation devices has a configuration of a one-chip integrated circuit.