JP2000131387A - Semiconductor-testing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make to data width correspond to accessing memory which is provided in a DUT for storing into a fail bit memory by successively receiving a fail signal, where a lower bit corresponding to a bit width outputted by a device (the DUT) to be tested is divided, and by performing specific shift conversion. SOLUTION: Serially outputting signals C100s which are divided into Q times by a DUT are supplied to a fail signal selection control part 10 from a pattern generator. A multiplexer 20 of a shift conversion means successively receives fail signals FD1-FDm which are divided into Q times of a lower M bit, corresponding to a bit width M being outputted by the DUT in the fail signals FD 1-FDn with on n-bit width from a logic comparator. Then, to the bit position corresponding to the P-bit parallel data width inside the DUT, the fail signals FD1-FDm of the lower M bits are subjected to shift conversion as prescribed, and conversion fail signals MFD1-MFDn are supplied to corresponding fail bit memories FM1-FMn.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test apparatus for facilitating fail analysis of a device under test in which the input / output mode of the device is serial transfer.

[0002]

2. Description of the Related Art First, as a specific example of a device under test (DUT), as shown in a timing chart of a serial transfer type device in FIG.
A memory device that performs a write / read operation by giving a continuous control sequence to a serial I / O terminal starting from a start signal Start (see FIG. 5B) will be described below. The DUT is assumed to have a 16-bit data unit for accessing the internal memory, a 4-bit serial output bit width, and a device that inputs and outputs four consecutive sequences.

A continuous control sequence at the time of writing is 2
Cycle commands cmd1, cmd2 (see FIG. 5E)
And 4-cycle serial addresses adr1 to adr4
(See FIG. 5F) and the 4-cycle serial data Di1
To Di4 (see FIG. 5G). In this case, the data width of the supplied address signal and the data width of the write data are both 16 bits. A continuous control sequence at the time of reading includes a command of two cycles, a serial address of four cycles, and a DUT after that.
Is a serial transfer of four cycles of serial data Do1 to Do4 output in synchronism with the clock.

Next, the configuration of the main part of the semiconductor test apparatus will be described with reference to FIG. Since the semiconductor test apparatus is well-known and well-known in the art, detailed description of the entire system is omitted. The main configuration is a pattern generator (PG) 100
, A waveform shaper (FC), a logical comparator (DC), and a fail memory (FM). The timing generator supplies various clocks at predetermined timings to the respective units. P
The main signals generated by G100 include an address signal, a write data signal, a control signal, and an expected value. Note that the address signal A100s is output from the DU via the FC.
It is supplied to T and also to FM, so that both address information is the same address information. In DC, fail signals FD1 to FDn obtained by comparing the signal output from the DUT with the expected value supplied from the PG 100 and determining whether the signal is good or not.
To the FM. The FM is provided with a memory for fail storage corresponding to the address space of the DUT, and it is required that the FM be stored at an address in the FM corresponding to the fail address of the DUT. As a result, as a result of performing the device test, referring to the contents of the memory for storing the fail in the FM, it is possible to perform a fail analysis on which address position and which data bit position of the DUT has failed.

Next, FIG. 4 shows a main configuration of the FM according to the present invention.
Will be described further. The internal configuration of the main part of the FM according to the present invention includes an address MUX unit 50, n-channel fail bit memories FM1 to FMn, and WE control units WE1 to WEn. The number of channels n is D
It has the maximum data width of the UT, and has, for example, an n = 36 bit width to correspond to a device having a parity bit. Further, a semiconductor test apparatus capable of simultaneously measuring a plurality of DUTs has 32 systems corresponding to the number of simultaneous measurements, for example, 32 simultaneous measurements. The internal configuration will be described.

The address MUX unit 50 receives the address signal A100s from the PG 100 and supplies the address signal 50adr to the address input terminals (Ain) of all the fail bit memories FM1 to FMn at the time of device testing. At the time of the fail analysis, a desired address of the fail bit memories FM1 to FMn is accessed and read by the address supplied from the tester bus.

Fail signals FD1 to FDn from DC
Is a signal level of "H" when a failure is detected, and a fail bit memory FM1 corresponding to each bit is provided.
To FMn and the corresponding WE control units WE1 to WEn.

The WE control units WE1 to WEn generate and supply a write signal (/ WE) to the fail bit memories FM1 to FMn corresponding only to the cycle in which a failure has occurred.

The fail bit memories FM1 to FMn are:
A 1-bit width memory having at least the same address space as the DUT, and the WE control units WE1 to WE
The fail information is stored in the address position corresponding to the DUT by the write signal (/ WE) from En. As a result,
All the generated fail information is accumulated and stored.

In the above-described internal configuration of the conventional FM shown in FIG. 4, a serial I / O type DU as shown in FIG.
There is a drawback in that, upon receiving a fail signal due to T, the DUT cannot store the data at the address position in the FM corresponding to the address position where the failure has occurred. The reason is that, for the same address signal 50adr, for example, the fail signal FD1 is input to the fail bit memory FM1 in four cycles. As a result, when the bits of the 16-bit data of the memory in the DUT are bits 1, 2, 3,..., Bits 1, 5, 9, and 13 are input to fail bit memory FM1 in four cycles. Would. Therefore,
Bits 1, 5, 9, and 13 are OR-added and stored. The other fail bit memories FM2, FM3, FM4 are similarly OR-added and stored.

[0011]

As described above, in the conventional FM, a serial I / O device is not stored in a memory in the FM corresponding to the internal data width of the DUT on a 1: 1 basis. There are difficulties. As a result, normal failure analysis cannot be performed. In this respect, there is an unfavorable practical problem. Accordingly, an object of the present invention is to provide a semiconductor test apparatus capable of storing data in a fail storage memory in an FM corresponding to a data width to access a memory provided in the DUT.

[0012]

First, in order to solve the above-mentioned problems, according to the configuration of the present invention, fail signals FD1 to FDn having an n-bit width are received from a logical comparator (DC), N-bit fail bit storage means (fail bit memories FM1 to FMn and W
E control units WE1 to WEn) are provided in the fail memory device. On the other hand, the device under test has a P-bit data width for accessing the memory provided therein.
This is an output mode in which when outputting parallel data having a bit width, it is divided into Q times with M bit width and serially output.
In the semiconductor test apparatus for testing the device, the DUT divides the signal into Q times, supplies a serial output signal C100s indicating that serial output is being performed from a pattern generator, receives the serial output signal C100s, and performs the logical comparison. -Bit width fail signals FD1 to FD from devices
n fail signals FD1 to FD1 divided into Q times of lower M bits corresponding to the bit width M output by the DUT in n
FDm are sequentially received, and the lower M-bit fail signals FD1 to FDm are shift-converted to a predetermined bit position corresponding to the P-bit parallel data width in the DUT. The semiconductor test apparatus is provided with shift conversion means for supplying to n-channel fail bit storage means. According to the above invention, the DU is changed with respect to the data width P for accessing the memory provided in the DUT.
Even for a DUT in an output form in which the data is divided into a plurality of serial data and output when the data is output from T to the outside, the data width P of the internal memory of the DUT is made to correspond to 1: 1 to store the fail in the FM. A semiconductor test device that can be stored in a memory can be realized.

FIG. 1 and FIG. 2 show a solution according to the present invention. Second, in order to solve the above problem, in the configuration of the present invention, the fail signals FD1 to FD1
Dn received from the logical comparator, and n-channel fail bit storage means (fail bit memories FM1 to FMn and WE control unit WE1) corresponding to the n bit width.
To WEn) in the fail memory device, while the device under test has a P-bit data width for accessing the internal memory, and outputs M-bit Q data when outputting the P-bit parallel data. In a semiconductor test apparatus for testing the device, the serial output signal C100s indicating that the DUT is divided into Q times and serial output is being performed.
From the pattern generator, receives the serial output in-progress signal C100s, and outputs Q times of lower M bits corresponding to the bit width M output by the DUT in the n-bit width fail signals FD1 to FDn from the logical comparator. Sequentially receive the fail signals FD1 to FDm divided into
The lower M-bit fail signals FD1 to FDm are shifted to bit positions corresponding to the internal P-bit parallel data width.
A fail signal selection control unit 10 for outputting a selection control signal 10 s for shifting and outputting the selection control signal 10 s. A semiconductor device comprising a switching means (multiplexer) 20 for performing predetermined shift conversion in accordance with a parallel data width of P bits and supplying the converted fail signals MFD1 to MFDn to the corresponding fail bit storage means. There is a test device.

As the serial output signal C100s supplied from the pattern generator, one output start signal indicating that the DUT has started serial output in Q times or a predetermined signal indicating positional information of each cycle of serial output. There is the semiconductor test apparatus described above, wherein the number is the number of cycle information signals.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings together with embodiments.

The present invention will be described below with reference to an example of the internal configuration of a main part of the FM shown in FIG. 1 and a timing chart for explaining fail storage in FIG. Elements corresponding to the conventional configuration are denoted by the same reference numerals. Also, the description will be made assuming that the DUT is a device similar to the conventional device. In other words, it is assumed that the memory in the DUT has a 16-bit width and is a device of a form in which 4-bit width data is serially transferred four times in succession.

As shown in FIG. 1, an example of the internal configuration of the main part of the FM according to the present invention has a configuration in which a fail signal selection control unit 10 and a multiplexer 20 are added to conventional components.

The fail signal selection control unit 10 receives the serial output signal C100s from the pattern generator,
The fail signal FD is sent to the multiplexer 20 to the bit position corresponding to the parallel data width of 16 bits in the DUT.
A selection control signal 10s for shifting 1 to FD4 is output. Here, as a first example of the serial output signal C100s supplied by the pattern generator, one output start signal C100s1 indicating that the DUT starts serial output.
There is an example. In this case, the output start signal C1 is provided with a setting register for designating the number of serial outputs four times.
Immediately after receiving 00s1, the selection control signal 10 which is shift information (see FIG. 2C), for example, 0, 1, 2, 3 for 4 cycle periods set by the setting register.
s is sequentially supplied to the multiplexer 20. As a second example of the serial output signal C100s, there is an example in which the pattern generator directly outputs shift information C100s2 of, for example, 0, 1, 2, 3 for four cycle periods. In this case, upon receiving the shift information, the selection control signal 10 s, which is simply retimed shift information, may be supplied to the multiplexer 20.

The multiplexer 20 is means for shifting and switching the n input signal to a predetermined output terminal of the n output terminals in a predetermined bit width unit. That is, in response to the selection control signal 10s, in each of the four divided serial cycles, the lower four bits FD1 to FD4 are output to the output terminal shifted in units of four bits. For example, in FIG. 2, in the first cycle of the four-cycle period, the fail signal F determined as pass / fail with the corresponding DUT serial data Do1 (see FIG. 2D).
D1 to FD4 are directly output as MFD1 to MFD4 (see FIG. 2E). The next cycle is the corresponding DUT
MF obtained by shifting the fail signals FD1 to FD4 determined as good or bad by the serial data Do2 (see FIG. 2F) by 4 bits
Output as D5 to MFD8 (see FIG. 2G). In the next cycle, the fail signals FD1 to FD4 determined to be good or bad by the corresponding DUT serial data Do3 are output to MFD9 to MFD12 which are shifted by 8 bits. In the last cycle, the fail signals FD1 to FD4 determined to be good or bad with the corresponding DUT serial data Do4 (see FIG.
The data is output to MFD13 to MFD16 shifted by 2 bits (see FIG. 2J).

The means for realizing the present invention is not limited to the above embodiment. For example, as shown in the configuration example of FIG. 6, there is an implementation example including a multiplexer 30 and a WE selection control unit 35. In this case, the multiplexer 30 receives the fail signals FD1 to FD4 in units of bits specified by the register, for example, in units of lower 4 bits, and distributes and outputs the signals in units of upper 4 bits. For example, SFD1,5
9, 13, 17, ... supply FD1. On the other hand, the WE selection control unit 35 supplies the write enable signals 20s1 to 20sn to the WE control units WE1 to WEn only for any group in units of 4 bits. For example, in the first cycle of the four cycle period, the write enable signal 2 is provided only to the WE control units WE1 to WE4.
0s1 to 20s4 are supplied, and in the next cycle, the write enable signals 20s5 to 20s8 are supplied only to the WE control units WE5 to WE8. The same applies to the following.

[0021]

According to the present invention, the following effects can be obtained from the above description. As described above, according to the present invention, even when a DUT is output from the DUT to the outside by dividing the data into a plurality of serial data and outputting the data, the FM is made to correspond to the data width of the memory in the DUT. In this configuration, the failed data can be stored in the memory for storing the failed data, so that the position of the failed data becomes 1: 1 correspondence. The advantage that a good fail analysis can be obtained is obtained, and the convenience of the fail analysis is improved.

[Brief description of the drawings]

FIG. 1 is an example of an internal configuration of a main part of an FM according to the present invention.

FIG. 2 is a timing chart for explaining fail storage in a device of a serial transfer mode according to the configuration of FIG. 1;

FIG. 3 is a main configuration of a semiconductor test apparatus.

FIG. 4 is a conventional internal configuration of an FM.

FIG. 5 is a timing chart of serial transfer of a device in a serial transfer mode.

FIG. 6 is an example of an internal configuration of a main part of another FM according to the present invention.

[Explanation of symbols]

 FM1 to FMn Fail bit memory WE1 to Wen WE control unit 10 Fail signal selection control unit 20, 30 Switching means (multiplexer) 35 WE selection control unit 50 Address MUX unit 100 Pattern generator (PG) DC logical comparator FM Fail memory FC Waveform shaper

Claims (3)

[Claims] An n-bit fail signal is received from a logical comparator, and n-channel fail bit storage means corresponding to the n-bit width is provided in a fail memory device.
The device under test (DUT) has a data width of P bits for accessing an internal memory, and when outputting the parallel data of the P bit width, the data is divided into M times and Q times to output serially. In the semiconductor test apparatus for testing the device, the DUT supplies a serial output signal indicating that serial output is being performed by dividing it into Q times from the pattern generator, receives the serial output signal, and performs the logic In the fail signal of n-bit width from the comparator, the fail signal divided into Q times of lower M bits corresponding to the bit width M output by the DUT is sequentially received to correspond to the parallel data width of P bits in the DUT. The lower M-bit fail signal is shift-converted to a predetermined bit position, and the converted fail signal is shifted to the corresponding n channel. The semiconductor testing apparatus characterized in that it comprises a shift conversion unit supplied to the fail bit storage means Le. 2. An n-bit fail signal is received from a logical comparator, and n-channel fail bit storage means corresponding to the n-bit width is provided in the fail memory device.
The device under test (DUT) has a data width of P bits for accessing an internal memory, and when outputting the parallel data of the P bit width, the data is divided into M times and Q times to output serially. In a semiconductor test apparatus for testing the device, a DUT divides the signal into Q times, supplies a serial output signal indicating that a serial output is being performed from a pattern generator, receives the serial output signal, and In the fail signal of n bit width from the comparator, the fail signal divided into Q times of the lower M bits corresponding to the bit width M output by the DUT is sequentially received and corresponds to the parallel data width of P bits in the DUT. A fail signal selection control unit that outputs a selection control signal that shifts and outputs the lower M-bit fail signal to a bit position to be performed; Receiving the selection control signal, the lower M bits in each serial cycle divided into Q times are predetermined-shift-converted in accordance with the parallel data width of P bits in the DUT, and the converted fail signal corresponding to the shift conversion is supported. Switching means for supplying to the fail bit storage means. 3. The serial output signal supplied from the pattern generator is one output start signal indicating that the DUT has started serial output in Q times or a predetermined number indicating shift information of each cycle of serial output. 3. The semiconductor test device according to claim 1, wherein the shift information signal is a shift information signal.