JP2000125149A - Video equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To sufficiently reduce an EMI level without using any EMI countermeasure parts and a housing shielding member which cause cost increase. SOLUTION: A video camera 21 of an analog system is provided with a CCD 22 that photographs an object, a CCD driver 23 that drives the CCD 22, a basic clock oscillator 24 that generates a basic clock, an SSCG 1 that applies spread spectrum processing to the basic clock from the basic clock oscillator 24, an SSG 25 that generates various synchronizing signals based on the basic clock that is spread-spectrum-processed by the SSCG 1, a frequency divider 25 that divides the basic clock by 1/4, and a sample-and-hold circuit 27 that samples and holds an output of the CCD 22.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video device, and more particularly, to a video device characterized by an EMI measure.

[0002]

2. Description of the Related Art Conventionally, in electronic equipment, regulation values (FCC (US), V
EMI measures are implemented to satisfy CCI (Japan) and CISPR (Europe).

For electronic devices distributed in the European region, C
To take the E mark, EMC measures are an essential item in design. In particular, in video equipment, with the digitization of video signals, many harmonic components of the clock are generated as electromagnetic waves because the operation is performed using a clock signal of several tens of MHz.

The EMI countermeasure for suppressing the harmonic component of the clock within the limit value of the clock has been repeatedly performed in trial and error in the development stage of the video equipment. Conventionally, the following countermeasures have been taken as a countermeasure for this.

(A) A substrate of an electronic circuit, which is a source of electromagnetic wave noise, is covered with a metal housing, and a gap between the metal housings is formed into a complete box-shaped shield housing using a gasket, a shield finger, or the like to confine electromagnetic waves.

(B) A shielded wire is used for the connection cable connected to the connector, and the connection shield potential is made the same as the potential of the metal casing to improve the shielding ability of the cable, so that electromagnetic waves leak outside the casing and the connection cable. To prevent

[0007] (C) When it is not possible to completely shield with a metal housing, an EMI countermeasure component such as a ferrite bead is disposed at an electromagnetic wave generation source of an electronic circuit, and a harmonic component of a signal causing the generation is attenuated as thermal energy. Or to a low impedance portion such as GND to reduce the electromagnetic radiation level.

The conventional countermeasures (A) and (B) described above
In this case, ingenious measures to improve the shielding performance by devising the case design have increased the size of the electronic device and increased the cost.

In the countermeasure method (C), addition of an EMI countermeasure portion such as a ferrite bead on an electronic circuit increases the size of the circuit, and further increases the cost of the EMI countermeasure component.

Here, a CCD 20 as shown in FIG.
1. CCD driver 202, SSG (synchronous signal generator)
203, basic clock oscillator 204, S / H (sample and hold circuit) 205, LPH (low-pass filter) 2
06, A / D converter 207, DSP 208, D / A
Converter 209, LPF 210, encoder 211,
The prior art will be described using an electronic circuit including a frequency divider 212 and an adder 213 as an example.

The electronic circuit shown in FIG. 13 is a circuit configuration of a conventional video camera. The basic clock from the basic clock oscillator 204 is frequency-divided by the SSG 203 to convert various synchronization signals (4 fsc, Sync, BF, etc.) into S / S signals. The signal is supplied to a signal processing step from H205 to the encoder 211. The CCD 201 is driven via a CCD driver 202 by a signal output from the SSG 203.

The output signal from the CCD 201 is S / H20
5 and input to the A / D converter 207 through the LPF 206 to be converted into a digital value.
Operation is performed at 08. The D / A converter 209 converts the output of the DSP 208 into an analog signal (luminance Y, color difference R
-Y, BY). Where LPF
A low-pass filter 210 removes noise of the analog signal after the D / A conversion.

The encoder 211 is connected to the SSG 203
Receives various synchronization signals (4fsc, Sync, BF, etc.) and fsc from the frequency divider 212, and outputs a luminance signal Y and a color subcarrier signal C that match the television signal format (NTSC, PAL, etc.).

An adder 213 adds the luminance signal Y and the color subcarrier signal C and outputs a composite video signal such as NTSC or PAL.

Next, as an operation for processing an output signal of the CCD 201, a mechanism of a conventional sample and hold process will be described with reference to FIG.

Since the drive signal arrives at the CCD 201 with a delay with respect to the drive pulse shown in FIG.
CCD having a delay time of Δt1 as shown in FIG.
Output. Further, the CCD output is Δt up to the CCU unit.
Since two cable delays occur, the received signal of the S / H circuit 205 is as shown in FIG. Then, the S / H circuit 205 converts the received signal into an S / H signal shown in FIG.
The sample was held by the H pulse.

Here, the S / H pulse shown in FIG. 14 (d) corresponds to the CCD 2 in the driving pulse train shown in FIG. 14 (a).
The S / H pulse was generated with reference to the signal at point B, which was temporally delayed from the original signal point A that driven 01.

This conventional design method is usually called a synchronous circuit, and is a technique that is easy to perform timing design and is usually performed. However, since the system operates on the basis of the synchronized clock, there is a point that harmonic components of the clock are likely to be generated periodically during the rise and fall times of the clock.

That is, in the conventional electronic circuit example shown in FIG. 13, the basic clock oscillator 2 is used in all stages from the driving of the CCD 201 to the generation of the final video signal.
All the blocks are operated in synchronization with the basic clock oscillator 204, and the harmonic components of the basic clock oscillator 204 are transmitted to the outside as EMI components. It will be emitted as electromagnetic waves.

Since the level of this electromagnetic wave is an electromagnetic wave component synchronized with the basic clock oscillator 204 as shown in FIG. 15, it is expressed as a narrow band energy distribution having a peak level when observed with a measuring instrument such as a spectrum analyzer. Is done.

E to evaluate against the electromagnetic interference wave regulation value of each country
In the MI observation, the noise level is evaluated by reading the intensity level of the narrow band energy distribution having the peak level with a receiver through a certain band filter.

Reducing this noise level is a measure against EMI. As a conventionally well-known means, as shown in FIG. 16, a case 222 in which a circuit board 221 is made of metal is used.
It has been devised to improve the shielding performance by covering with.

In order to reduce the weight, the housing 222
Is not made of metal, the circuit board 221 is covered with a member such as a mold. However, in this case, since there is no shielding effect, the circuit board 221 is mounted on the molded casing 222.
The device has been devised to cover it internally with an equipotential metal plate, or to form a conductive film inside the casing 222 formed by molding to provide a shielding effect.

Further, as a circuit measure for lowering the noise level, an EMI countermeasure component such as a ferrite bead is added to the electronic circuit portion on the circuit board 221 to suppress the EMI level on the circuit. I went pinpoint.

[0025]

However, any of the above-mentioned conventional EMI countermeasures has a problem that an expensive additional countermeasure member is required and the cost is increased.

Also, the noise suppression effect of the countermeasure member has a difference due to the variation of the member and the joining condition at the time of assembling, and there is a problem in manufacturing that the countermeasure effect is not stable.

FIGS. 17 and 18 show specific examples of the results after the conventional EMI countermeasure measured using a spectrum analyzer in an anechoic chamber.

In both FIGS. 17 and 18, the horizontally polarized E
It is the result of observing the MI level. In FIGS. 16 and 17, as a reference example, CISPR Pub. 1
The limit line of Class A of No. 1 is shown. The dotted line is a 6 dB margin line for reference.

FIG. 17 shows the result of a conventional countermeasure in a case where the circuit board 221 is covered with a metal casing 222 as shown in FIG. Further, FIG. 18 shows the result when the circuit board 221 is covered by the casing 222 using a member such as a mold. In this case, since there is no shielding effect, the EMI radiation level is also increased.

FIG. 17 and FIG.
Although it is the sA limit line, the regulation value of each country for consumer equipment and medical equipment usually requires the Class B limit line, and the countermeasure requires a very large amount of time and labor.

The limit line of Class B is C
In the case of CISPR with respect to the limit line of lessA, the standard value becomes stricter by 10 dB. This 10
The limit line of dB is 10 dB below the limit line and the margin line shown in FIGS.
Because of the parallel movement, it is difficult to clear the Class B limit line and the margin line at the current EMI level shown in FIGS.

As described above, in the prior art, in addition to the above-mentioned problems, in addition to designing the housing 222 to improve the shielding property, the electronic circuit portion on the circuit board 221 may be used.
There is a problem that EMI countermeasures cannot be sufficiently implemented even if an expensive additional countermeasure member is used, for example, by adding an EMI countermeasure component such as a ferrite bead to suppress the EMI level on the circuit.

The present invention has been made in view of the above circumstances, and provides an image apparatus capable of sufficiently reducing the EMI level without using an EMI countermeasure component or a casing shield which causes an increase in cost. It is intended to be.

[0034]

According to the present invention, there is provided a video apparatus for performing video signal processing using a first clock subjected to a spread spectrum processing, and a second video processing apparatus not performing a spread spectrum processing. Video signal generating means for generating a video signal using a clock.

In the video equipment of the present invention, the video processing means performs the video signal processing using the first clock subjected to the spread spectrum processing, so that the EMI countermeasure parts and the shield of the housing which cause an increase in cost can be provided. The EMI level can be sufficiently reduced without using it.

[0036]

Embodiments of the present invention will be described below with reference to the drawings.

First Embodiment FIGS. 1 to 6 relate to a first embodiment of the present invention, and FIG. 1 is a configuration diagram showing a configuration of an analog video camera which is a video device.
FIG. 3 is a configuration diagram showing the configuration of the SSCG of FIG. 1, and FIG.
FIG. 4 is an explanatory view for explaining the operation of the spread spectrum processing by SCG, FIG. 4 is a view showing the result of EMI measurement when the video camera of FIG. 1 is covered with a metal housing, and FIG. FIG. 6 is a diagram showing a result of EMI measurement when the sample is covered by the above, and FIG. 6 is a diagram for explaining the sample and hold signal of FIG.

In each of the following embodiments including this embodiment, a spread spectrum process is performed on a basic operation clock of a video device to perform a video signal process.

Further, in order to match each TV system,
A signal system not subjected to the spread spectrum processing is prepared separately from the video signal processing system, and a TV signal is synthesized or controlled so that it can be connected to ordinary video equipment.

As a result, the video signal processing system performs a spread spectrum process to realize a circuit operating at a low EMI level. In addition, since TV signals are synthesized or controlled using a signal system that is not subjected to spread spectrum processing, it is practically compatible with ordinary video equipment. Inexpensive EMI without the need for more expensive EMI countermeasure parts
Since measures can be taken, it is effective in reducing the cost of video equipment.

First, the operation of the spread spectrum processing will be described with reference to FIG.

In FIG. 3, the solid line indicates the noise level when the spread spectrum processing is not performed, and the broken line indicates the case where the spread spectrum processing is executed.

When the spread spectrum processing is executed, the noise level which has been present in a peak shape in the case of the noise level when the spread spectrum processing is not performed is changed to the noise level power within a certain band as indicated by an arrow. As a result, the noise level is improved by about 6 dB to about 10 dB as compared with the case where the spread spectrum is not performed.

This spread spectrum processing reduces the level of EMI and makes it possible to take a small measure.

Next, the principle of the spread spectrum technique will be described first with reference to FIG.

FIG. 2 shows an SSCG (Spread Speech).
1 shows an internal configuration of a CTC (Clock Clock Generator) 1. In the SSCG 1, a signal from a clock input terminal 2 is received by a phase comparator (PC) 3, and a phase error signal is received by a charge pump 4. hand over. Here, charge pump 4
Is stable at DC potential when the phase error is small.

The output of the charge pump 4 is supplied to an adder 5
The spread signal output from the D / A converter 6 is mixed. The signal obtained by mixing the spread signal is input to the VCO 7, and is output from the spread spectrum clock output terminal 8 to the outside as a spread spectrum clock signal. The spread-spectrum clock signal output to the spread-spectrum clock output terminal 8 is:
The feedback loop of the PLL operates so that the phase is returned to the phase comparator 3 and compared with the clock input terminal 2 to reduce the phase error.

The spread spectrum data is stored in the RAM 1
0, which is read out from the RAM 10 as spread spectrum data, D / A converted by the D / A converter 6, and input to the adder 5 as the spread signal.

The spread spectrum data stored in the RAM 10 has a function of returning to the initial state in response to a reset signal from a reset terminal 11. By inputting this reset signal from the outside, the spread spectrum of the external signal is reduced. Processing can be performed synchronously. Further, from the data load terminal 12, spectrum spread data to be stored in the RAM 10 can be input and rewritten.

As the format of the spread spectrum data that can be input from the data load terminal, as shown in FIG. 2, the spread spectrum may be performed by performing a periodic linear phase shift such as a ramp wave shape, or may be performed by white light. Finite-period PN that forms a spectral component with a noise component
(Pseudo-random noise) data.

The first embodiment will be specifically described with reference to FIG. FIG. 1 shows an embodiment of an analog video camera.

As shown in FIG. 1, an analog video camera 21 according to the present embodiment has a CCD for imaging a subject.
22, a CCD driver 23 for driving the CCD 22,
A basic clock oscillator 24 for generating a basic clock (4 fsc, fsc: subcarrier frequency), SSCG1 for performing spectrum spreading on a basic clock (4 fsc) from the basic clock oscillator 24, and SSCG
SSG (synchronous signal generator) 25 that generates various synchronous signals from the basic clock subjected to spread spectrum by 1
A frequency divider 26 that divides the basic clock by ４, and CC
An S / H (sample and hold circuit) 27 for sampling and holding the output of D22 is provided.

In the analog video camera 21, the delay circuit 28 receives the clock from the SSG 25 and delays the S / H pulse 28a by Δt ₁ + Δt ₂ for S.
/ H27.

Further, the signal sampled and held by the S / H 27 is subjected to γ correction processing in a γ correction circuit 29, and then subjected to outline enhancement in a HAP (horizontal outline) enhancement circuit 30 and a VAP (vertical outline) enhancement circuit 31. The processing is performed, and the adder 33 converts the signal into a Y signal.

The signal sample-and-hold processed by the S / H 27 passes through the 1-HDlay circuit 34 and the synchronizing switch 35 to become CB and CR of color signal components. Then, the YL signal and the CR and CB signals, which are the luminance signal components, are converted into three primary color signals of RGB in the matrix circuit 36.

The gain control circuit 37 is a variable gain section for obtaining a white balance with respect to the RGB three primary color signals from the matrix circuit 36. The gain control circuit 37 converts the R'G'B 'signal after the gain control processing into a color operation circuit 38.
, And the result is converted to a DC level by an integrating circuit 39, and a WB (white balance) control circuit 40
Is fed back to the gain control circuit 37.

By this feedback loop, control is performed so that white balance can be obtained for the RGB primary color signals from the matrix circuit 36.

R ′ after gain control processing in the gain control circuit 37 that has been subjected to white balance processing.
The G′B ′ signal is processed by the color γ circuit 41 and R′G ″
The gradation is corrected so as to obtain an appropriate color reproduction as a B ″ signal.
The B "signal is converted to an RY, BY color difference signal.

Further, the RY and BY color difference signals are subjected to quadrature quadrature modulation by the color modulator 43,
It becomes a color signal modulated by sc (subcarrier frequency). The modulated signal is added to a later-described reference burst signal by an adder 44 to become a color signal C. Then, the color signal C is added to the Y signal from the adder 33 by the adder 45 and output as a video signal (video).

In the first embodiment, the basic clock of the basic clock oscillator 24 is frequency-divided by 1/4 by the frequency divider 26 to divide the frequency to generate fsc (subcarrier frequency).
Also, the reference burst signal receives a BF (burst flag) signal from the SSG 25 by the burst gate 46 and receives the fs signal.
It is created by gating c (subcarrier frequency).

In the first embodiment, as described above, the basic clock oscillator 24 is connected to the S clock described in FIG.
A clock whose spectrum is spread using SCG1 is used.

That is, the TV synchronization signal (Sync signal, H
DSG, VD signal, etc.) are operated using a spread spectrum clock, and the CCD
The drive of the CCD 22 is also performed with a spread-spectrum clock from the sample-and-hold processing of the CCD 22 to the point before the quadrature-phase modulation is performed by the color modulator.

In the first embodiment, the output portion of the basic clock oscillator 24 indicated by the bold line in FIG. 1, the fsc (subcarrier frequency) from the frequency divider 26 and the reference burst signal from the burst gate 46 Is a signal completely synchronized with the basic clock oscillator 24, but otherwise operates with a clock that is spread spectrum by the SSCG1.

In the case of the present embodiment, the synchronizing signal relating to the horizontal scanning such as the Sync signal loses the frequency interleaving relationship between the color subcarrier signals of fsc, but the devices such as the TV monitor and the VTR are horizontal. Since the apparatus has an automatic correction function such as AFC and APC for the scanning phase shift (jitter) on its own side, there is no problem in practice even if the relationship of frequency interleaving is broken.

FIG. 4 (metal housing) and FIG. 5 (mold housing)
FIG. 3 shows specific EMI measurement results of the analog video camera 21 of the present embodiment.

FIGS. 4 (metal casing) and FIG. 5 (mold casing) show the same set as FIGS. 17 (metal casing) and FIG. 18 (mold casing) described in the prior art. The effect of the present embodiment is alternately compared.

FIG. 4 (metal housing) shows an example in which the housing is treated with a metal shield. The shield is the same as the condition shown in FIG. 17 (metal housing) of the conventional example.

When compared with the conventional FIG. 17 (metal casing),
It can be confirmed that the peak-like EMI noise in the band from about 60 MHz to about 200 MHz is reduced by the spread spectrum processing and is reduced to the dark noise level of the measurement system as shown in FIG. 4 (metal casing).

Further, in FIG. 5 (mold casing), the casing is a mold, and despite no shielding effect, the peak EMI noise in the band from about 60 MHz to about 500 MHz is subjected to the spread spectrum processing. Have been reduced. Compared to the case of FIG. 18 (mold housing), FIG. 5 (mold housing) is improved by about 6 dB.

As described above, in the present embodiment, looking at the EMI measurement results of FIG. 4 (metal casing) and FIG. 5 (mold casing), the conventional FIG. 17 (metal casing) and FIG. The EMI noise having a peak shape is diffused as compared with the case of (body), so that the EMI level is improved, and
EMI until B limit line can be cleared enough
The level can be reduced.

The processing performed by the S / H circuit 27 is as follows.
The timing must correspond to the CCD signal output from the CCD 22, and the CCD signal must be completely correlated.

If this timing does not coincide with the drive signal side, the occurrence of 1 / f noise due to the phase timing shift in S / H 27 appears as random or beat-like visual noise.

A method for solving this beat phenomenon will be described with reference to FIG. FIG. 6 is a diagram illustrating generation of the sample and hold pulse according to the present embodiment.

In the sample-and-hold pulse generating operation shown in FIG. 14 of the conventional example, a CCD output is generated on the basis of a driving pulse, which is received by a receiving circuit and then processed by a sample-and-hold circuit.

In the conventional sample-and-hold processing, a signal generated based on the A drive pulse has a time delay of Δt1 and Δt2. Therefore, the signal is processed by a drive pulse B which is a reference pulse next to the A drive pulse (normal signal). Synchronization processing circuit). Therefore, as described with reference to FIG. 14, the sample and hold circuit generates the sample and hold pulse based on the B drive pulse.

In the conventional circuit shown in FIG. 13, FIG.
As shown in (1), if the sample and hold pulse is processed at the timing of the synchronization signal such as the A drive signal or the B drive signal, there is no effect on the image quality, and there is no problem.

However, when each drive signal is spread spectrum as in this embodiment, since each CCD output itself is subjected to spread spectrum modulation, each sample hold signal is also applied to each drive signal. It is necessary to process at the timing corresponding to. If this is not performed, image noise will occur.

FIG. 6A shows an SS-modulated (spread spectrum modulation) drive pulse, FIG. 6B shows an SS-modulated CCD output signal, and FIG. 6C shows a received signal of the S / H 27 and FIG. (D) shows an SS-modulated sample hold pulse.

In this embodiment, in FIG. 6, the CCD signal generated from the drive signal modulated by the “A pulse modulation component” of the drive pulse is SS-modulated by the “A pulse modulation component”. Sample hold (S /
H) processed by pulse (d).

Therefore, in the present embodiment, the drive signal is delayed by the delay circuit 28 so that the drive signal is associated with the modulation components of the CCD signal and the sample hold signal.

Second Embodiment FIGS. 7 and 8 relate to a second embodiment of the present invention. FIG. 7 is a configuration diagram showing a configuration of a digital video camera which is a video device, and FIG. FIG. 8 is a configuration diagram illustrating a configuration of a modification of the digital video camera in FIG. 7.

Since the second embodiment is almost the same as the first embodiment, only different points will be described, and the same components will be denoted by the same reference numerals and description thereof will be omitted.

Next, a second embodiment will be described with reference to FIG. FIG. 7 shows an embodiment of a digital video camera.

As shown in FIG. 7, in the digital video camera (digital camera) 51 of the present embodiment, the signal sampled and held by the S / H circuit 24 is output from the A / D converter 53 via the LPF 52. Output to input. Then, a digital output of the A / D converter 53 is output to an input of a DSP (digital signal processor) 54.

Further, the output of the DSP 54 is output to a D / A converter 55, and is output via three LPFs 56.
(Luminance signal) and the RY / BY signal are output to the encoder 58. Here, the LPF 56 is a D / A converter 5
5 are connected to each channel.

The encoder 58 has three LPFs 5
6 to receive the Y (luminance signal) and the RY / BY signal,
The color difference signal is balanced-modulated by an fsc (subcarrier signal) 59 to generate a C signal and a Y signal, and the adder 60 adds the C signal and the Y signal to output a video.

A / D converter 53, DSP 54 and D
The / A converter 55 is controlled by a System Clock which is a clock signal generated by the SSG 25. A synchronization signal 61 such as Sync and BF from the SSG 25 is a synchronization signal input to the encoder 58 and the DSP 54 for signal processing.

In the present embodiment, the analog signal processing circuit of the first embodiment is converted to digital signal processing using the DSP 54. That is, CCD2
The processing of the second output signal into a video signal is the same as in the first embodiment and the second embodiment.

In the second embodiment, the output of the S / H 27 is connected to the signal input of the A / D converter 53 via the LPF 52 for removing unnecessary harmonic components before A / D conversion.

The signal of the S / H circuit 27, which has been digitally converted by the A / D converter 53, is subjected to digital processing by the DSP 54 in the video signal processing shown in the analog circuit of FIG.

The digital signal calculated from the output of the DSP 54 is converted by the D / A converter 55 into Y (luminance signal) and R
-Y / BY signal, and converted by the LPF 56 to AD
The high-frequency signal is removed by the conversion, and the final video signal is created by the encoder 58.

In the second embodiment, as in the first embodiment shown in FIG.
Uses a signal that has been synchronously frequency-divided by the frequency divider 26 without passing through the SSCG1.

Signal processing other than the generation of the subcarrier signal fsc (CCD driving, sample hold, A /
D conversion, DSP signal processing, D / A conversion, System
Clock, Sync, BF, etc.)
Are all generated using clock signals that are spread using SSCG1.

As described above, in the second embodiment, similarly to the first embodiment, since the spectrum other than the subcarrier signal fsc is spread, digital signal processing with an improved EMI level can be realized. .

FIG. 8 shows a configuration of a modification of the second embodiment, and is different from the second embodiment in the method of producing fsc (subcarrier frequency).

In this modification, the 4fsc signal is converted to the SSCG
In step 1, a spread spectrum process is performed to generate an SS-4fsc signal. It is frequency-divided directly by the frequency divider 26 and SS-fsc
Has been created.

In this modification, INV. SS-fsc subjected to spread spectrum processing through SSCG section 61
The signal is subjected to despreading processing to generate fsc (subcarrier frequency) that has not been subjected to spectrum spreading processing.

To execute this despreading process, the SSG
25 using the SSCG Reset signal 62
G25 corresponding to the diffusion process of INV. The SSCG 61 is being reset.

More specifically, a process of correcting the fsc (subcarrier frequency) signal so as to eliminate the phase shift of fsc (subcarrier frequency) is performed.

In the configuration of this modified example, the synchronizing signal serving as the EMI noise source is composed of the 4fsc signal output from the basic clock oscillator 24 and the INV. Only the fsc (subcarrier frequency) output from the SSCG unit 61 is used, and a portion serving as a noise source can be laid out small. In addition, since all other signal processing is performed using the signal subjected to the spread spectrum processing, the circuit configuration with the improved EMI level is the second.
This has the effect of being simpler than the embodiment.

Also in the above-described modified example, similar to the second embodiment, since a signal other than fsc (subcarrier frequency) is spread, a digital signal processing with an improved EMI level can be realized.

Third Embodiment FIG. 9 is a configuration diagram showing a configuration of a medical electronic endoscope apparatus which is a video apparatus according to a third embodiment of the present invention.

Since the third embodiment is almost the same as the second embodiment, only different points will be described, and the same components will be denoted by the same reference numerals and description thereof will be omitted.

In the medical electronic endoscope apparatus 71 according to the third embodiment, as shown in FIG. 9, the purpose of processing the signal of the CCD 22 and finally converting the signal into a video signal is as follows. The third embodiment is characterized in that it is divided into a patient circuit and a secondary circuit.

Here, an insulation circuit (photocoupler, insulation transformer, etc.) 72 separates the patient circuit and the secondary circuit.

The signal from the CCD 22 is processed by the S / H circuit 27, and is input to the DSP 54 via the A / D converter 53, and is input from the D / A converter 55 to the Y signal, RYB
The flow of outputting the -Y signal and the like is the same as in the second embodiment.

In the third embodiment, the S / H pulse 28
In order to create a ', a PLL circuit is formed. That is, a PLL loop is formed by the PLL phase comparator (PC) 73, the PLL charge pump (CP) 74, the PLL VCO 75, and the PLL frequency divider (1 / N circuit) 76a. The output of the S / H pulse divider (1 / N circuit) 76b is used as the S / H pulse 28a '.

S / H pulse divider (1 / N circuit) 76
“a” divides the frequency of the output of the PLL VCO 77. In this PLL circuit section, the SSCG 1 is provided in a PLL loop, and a signal subjected to spread spectrum processing is input to a PLL phase comparator (PC) 73. SSCG1 Rese
The SSCG Reset signal is input to the t terminal 11 from the SSG 25 via the delay circuit 78.

On the other hand, the PLL circuit arranged in the secondary circuit (= non-insulated circuit) has a PLL phase comparator (PC) 73.
, PLL charge pump (CP) 74, and PL
VXO75 for L, divider for PLL (1 / N circuit) 76a
The output of the PLL VCO 75 is A /
D converter 53, DSP 54, D / A converter 55
The reference clock is supplied to the DSP unit constituted by.

The SSG (synchronous signal generator) 79 arranged in the secondary circuit (= non-insulated circuit) is used for synchronizing signals (Sync, HD, VD) conforming to the television signal format.
, Etc.) are supplied to the DSP unit to serve as operation reference signals.

In this embodiment, the CCD 22 is driven by using a signal subjected to the spread spectrum processing by the SSCG 1.

This point is the same as the first and second embodiments. Thereby, the EMI level at the time of driving the CCD is reduced.

In particular, the patient circuit (= insulation circuit) is a floating portion and a circuit portion floating with respect to the earth ground because the leakage current is reduced and the electrical safety is improved. Conventionally, this floating portion is a noise generating source portion. For EMI countermeasures, it is necessary to cover the patient circuit (= insulation circuit) with a metal BOX shield as much as possible and to insert a ferrite core or the like into a signal line where EMI noise is generated.

In the present embodiment, the EMI noise component is reduced by causing the patient circuit (= insulation circuit), which is the floating portion, to operate using the signal subjected to the spread spectrum processing.

The reset signal from the delay circuit 78 is input to the reset terminal 11 of the SSCG1. This Reset signal is transmitted to the SSCG1 on the CCD drive side.
The drive signal of the CCD 22 that has been subjected to the spread spectrum processing is subjected to the spread processing in association with the drive signal.

In the first embodiment, the drive signal and C
Corresponds to the modulation components of the CD signal and the sample hold signal.
Although it was related by the delay means by the elay circuit,
As another means, as shown in the present embodiment, SS
The drive signal, the CCD signal, and the modulation component of the sample hold signal are associated with each other by forcibly associating the SSCG 1 for generating the sample hold pulse with the reset terminal 11 using the CG Reset signal.

Fourth Embodiment FIG. 10 shows a fourth embodiment of the present invention.
3 is a configuration diagram showing a configuration of a video device according to the embodiment. FIG.

The fourth embodiment will be described with reference to FIG. The portion indicated by reference numeral 81 in FIG. 10 is a video camera unit, which is a digital camera "not performing spread spectrum processing" which is the same as the conventional example shown in FIG. The portion indicated by reference numeral 82 is an image processing unit that has not been shielded, and is connected to the video camera unit 81.

The difference from the conventional example shown in FIG. 13 is that the video camera unit 81 is entirely covered with a shield case 81a.

The image processing unit 82 and the video camera unit 81 are connected by a digital data bus 83 from the DSP 208. Further, the video camera unit 81 outputs 4 fsc or a pixel clock to the SSCG 1 of the image processing unit 82.

The digital data bus 83 is latched by a DFF (latch circuit) 84, becomes an SS digital data bus 85, and is transmitted to an image processor 86 at the next stage.

In the image processing unit 82, the 4 fsc or pixel clock is subjected to the spectrum spread processing by the SSCG 1 and output as SS-CLK 87.

In the video camera unit 81, all the circuit processes are synchronized. As described in the first or second embodiment, the EMI level can be reduced by performing the spread spectrum processing. However, the video camera unit 81 is a single hybrid IC or a one-chip signal processing circuit, so that the size can be reduced. To realize this, the same circuit configuration as that of the conventional example is adopted.

In the video camera unit 81, E
In order to reduce the level of MI, the noise level is reduced by being covered with a shield case 81a.

In this embodiment, the video camera unit 81 does not perform the spread spectrum processing, but the image processing unit 82 is processed by the SS-CLK 87 that has been subjected to the spread spectrum processing by the internal SSCG 1. A digital data bus 83 input / output from / to the DSP 54 is SS-CLK by a DFF (latch circuit) 84.
The signal is processed based on the timing of 87 and becomes the SS digital data bus 85.

The SS digital data bus 85 is connected to the EMI
It is a bundle of digital data signals with reduced levels.

As described above, in the present embodiment, a unit having a large EMI level shown in the conventional example is processed using a clock subjected to spread spectrum processing in a processing unit to be connected. Similar effects can be obtained.

The SSCG 1 of the image processing unit 82 shown in the fourth embodiment may be placed at another location such as the position indicated by the broken line 88 in the video camera unit 81. Also, a DFF (latch circuit) 84 may be provided in the video camera unit 81 in the same manner.

In the fourth embodiment, the video camera unit 81 is provided with the shield case 81a. However, in the case where the video camera unit 81 is integrated as a result of the advance of semiconductor design and is formed as a single chip, the shield case is provided on the substrate. A case may be applied. In addition, the video camera unit 81
In the case where is configured as a single chip due to advances in semiconductor design, low power consumption is also achieved, and the EMI level decreases as the power consumption decreases. Therefore, the shield case may be removed.

Fifth Embodiment FIG. 11 shows a fifth embodiment of the present invention.
3 is a configuration diagram showing a configuration of a video device according to the embodiment. FIG.

Since the fifth embodiment is almost the same as the second embodiment, only different points will be described, and the same components will be denoted by the same reference numerals and description thereof will be omitted.

Next, a fifth embodiment will be described with reference to FIG. The fifth embodiment is an example of a display or printer device 91 such as a TV, FMD (face mount display), projector, etc., and a recording device 92 of a memory card or a magnetic recording device connected thereto.

The display or printer device 91 includes:
A video signal such as a composite signal is input from a video input terminal 93, and a YC separator (Sep) 94
The signal is separated, and the signal is separated into Y0, U0, and V0 signals by the decoder 95.

The C signal is output from the PLL phase comparator (P
C) 73, PLL charge pump (CP) 74, PL
A clock fsc synchronized with the video input terminal 93 is generated by a PLL circuit represented by the VCO 75 for L.

The LPF 96 for filtering the signal from the decoder 95 is supplied to the A / D converter 97 by Y0 and U
This is a band limiting filter for preventing aliasing before inputting 0 and V0 signals. A2 / D Y2, U2, V
The two signals are signal-processed by the digital process circuit 98,
The signals become R0, G0, and B0 signals, and become digital signals corresponding to the input signal format of the LCD 99 at the subsequent stage.

The R0, G0, and B0 signals are converted to analog signals by the D / A converter 100, and are converted into R1, G1, and B1 signals.
The signal is output to the LCD 99 as a signal. Here, the lens 10
Reference numeral 1 denotes an optical system that forms an image on a display medium such as the LCD 99, and provides an optimal image for a viewer or the print medium 102.

It should be noted that SSCG1 is connected to the reference clock (fs
c) and outputs SS-fsc.

In the recording device 92, for example, a magnetic recording medium (memory) 103 is provided as a recording means, and the Y1, U1, and V1 signals are converted into signals R2, It is output as G2 and B2 signals.

In this embodiment, the video input terminal 93 is YC-separated by a YC separator (Sep) 94, and
At 5, decoding processing is performed to convert to YUV signals. The reference clock necessary for this decoding is a PLL phase comparator (PC) 73 and a PLL charge pump (CP) 7.
4. PLL VCO 75, PLL frequency divider (1 / N) 7
6a.

In the present embodiment, the decoded YUV signal is A / D-converted based on the SS-fsc clock subjected to the spread spectrum processing by the SSCG 1, and thereafter, digital processing is performed by the digital process circuit 98. . Based on this SS-fsc clock, the LCD 99
And so on or a printer driver.

Further, recording of image information is performed on the magnetic recording medium 103 such as a memory card by the recording device 92 based on the SS-fsc clock.

In this embodiment, after digitization, “signal processing for display” and “signal processing for recording”
Using the SS-fsc clock that has been subjected to spread spectrum processing, the level of EMI interference waves can be significantly reduced.

Due to this effect, the display or the printer device 91 (FMD, laser beam driver, etc.) provided with the LCD 99 and the like can perform EMI without using a shielding material or the like.
Therefore, a small, lightweight and inexpensive display device is realized. Also, the recording device 92 does not require a shield material, and can be manufactured to be thin and inexpensive.

The recording device 92 may be detachable from a display device having an LCD 99 or the like or a printer device 91.

Sixth Embodiment FIG. 12 shows a sixth embodiment of the present invention.
3 is a configuration diagram showing a configuration of a video device according to the embodiment. FIG.

As shown in FIG. 12, this embodiment is an application example to a portable telephone with image function, a PHS, or the like.

The mobile phone with image function, PHS121,
Antenna 122, RF unit 123, IF (intermediate frequency) unit 1
24, a baseband unit 125, an audio processing unit 126, and an image processing unit 127.

These blocks are divided according to the operating frequency required for each block.
Is composed of an RFSW (switch) 131 for switching transmission, a power amplifier 132, and a preamplifier 132 for reception.

An IF (intermediate frequency) section 124 includes a transmission mixer 141, a transmission quadrature modulator 142, and a reception mixer 1
43, an IF amplifier 144 and a quadrature demodulator 145 for reception.

On the other hand, in the baseband section 125, the TDM
A151 (or CDMA baseband processing unit) 161
Mainly performs a channel codec for rearranging signals in accordance with a signal format such as TDMA or CDMA, and further uses a D / A converter 162 for a modulator to perform differential modulation / demodulation, error correction, and encoding. Performed by the department.

In the sound processing unit 126, the microphone 1
An audio signal is fetched from the audio signal 71 by the audio A / D converter 172. In addition, sound D /
The signal of the A converter 174 is received and an audio signal is output. The audio codec 175 performs audio signal band compression and audio encoding and decoding corresponding to each country's format (PHS, GSM, IS-54, etc.).

The image processing section 127 incorporates the digital video camera 81 described in the second embodiment.
Further, the display or the printer device 91 which has been subjected to the SS diffusion processing described in the fifth embodiment is incorporated to display an image. The operation of the sixth embodiment will be described below in detail. In the sixth embodiment, an example of a mobile phone with an image function / PHS is shown.

First, the receiving operation will be described. The voice receiving operation is performed by transmitting the signal received by the antenna 122 to the RF unit 1
Amplified by 23 preamplifiers 133, IF (intermediate frequency)
The detection and demodulation are performed by the unit 124.

In the baseband unit 125, a channel codec is applied, and the audio is decoded in the audio processing unit 126.

In the image receiving operation, the basic data flow is the same as that of the audio processing up to the baseband section 125.
When image data is received, the format of MPEG2, 4, etc. is demodulated.

The display or printer device 91 of the image processing unit 126 is an image display device in which the EMI level is reduced by SS diffusion, and displays a received image.

Next, the transmission operation will be described. Voice processing unit 12
6 is converted into a signal conforming to the transmission format by the baseband unit 125,
The signal is modulated by the (intermediate frequency) section 124, amplified by the RF section 123, and transmitted from the antenna 122.

In the image transmission operation, the digital video camera 81 in the image processing unit 127 captures an observation image, and the baseband unit 125 converts the image into an image transmission format such as MPEG2, 4, or the like.

[0159] Thereafter, the IF
This is the same as (intermediate frequency) section 124 and subsequent sections.

In the sixth embodiment, a digital video camera 81 is used to realize a low EMI level and perform signal processing when capturing an image in the image processing section 127.

[0161] Also, For display of an image, the EMI level is reduced by SS diffusion using a display or a printer device 91.

Normally, portable telephones, PHSs, and the like handle small power at the time of reception and handle large power at the time of transmission. The level difference between the transmitting and receiving blocks inside a small portable device is about 100 dB
Therefore, it was a major design problem to prevent mutual interference between transmission and reception blocks.

In the present embodiment, SS
The image processing unit 1 is provided with a low EMI level image pickup or image display or printing device by applying diffusion processing.
27, the interference with the audio processing unit 126 is reduced, and the data error rate is improved.
Accordingly, there is an effect that interference with the image processing unit 127 is reduced and noise on the screen is reduced.

[Supplementary Notes] (Supplementary Note 1) A video processing means for performing video signal processing using the first clock subjected to the spread spectrum processing and a video signal using the second clock not subjected to the spread spectrum processing A video signal generating means for generating a video signal.

(Additional Item 2) The image processing apparatus according to additional item 1, wherein the video processing means using the first clock performs signal processing of a video camera.

(Additional Item 3) The video device according to additional item 1, wherein the video processing means using the first clock performs signal processing of an electronic endoscope.

(Additional Item 4) The video apparatus according to additional item 1, wherein the video processing means using the first clock performs signal processing of image processing.

(Additional Item 5) The image processing apparatus according to additional item 1, wherein the video processing means using the first clock performs signal processing of an image display device.

(Additional Item 6) The video apparatus according to additional item 1, wherein the video processing means using the first clock performs signal processing of an image recording device.

(Additional Item 7) The video apparatus according to additional item 1, wherein the video processing means using the first clock performs signal processing of a portable communication tool.

(Additional Item 8) An additional item characterized by further comprising a spread code holding means for externally inputting and holding the spread code of the spread spectrum processing applied to the first clock as arbitrary spread information. 2. The video device according to 1.

(Additional Item 9) The second clock not subjected to the spread spectrum processing is a clock not subjected to the spread spectrum processing or a clock subjected to the inverse spread spectrum processing after being subjected to the spread spectrum processing. 3. The video device according to claim 1, wherein

(Additional Item 10) In the signal processing of the video camera, it is assumed that the sample-hold processing of the image-spread imaging device is processed by a sample-hold pulse having a correlation with the signal output of the image-spread image sensor. The video device according to claim 2, characterized in that:

[0174]

As described above, according to the video equipment of the present invention, the video processing means performs the video signal processing using the first clock subjected to the spread spectrum processing. There is an effect that the EMI level can be sufficiently reduced without using a shield of a housing or a housing.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a configuration of an analog video camera which is a video device according to a first embodiment of the present invention;

FIG. 2 is a configuration diagram showing a configuration of the SSCG of FIG. 1;

FIG. 3 is an explanatory diagram for explaining the operation of the spread spectrum processing by the SSCG of FIG. 2;

FIG. 4 is a view showing E when the video camera of FIG. 1 is covered with a metal housing;
Diagram showing the result of MI measurement

FIG. 5 is a diagram showing a result of EMI measurement when the video camera of FIG. 1 is covered with a mold housing;

FIG. 6 is a view for explaining the sample and hold signal of FIG. 1;

FIG. 7 is a configuration diagram showing a configuration of a digital video camera which is a video device according to a second embodiment of the present invention;

8 is a configuration diagram showing a configuration of a modified example of the digital video camera in FIG. 7;

FIG. 9 is a configuration diagram showing a configuration of a medical electronic endoscope apparatus which is an imaging device according to a third embodiment of the present invention.

FIG. 10 is a configuration diagram showing a configuration of a video device according to a fourth embodiment of the present invention.

FIG. 11 is a configuration diagram showing a configuration of a video device according to a fifth embodiment of the present invention.

FIG. 12 is a configuration diagram showing a configuration of a video device according to a sixth embodiment of the present invention.

FIG. 13 is a configuration diagram showing a configuration of a conventional video device.

FIG. 14 is a view for explaining a sample and hold signal of the video device of FIG. 13;

FIG. 15 is a view for explaining the level of electromagnetic wave radiation of the video device of FIG. 13;

FIG. 16 is a diagram showing an example of measures against electromagnetic wave radiation of the video device in FIG. 13;

FIG. 17 is a view showing E when the video device of FIG. 13 is covered with a metal housing;
Diagram showing the result of MI measurement

FIG. 18 is a diagram showing a result of an EMI measurement when the video device in FIG. 13 is covered with a mold housing;

[Description of Signs] 1 ... SSCG 21 ... Video Camera 22 ... CCD 23 ... CCD Driver 24 ... Basic Clock Oscillator 25 ... SSG 26 ... Divider 27 ... S / H

Claims (1)

[Claims] 1. A video processing means for performing video signal processing using a first clock subjected to a spread spectrum processing, and a video signal generation generating a video signal using a second clock not subjected to a spread spectrum processing And video means.