JP2006095330A - Electronic endoscope apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic endoscope apparatus which reduces an EMI level fully without using an EMI-prevention component and the shield of an enclosure which cause cost rise. <P>SOLUTION: The electronic endoscope apparatus is equipped with a CCD 22 which images a subject, a CCD driver 23 which actuates the CCD 22, a basic clock oscillator 24 which generates a basic clock, a spectrum spreading clock generator SSCG 1 which spreads a spectrum for the basic clock from the basic clock oscillator 24, a SSG 25 which generates various synchronized signals from the basic clock spectrum-spread by the SSCG 1, and an S/H 27 which samples and holds the output of the CCD 22. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an electronic endoscope apparatus, and more particularly to an electronic endoscope apparatus characterized by an EMI countermeasure part.

  Conventionally, in electronic equipment, EMI countermeasures have been implemented in order to satisfy the regulation values (FCC (US), VCCI (Japan), CISPR (Europe), etc.) of each country regarding electromagnetic environment characteristics EMC.

  For electronic equipment distributed in the European region, EMC measures are an essential item in the design in order to obtain the CE mark. Particularly in video equipment, with the digitization of video signals, the operation is performed using a clock signal of several tens of MHz, so that many harmonic components of the clock are generated as electromagnetic waves.

  Measures against EMI to keep the harmonic components of the clock within the limits of the regulation value have been repeatedly performed in many trials and errors in the development stage of video equipment. Conventionally, as countermeasures for this, the following countermeasures have been taken.

  (A) The substrate of the electronic circuit, which is the source of electromagnetic noise, is covered with a metal casing, and the gap between the metal casings is made into a complete box-shaped shield casing using gaskets, shield fingers, etc. to confine electromagnetic waves.

  (B) Use a shielded wire for the connection cable connected to the connector, make the connection shield potential the same as that of the metal housing, improve the shielding performance of the cable, and prevent electromagnetic waves from leaking outside the housing and the connection cable. .

  (C) When it is not possible to completely shield with a metal casing, an EMI countermeasure component such as a ferrite bead is arranged at the electromagnetic wave generation source of the electronic circuit, and the harmonic component of the signal causing the generation is attenuated as thermal energy or GND Escape to a low impedance part such as, and reduce the electromagnetic radiation level.

  In the conventional countermeasure methods (A) and (B) described above, the idea of improving the shielding performance by devising the design of the casing increases the size of the electronic device and increases the cost.

  In the countermeasure method (C), the addition of an EMI countermeasure part such as a ferrite bead on the electronic circuit increases the size of the circuit and further increases the cost of the EMI countermeasure part.

  Here, as shown in FIG. 13, CCD 201, CCD driver 202, SSG (synchronization signal generator) 203, basic clock oscillator 204, S / H (sample hold circuit) 205, LPH (low-pass filter) 206, A / D The prior art will be described by taking an electronic circuit comprising a converter 207, a DSP 208, a D / A converter 209, an LPF 210, an encoder 211, a frequency divider 212, and an adder 213 as an example.

  The electronic circuit of FIG. 13 has a circuit configuration of a conventional video camera. The basic clock from the basic clock oscillator 204 is divided by the SSG 203 and various synchronization signals (4fsc, Sync, BF, etc.) are encoded from the S / H 205 to the encoder. The signal processing steps up to 211 are supplied. The CCD 201 is driven via the CCD driver 202 by a signal output from the SSG 203.

  An output signal from the CCD 201 is processed by the S / H 205, input to the A / D converter 207 through the LPF 206, converted into a digital value, and an operation is executed by the DSP 208. The D / A converter 209 converts the output of the DSP 208 into an analog signal (luminance Y, color difference RY, BY, etc.) and outputs it. Here, the LPF 210 is a low-pass filter that removes noise of the analog signal after D / A conversion.

  The encoder 211 receives various synchronization signals (4 fsc, Sync, BF, etc.) from the SSG 203 and fsc from the frequency divider 212, and outputs a luminance signal Y and a color subcarrier signal C that match the television signal format (NTSC / PAL, etc.). Output.

  The adder 213 adds the luminance signal Y and the color subcarrier signal C, and outputs a composite video signal such as NTSC or PAL.

  Next, as an operation for processing the output signal of the CCD 201, a conventional sample and hold processing mechanism will be described with reference to FIG.

  Since the drive signal arrives at the CCD 201 with a delay from the drive pulse shown in FIG. 14A, the CCD output has a delay time of Δt1 as shown in FIG. 14B. Further, since the CCD output has a cable delay of Δt2 up to the CCU section, the received signal of the S / H circuit 205 is as shown in FIG. The S / H circuit 205 samples and holds this received signal with the S / H pulse shown in FIG.

  Here, the S / H pulse shown in FIG. 14D is a B point signal delayed in time from the original signal point A that drives the CCD 201 in the drive pulse train shown in FIG. The S / H pulse was made on the basis.

  This conventional design method is usually called a synchronous circuit, and is a technique that is usually implemented because it is easy to design timing. However, since the system operation is performed based on the synchronized clock, the harmonic component of the clock tends to be generated periodically at the rising and falling times of the clock.

  That is, in the example of the conventional electronic circuit shown in FIG. 13, processing is performed by various synchronization signals obtained by dividing the basic clock from the basic clock oscillator 204 in all stages from the drive of the CCD 201 to the production of the final video signal. All the blocks operate in synchronization with the basic clock oscillator 204, and the harmonic component of the basic clock oscillator 204 is emitted to the outside as an electromagnetic wave as an EMI component.

  As shown in FIG. 15, the level of the electromagnetic wave is an electromagnetic wave component synchronized with the basic clock oscillator 204, and is therefore expressed as a narrow band energy distribution having a peak level when observed with a measuring instrument such as a spectrum analyzer.

  In the EMI observation to evaluate the electromagnetic interference regulation value in each country, the noise level is evaluated by reading the intensity level with a receiver through a certain band filter for the narrow band energy distribution having this peak level.

  Reducing this noise level is a measure against EMI. As a means that is often implemented conventionally, as shown in FIG. 16, the circuit board 221 is covered with a casing 222 made of metal and has been devised to improve the shielding performance.

  Further, when the casing 222 cannot be made of metal in order to achieve weight reduction, a member such as a mold is used to cover the circuit board 221. However, since there is no shielding effect in this case, a device such as covering the circuit board 221 with an equipotential metal plate inside the mold casing 222 or forming a conductive film on the inside of the casing 222 formed by the mold. And have been devised to have a shielding effect.

  Furthermore, as a circuit measure for reducing the noise level, an EMI countermeasure part such as a ferrite bead is added to the electronic circuit portion on the circuit board 221 to pin down the EMI level on the circuit. I went to.

  However, the conventional EMI countermeasures described above have a problem that an expensive additional countermeasure member is required and the cost is increased.

  Further, the noise suppression effect of the countermeasure member also varies depending on the variation of the member, the joining condition at the time of assembly, and the like, and the lack of stability of the countermeasure effect is a manufacturing problem.

  FIG. 17 and FIG. 18 show specific examples of results after conventional EMI countermeasures measured using a spectrum analyzer in an anechoic chamber.

  Both FIG. 17 and FIG. 18 are the results of observing the EMI level of horizontal polarization. In FIGS. 16 and 17, CISPR Pub. 11 shows limit lines of Class A. The dotted line is a 6 dB margin line for reference.

  FIG. 17 shows a conventional countermeasure result when the circuit board 221 is covered with a metal casing 222 as shown in FIG. Further, FIG. 18 shows a result when the circuit board 221 is covered with a casing 222 using a member such as a mold. In this case, since there is no shielding effect, the radiation level of EMI also increases.

  17 and 18 show the Class A limit line. However, in consumer equipment and medical equipment, the regulation value of each country usually requires the Class B limit line, and it takes a very long time for countermeasures. And requires labor.

  The limit line of Class B is a standard value that is 10 dB stricter in the case of CISPR than the limit line of Class A. The limit line of 10 dB is obtained by translating the limit line and the margin line shown in FIGS. 17 and 18 downward by 10 dB. At the current EMI level shown in FIGS. It will be difficult to clear the line.

  As described above, in the conventional technology, in addition to the above problems, the housing 222 is designed in order to improve the shielding property, or the electronic circuit part on the circuit board 221 has EMI countermeasure parts such as ferrite beads. There is a problem that EMI countermeasures cannot be sufficiently implemented even if expensive additional countermeasure members are used, such as by performing addition or the like to suppress the EMI level on the circuit.

  The present invention has been made in view of the above circumstances, and provides an electronic endoscope apparatus capable of sufficiently reducing the EMI level without using an EMI countermeasure component or a shield of a casing that causes an increase in cost. The purpose is that.

  The electronic endoscope apparatus according to the present invention includes a video processing unit that performs video signal processing using a first clock that has been subjected to spread spectrum processing, and a video signal that uses a second clock that has not been subjected to spread spectrum processing. And a video signal generating means for generating.

  In the electronic endoscope apparatus according to the present invention, the video processing means performs the video signal processing using the first clock subjected to the spread spectrum processing, so that the EMI countermeasure parts and the shield of the casing that increase the cost can be obtained. It is possible to sufficiently reduce the EMI level without using it.

  According to the electronic endoscope apparatus of the present invention, the video processing means performs the video signal processing using the first clock that has been subjected to the spread spectrum processing. Therefore, there is an effect that the EMI level can be sufficiently reduced.

  Embodiments of the present invention will be described below with reference to the drawings.

First embodiment:
1 to 6 relate to the first embodiment of the present invention, FIG. 1 is a block diagram showing the configuration of an analog video camera as a video equipment, and FIG. 2 is a block diagram showing the configuration of the SSCG in FIG. 3 is an explanatory diagram for explaining the action of the spread spectrum processing by the SSCG of FIG. 2, FIG. 4 is a diagram showing the result of EMI measurement when the video camera of FIG. 1 is covered with a metal casing, and FIG. FIG. 6 is a diagram illustrating a result of EMI measurement when the video camera is covered with a mold housing, and FIG.

  In each of the following embodiments including this embodiment, spread spectrum processing is performed on the basic operation clock of the video equipment to perform video signal processing.

  Furthermore, in order to match each TV system, a signal system not subjected to spread spectrum processing is prepared separately from the video signal processing system, and a TV signal is synthesized or controlled, thereby enabling connection to a normal video device.

  Thus, the video signal processing system is subjected to spread spectrum processing, thereby realizing a circuit that operates at a low EMI level. In addition, since a TV signal is synthesized or controlled using a signal system that is not subjected to spread spectrum processing, it is practically compatible even when a normal video device is used. Furthermore, since it is possible to implement inexpensive EMI countermeasures without requiring expensive EMI countermeasure parts, it is effective for reducing the cost of video equipment.

  First, the effect | action of a spread spectrum process is demonstrated using FIG.

  In FIG. 3, the noise level when not performing the spread spectrum process is indicated by a solid line, and the case where the spread spectrum process is executed is indicated by a broken line.

  When spread spectrum processing is executed, the noise level that was present in a peak shape in the case of the noise level when spectrum spread processing is not performed becomes a spectrum by spreading the noise level power within a certain band as shown by the arrow. The noise level is improved by about 6 dB to about 10 dB as compared with the case without diffusion.

  This spread spectrum processing can reduce the EMI level and make the countermeasures light.

  Next, the principle of the spread spectrum technique will be described first with reference to FIG.

  FIG. 2 shows an internal configuration of an SSCG (Spread Spectrum Clock Generator) 1. In this SSCG 1, a signal from the clock input terminal 2 is received by the phase comparator (PC) 3, and a phase error is generated. The signal is transferred to the charge pump 4. Here, the output of the charge pump 4 is stable at a DC potential when the phase error is small.

  The output of the charge pump 4 is mixed with the spread signal which is the output of the D / A converter 6 by the adder 5. A signal obtained by mixing the spread signal is input to the VCO 7 and output to the outside as a clock signal subjected to spread spectrum from the spread spectrum clock output terminal 8. Further, the PLL feedback loop operates so that the spread spectrum clock signal output to the spread spectrum clock output terminal 8 is returned to the phase comparator 3 and phase-compared with the clock input terminal 2 to reduce the phase error. To do.

  The spread spectrum data is stored in the RAM 10, and the spread spectrum data is read from the RAM 10, D / A converted by the D / A converter 6, and input to the adder 5 as the spread signal. .

  The spread spectrum data stored in the RAM 10 has a function of returning to the initial state by a reset signal from the reset terminal 11, and by inputting the reset signal from the outside, the spread spectrum processing is synchronized with the external signal. Can be done. Further, from the data load terminal 12, the spread spectrum data to be stored in the RAM 10 can be inputted and rewritten.

  As the format of the spread spectrum data that can be input from the data load terminal, as shown in FIG. 2, the spread spectrum data may be obtained by performing a periodic linear phase shift such as a ramp waveform, or a white noise component. It may be PN (pseudorandom noise) data having a finite period forming a spectral component.

  The first embodiment will be specifically described with reference to FIG. FIG. 1 shows an embodiment of an analog video camera.

  As shown in FIG. 1, an analog video camera 21 according to the present embodiment generates a CCD 22 that images a subject, a CCD driver 23 that drives the CCD 22, and a basic clock (4 fsc, fsc: subcarrier frequency). The basic clock oscillator 24, the above-described SSCG1 that performs spread spectrum on the basic clock (4fsc) from the basic clock oscillator 24, and an SSG (synchronization signal) that generates various synchronization signals from the basic clock that has been spread spectrum by the SSCG1 Generator 25, a frequency divider 26 that divides the basic clock by ¼, and an S / H (sample hold circuit) 27 that samples and holds the output of the CCD 22.

In the analog video camera 21, the delay circuit 28 receives a clock from the SSG 25 and delays the S / H pulse 28 a by Δt ₁ + Δt ₂ hours and supplies it to the S / H 27.

  Further, the signal sampled and held by the S / H 27 is subjected to a contour enhancement process by a HAP (horizontal contour) enhancement circuit 30 and a VAP (vertical contour) enhancement circuit 31 after a γ correction process by a γ correction circuit 29. The adder 33 generates a Y signal.

  Further, the signal sampled and held by the S / H 27 passes through the 1 HD delay circuit 34 and the synchronization switch 35 and becomes CB and CR of color signal components. The matrix circuit 36 converts the YL signal, which is a luminance signal component, and the CR and CB signals into RGB primary color signals.

  The gain control circuit 37 is a variable gain unit for obtaining white balance with respect to the RGB three primary color signals from the matrix circuit 36, and an R′G′B ′ signal after gain control processing is calculated by the color calculation circuit 38. Then, the result is converted to a DC level by the integration circuit 39 and fed back to the Gain control circuit 37 by the WB (white balance) control circuit 40.

  By this feedback loop, control is performed so that white balance is obtained for the RGB three primary color signals from the matrix circuit 36.

  The R′G′B ′ signal after the gain control process in the gain control circuit 37 that has been subjected to the white balance process is processed in the color γ circuit 41 and converted into an R “G” B ”signal so that an appropriate color reproduction is obtained. Then, the color difference matrix circuit 42 converts the R "G" B "signal into RY and BY color difference signals.

  Further, the RY and BY color difference signals are subjected to quadrature two-phase modulation by the color modulator 43, and become color signals modulated by fsc (subcarrier frequency) from the frequency divider 26. This modulated signal is added to a reference burst signal, which will be described later, by an adder 44 to become a color signal C. The color signal C is added to the Y signal from the adder 33 by the adder 45 and output as a video signal (video).

  In the first embodiment, the basic clock of the basic clock oscillator 24 is divided by ¼ by the frequency divider 26 to generate fsc (subcarrier frequency). The reference burst signal is generated by receiving a BF (burst flag) signal from the SSG 25 by the burst gate 46 and gating the fsc (subcarrier frequency).

  Further, in the first embodiment, as described above, the basic clock oscillator 24 uses a spread spectrum clock using the SSCG 1 described in FIG.

  In other words, the SSG 25 for generating the TV synchronization signal (Sync signal, HD signal, VD signal, etc.) is operated using the spectrum spread clock, and the CCD 22 is also driven by the color modulator from the sample hold processing of the CCD 22 by the color modulator. It is processed with a spread spectrum clock even before it is received.

  In the first embodiment, the output portion of the basic clock oscillator 24 shown by the thick line in FIG. 1, the fsc (subcarrier frequency) from the frequency divider 26, and the reference burst signal from the burst gate 46 are synchronized. Only the rounding process is a signal that is completely synchronized with the basic clock oscillator 24, but other than that, the operation is performed by a clock whose spectrum is spread by SSCG1.

  In the case of the present embodiment, the synchronization signal related to the horizontal scanning such as the Sync signal is not related to the frequency interleaving relationship between the fsc color subcarrier signals, but devices such as a TV monitor and a VTR have a phase of the horizontal scanning. Since the device has an automatic correction function such as AFC or APC for deviation (jitter), there is no problem even if the frequency interleaving relationship is broken in practice.

  FIG. 4 (metal casing) and FIG. 5 (mold casing) show specific EMI measurement results of the analog video camera 21 of the present embodiment.

  4 (metal casing) and FIG. 5 (molded casing) are the same as those in FIG. 17 (metal casing) and FIG. 18 (molded casing) described in the prior art. This is a comparison of the effect by applying the form.

  FIG. 4 (metal casing) is an example when the casing is treated with a metal shield, and the shield has the same conditions as those shown in FIG. 17 (metal casing) of the conventional example.

  Compared with the conventional FIG. 17 (metal casing), the peak EMI noise in the band from about 60 MHz to 200 MHz is reduced by the spread spectrum process, and as shown in FIG. It can be confirmed that the noise level is reduced to the dark noise level.

  Further, in FIG. 5 (molded casing), the casing is a mold, and although there is no shielding effect at all, the peak EMI noise in the band from about 60 MHz to about 500 MHz is reduced by the spread spectrum processing. ing. Compared to the case of FIG. 18 (molded housing), FIG. 5 (molded housing) is improved by about 6 dB.

  Thus, in the present embodiment, when the EMI measurement results of FIG. 4 (metal casing) and FIG. 5 (molded casing) are viewed, the conventional FIG. 17 (metal casing) and FIG. Compared to the case, the peak EMI noise is diffused, and as a result, the EMI level is improved, and the EMI level can be reduced until the Class B limit line can be sufficiently cleared.

  Note that the processing performed by the S / H circuit 27 needs to be timed in accordance with the CCD signal output from the CCD 22 and needs to be completely correlated with the CCD signal.

  If this timing does not coincide with the drive signal side, the occurrence of 1 / f noise due to the phase timing shift at S / H 27 appears as random or beat-like visual noise.

  Therefore, a method for solving this beat phenomenon will be described with reference to FIG. FIG. 6 is a diagram of sample hold pulse generation according to the present embodiment.

  In the sample and hold pulse generating operation shown in FIG. 14 of the conventional example, a CCD output is generated with reference to the drive pulse, and this is received by the receiving circuit and then processed by the sample and hold circuit.

  In the conventional sample and hold process, a signal generated with the A drive pulse as a reference has a time delay of Δt1 and Δt2. Therefore, the signal is processed with a drive pulse B that is a reference pulse next to the A drive pulse (normal synchronization processing circuit). ). Therefore, as described in FIG. 14, the sample and hold circuit generates the sample and hold pulse based on the B drive pulse.

  In the circuit shown in FIG. 13 of the conventional example, if the sample and hold pulse is processed at the timing of the synchronization signal such as the A drive signal or the B drive signal as shown in FIG. 14, there is no influence on the image quality and there is no problem. It was.

  However, when each drive signal is spread spectrum as in this embodiment, each CCD output itself is subjected to spread spectrum modulation, so that each sample hold signal also corresponds to the drive signal. It is necessary to process at the timing. If this is not done, image noise will occur.

  FIG. 6A shows an SS modulated (spread spectrum modulated) drive pulse, FIG. 6B shows an SS modulated CCD output signal, FIG. 6C shows an S / H27 received signal, and FIG. Shows an SS-modulated sample hold pulse.

  In this embodiment, in FIG. 6, the CCD signal generated from the drive signal modulated by the “A pulse modulation component” of the drive pulse is the SS-modulated sample hold (modulated by the “A pulse modulation component”). S / H) is processed by pulse (d).

  Therefore, in the present embodiment, the drive pulse is delayed by the delay circuit 28, thereby associating the modulation components of the drive signal with the CCD signal and the sample hold signal.

Second embodiment:
7 and 8 relate to the second embodiment of the present invention, FIG. 7 is a block diagram showing the configuration of a digital video camera as a video device, and FIG. 8 is a modification of the digital video camera of FIG. It is a block diagram which shows the structure of an example.

  Since the second embodiment is almost the same as the first embodiment, only different points will be described, and the same components are denoted by the same reference numerals and description thereof will be omitted.

  Next, a second embodiment will be described with reference to FIG. FIG. 7 shows an embodiment of a digital video camera.

  As shown in FIG. 7, in the digital video camera (digital camera) 51 of this embodiment, the signal sampled and held by the S / H circuit 24 is output to the signal input of the A / D converter 53 via the LPF 52. Is done. The digital output of the A / D converter 53 is output to the input of a DSP (digital signal processor) 54.

  Further, the output of the DSP 54 is output to the D / A converter 55, and Y (luminance signal) and RY / BY signals are output to the encoder 58 via the three LPFs 56. Here, the LPF 56 is connected to each channel of the D / A converter 55.

  The encoder 58 receives Y (luminance signal) and RY / BY signals from the three LPFs 56, and balance-modulates the color difference signal with fsc (subcarrier signal) 59 to generate a C signal and a Y signal. At the same time, the adder 60 adds the C signal and the Y signal to output a video.

  The A / D converter 53, the DSP 54, and the D / A converter 55 are controlled by a system clock that is a clock signal generated by the SSG 25. A sync signal 61 such as Sync or BF from the SSG 25 is a sync signal for signal processing input to the encoder 58 and the DSP 54.

  In the other embodiments, the analog signal processing circuit of the first embodiment is changed to digital signal processing using the DSP 54. That is, the processing of the output signal of the CCD 22 to finally form a video signal is the same as in the first embodiment and the second embodiment.

  In the second embodiment, the output of the S / H 27 is connected to the signal input of the A / D converter 53 via the LPF 52 for removing unnecessary harmonic components before A / D conversion.

  The signal of the S / H circuit 27 digitally converted by the A / D converter 53 is subjected to video signal processing shown by the analog circuit in FIG.

  The digital signal calculated from the output of the DSP 54 is converted into Y (luminance signal) and RY / BY signal by the D / A converter 55, the high-frequency signal by AD conversion is removed by the LPF 56, and finally the encoder 58 A typical video signal is created.

  In the second embodiment, similarly to the first embodiment shown in FIG. 1, the subcarrier signal fsc uses a signal that is simply frequency-divided by the frequency divider 26 without passing through the SSCG 1. ing.

  All signal processing other than generating this subcarrier signal fsc (CCD drive, sample hold, A / D conversion, DSP signal processing, D / A conversion, use of System Clock, use of sync signals such as Sync, BF, etc.) It is generated using a clock signal that has been spread spectrum using SSCG1.

  As described above, in the second embodiment, similarly to the first embodiment, since the spectrum is spread to signals other than the subcarrier signal fsc, digital signal processing with improved EMI level can be realized.

  FIG. 8 shows a configuration of the modification of the second embodiment, and the method of creating fsc (subcarrier frequency) is different from that of the second embodiment.

  In this modification, the 4fsc signal is subjected to spread spectrum processing by the SSCG 1 to generate an SS-4fsc signal. The frequency is directly divided by the frequency divider 26 to create an SS-fsc.

  Furthermore, in this modification, INV. Through the SSCG unit 61, the spread spectrum processed SS-fsc signal is despread and an unscread spectrum fsc (subcarrier frequency) is generated.

  In order to execute this despreading processing, INV. Is used corresponding to the spreading processing of SSCG25 using SSCG Reset signal 62 from SSG25. The SSCG 61 is being reset.

  Specifically, a process of correcting the fsc (subcarrier frequency) signal so as to eliminate the phase shift of fsc (subcarrier frequency) is performed.

  In the configuration of this modified example, the synchronization signal serving as the EMI noise source is the 4fsc signal output from the basic clock oscillator 24, the INV. Only the fsc (subcarrier frequency) output from the SSCG unit 61 and a portion that becomes a noise source can be laid out in a small size. In addition, since all other signal processing is performed using a signal subjected to spread spectrum processing, there is an effect that a circuit configuration with improved EMI level can be simplified as compared with the second embodiment.

  Also in the modified example, as in the second embodiment, digital signal processing with improved EMI level can be realized because spectrum spreading is performed on signals other than fsc (subcarrier frequency).

Third embodiment:
FIG. 9 is a configuration diagram showing a configuration of a medical electronic endoscope apparatus which is a video apparatus according to the third embodiment of the present invention.

  Since the third embodiment is almost the same as the second embodiment, only different points will be described, and the same components are denoted by the same reference numerals and description thereof will be omitted.

  In the medical electronic endoscope apparatus 71 according to the third embodiment, as shown in FIG. 9, the purpose of processing the signal of the CCD 22 to finally form a video signal is that of the first and second embodiments. The third embodiment is characterized by being divided into a patient circuit and a secondary circuit.

  Here, an insulating circuit (photocoupler, insulating transformer, etc.) 72 separates the patient circuit and the secondary circuit.

  A flow in which a signal from the CCD 22 is processed by the S / H circuit 27 and is input to the DSP 54 via the A / D converter 53 and a Y signal, an RY / BY signal, etc. are output from the D / A converter 55. Is the same as in the second embodiment.

  In the third embodiment, a PLL circuit is formed in order to generate the S / H pulse 28a '. That is, a PLL loop is formed from the PLL phase comparator (PC) 73 to the PLL charge pump (CP) 74, the PLL VCO 75, and the PLL frequency divider (1 / N circuit) 76a. The output of the S / H pulse divider (1 / N circuit) 76b is used as the S / H pulse 28a '.

  The S / H pulse divider (1 / N circuit) 76a divides the output of the PLL VCO 77. In this PLL circuit unit, SSCG 1 is provided in the PLL loop, and a signal subjected to spread spectrum processing is input to a PLL phase comparator (PC) 73. An SSCG Reset signal is input from the SSG 25 to the Reset terminal 11 of the SSCG 1 via the Delay circuit 78.

  On the other hand, the PLL circuit arranged in the secondary circuit (= non-insulated circuit) includes a PLL phase comparator (PC) 73, a PLL charge pump (CP) 74, a PLL VXO75, and a PLL frequency divider. (1 / N circuit) 76a is used to supply a reference clock to a DSP unit comprising an A / D converter 53, a DSP 54, and a D / A converter 55 for the output of the PLL VCO 75.

  In addition, an SSG (synchronization signal generator) 79 arranged in the secondary circuit (= non-insulated circuit) supplies a synchronization signal (Sync, HD, VD, etc.) conforming to the television signal format to the DSP unit to operate. This is the reference signal.

  In the present embodiment, the CCD 22 is driven using a signal subjected to spread spectrum processing by the SSCG 1.

  This is the same as in the first and second embodiments. This reduces the EMI level when the CCD is driven.

  In particular, the patient circuit (= insulation circuit) is a floating portion and a floating circuit portion with respect to the earth ground because the electrical safety is improved by reducing the leakage current. This conventional floating part is a noise source part, and as a countermeasure against EMI, it is necessary to cover the patient circuit (= insulation circuit) with a metal BOX shield as much as possible and to insert a ferrite core or the like in the signal line where EMI noise occurs.

  In this embodiment, the EMI noise component is reduced by causing the patient circuit (= insulation circuit), which is the floating portion, to operate using a signal that has been subjected to spread spectrum processing.

  The Reset signal from the Delay circuit 78 is input to the Reset terminal 11 of the SSCG 1. This Reset signal is subjected to diffusion processing in association with the drive signal of the CCD 22 subjected to spectrum spread processing by the SSCG 1 on the CCD driving side.

  In the first embodiment, the correspondence between the modulation components of the drive signal, the CCD signal, and the sample hold signal is related by the delay means using the delay circuit. As other means, as shown in the present embodiment, The SSCG Reset signal is used to forcibly associate the SSCG 1 for generating the sample and hold pulse with the Reset terminal 11 to associate the drive signal with the modulation component of the CCD signal and the sample and hold signal.

Fourth embodiment:
FIG. 10 is a block diagram showing the configuration of the video equipment according to the fourth embodiment of the present invention.

  A fourth embodiment will be described with reference to FIG. In FIG. 10, the portion denoted by reference numeral 81 is a video camera unit, which is the same digital camera as the conventional example shown in FIG. A portion indicated by reference numeral 82 is an image processing unit that is not shielded, and is connected to the video camera unit 81.

The difference from the conventional example shown in FIG. 13 is that the video camera unit 81 is entirely covered by the shield case 81a.
The image processing unit 82 and the video camera unit 81 are connected by a digital data bus 83 from the DSP 208. Further, 4 fsc or a pixel clock is output from the video camera unit 81 to the SSCG 1 of the image processing unit 82.

  The digital data bus 83 is latched by a DFF (latch circuit) 84, becomes an SS digital data bus 85, and is transmitted to the image processor 86 in the next stage.

  In the image processing unit 82, 4 fsc or pixel clock is subjected to spectrum spread processing by SSCG 1 and output as SS-CLK 87.

  In the video camera unit 81, all circuit processes are synchronized. As shown in the first or second embodiment, if the spread spectrum process is performed, the EMI level can be reduced. However, the video camera unit 81 is a single hybrid IC or a one-chip signal processing circuit and can be downsized. In order to achieve this, the same circuit configuration as in the conventional example is adopted.

  The video camera unit 81 is covered with a shield case 81a to reduce the noise level in order to reduce the EMI level.

  In the present embodiment, the video camera unit 81 is not subjected to spread spectrum processing, but the image processing unit 82 is processed by SS-CLK 87 that has been subjected to spread spectrum processing by the internal SSCG 1. A digital data bus 83 input / output from the DSP 54 is processed by a DFF (latch circuit) 84 based on the timing of SS-CLK 87 to become an SS digital data bus 85.

  The SS digital data bus 85 is a bundle of digital data signals with a reduced EMI level.

  As described above, in the present embodiment, the unit having a large EMI level shown in the conventional example is processed using the clock subjected to the spread spectrum processing in the processing unit to be connected, and thus the same effects as those in the above embodiments. Can be obtained.

  Note that the SSCG 1 of the image processing unit 82 shown in the fourth embodiment may be placed at another installation location such as the position of the reference numeral 88 indicated by a broken line in the video camera unit 81. Similarly, a DFF (latch circuit) 84 may be provided in the video camera unit 81.

  In the fourth embodiment, the shield case 81a is applied to the video camera unit 81. However, when the video camera unit 81 is integrated by the advancement of semiconductor design and configured as one chip, the shield case is provided on the substrate. May be. In addition, when the video camera unit 81 is configured as a single chip due to advances in semiconductor design, low power consumption is also achieved, so the EMI level decreases as power consumption is reduced, so the shield case is removed. May be.

Fifth embodiment:
FIG. 11 is a block diagram showing the configuration of the video equipment according to the fifth embodiment of the present invention.

  Since the fifth embodiment is almost the same as the second embodiment, only different points will be described, and the same components are denoted by the same reference numerals and description thereof will be omitted.

  Next, a fifth embodiment will be described with reference to FIG. The fifth embodiment is an example of a display such as a TV, an FMD (face mount display), a projector, or a printer device 91, and a recording device 92 of a memory card or a magnetic recording device connected thereto.

  A video signal such as a composite signal is input to the display or printer device 91 from the video input terminal 93, the Y signal and the C signal are separated by a YC separator (Sep) 94, and Y 0, U 0, V 0 are separated by a decoder 95. Separated into signals.

  The C signal generates a clock fsc synchronized with the video input terminal 93 by a PLL circuit indicated by a PLL phase comparator (PC) 73, a PLL charge pump (CP) 74, and a PLL VCO 75.

  The LPF 96 that filters the signal from the decoder 95 is a band limiting filter for preventing aliasing before inputting the Y0, U0, and V0 signals to the A / D converter 97. The A / D Y2, U2, and V2 signals are processed by the digital process circuit 98 to become R0, G0, and B0 signals, which are digital signals corresponding to the input signal format of the LCD 99 at the subsequent stage.

  The R0, G0, and B0 signals are converted into analog signals by the D / A converter 100 and output to the LCD 99 as R1, G1, and B1 signals. Here, the lens 101 is an optical system that forms an image of a display medium such as the LCD 99, and provides an optimal image to the observer or the print medium 102.

  The SSCG 1 processes the reference clock (fsc) and outputs SS-fsc.

  The recording device 92 is provided with, for example, a magnetic recording medium (memory) 103 as recording means, and signals R2, G2, and B2 that match the Y1, U1, and V1 signals with the signal format of the recording device 92. Output as a signal.

  In the present embodiment, the video input terminal 93 is YC separated by a YC separator (Sep) 94, decoded by a decoder 95, and converted into a YUV signal. The reference clock required for this decoding is a PLL circuit composed of a PLL phase comparator (PC) 73, a PLL charge pump (CP) 74, a PLL VCO 75, and a PLL frequency divider (1 / N) 76a. Is occurring.

  In the present embodiment, the decoded YUV signal is A / D converted based on the SS-fsc clock subjected to spread spectrum processing by SSCG 1, and then digital processing is performed by the digital process circuit 98. Based on this SS-fsc clock, it is displayed on a display such as LCD 99 or a printer driver.

  In addition, image information is recorded on the magnetic recording medium 103 such as a memory card by the recording device 92 based on the SS-fsc clock.

  In this embodiment, since “signal processing relating to display” and “signal processing relating to recording” are performed using the SS-fsc clock that has been subjected to spread spectrum processing after being digitized, the level of EMI interference waves is greatly increased. Can be less.

  Due to this effect, the display or printer device 91 (FMD, laser beam driver, etc.) provided with the LCD 99 or the like can reduce the EMI level without using a shielding material or the like, thereby realizing a small, light and inexpensive display device. ing. Also, the recording device 92 does not require a shielding material and can be manufactured thinly and inexpensively.

  The recording device 92 may be detachable from a display provided with the LCD 99 or the like or the printer device 91.

Sixth embodiment:
FIG. 12 is a block diagram showing the configuration of the video equipment according to the sixth embodiment of the present invention.

  This embodiment is an application example to a mobile phone with image function, PHS, and the like as shown in FIG.

  The cellular phone with image function PHS 121 includes an antenna 122, an RF unit 123, an IF (intermediate frequency) unit 124, a baseband unit 125, an audio processing unit 126, and an image processing unit 127.

  These blocks are divided according to the operating frequency required for each block, and the RF unit 123 is configured by an RFSW (switch) 131 for switching transmission, a power amplifier 132, and a preamplifier 132 for reception.

  The IF (intermediate frequency) unit 124 includes a transmission mixer 141, a transmission quadrature modulator 142, a reception mixer 143, an IF amplifier 144, and a reception quadrature demodulator 145.

  On the other hand, in the baseband unit 125, the TDMA 151 (or CDMA baseband processing unit) 161 mainly performs a channel codec that rearranges signals in accordance with a signal format such as TDMA or CDMA, and further includes a modulator D / A converter 162. The baseband unit also performs differential modulation / demodulation, error correction processing, and encoding processing.

  The audio processing unit 126 takes in audio from the microphone 171 and takes in an audio signal with the audio A / D converter 172. The speaker 173 receives a signal from the audio D / A converter 174 and outputs an audio signal. The audio codec 175 performs audio signal band compression and audio encoding and decoding corresponding to each country format (PHS, GSM, IS-54, etc.).

  The image processing unit 127 incorporates the digital video camera 81 described in the second embodiment. Further, the display or printer apparatus 91 subjected to the SS diffusion processing described in the fifth embodiment is incorporated to display an image.

  The operation of the sixth embodiment will be described in detail below. In the sixth embodiment, an example of a mobile phone / PHS with an image function is shown.

  First, the reception operation will be described. In the sound reception operation, the signal received by the antenna 122 is amplified by the preamplifier 133 of the RF unit 123 and detected and demodulated by the IF (intermediate frequency) unit 124.

  The baseband unit 125 performs channel codec and the audio processing unit 126 performs audio decoding.

  In the image receiving operation, the basic data flow is the same as the sound processing up to the baseband unit 125, but when image data is received, the format of MPEG2, 4 or the like is demodulated.

  The display or printer device 91 of the image processing unit 126 is an image display device in which the EMI level is reduced by SS diffusion, and displays a received image.

  Next, the transmission operation will be described. The speech-coded signal input by the speech processing unit 126 is converted by the baseband unit 125 to match the transmission format, modulated by the IF (intermediate frequency) unit 124, amplified by the RF unit 123, and the antenna 122. Is sent from.

  In the image transmission operation, the digital video camera 81 in the image processing unit 127 captures an observation image, and the baseband unit 125 converts it into an image transmission format such as MPEG2, 4 or the like.

  The subsequent steps are the same as those after the IF (intermediate frequency) unit 124 shown in the voice transmission operation.

  In the sixth embodiment, the image processing unit 127 performs signal processing by realizing a low EMI level using the digital video camera 81 in capturing an image.

  Also. As for the image display, the EMI level is reduced by SS diffusion using the display or the printer device 91.

  Normally, cellular phones, PHSs, etc. handle minute power during reception and handle large power during transmission. The level difference between the transmission / reception blocks inside a small portable device is about 100 dB, and preventing a mutual interference between the transmission / reception blocks was a major design problem.

  In the present embodiment, since the SS transmission processing is applied to the image transmission / reception unit and a low EMI level image capturing or image display or printing device is provided, interference from the image processing unit 127 to the audio processing unit 126 is reduced. There is an effect that the error rate of the data is improved and that the sound processing unit 126 further reduces the interference with the image processing unit 127 and the noise on the screen is reduced.

[Appendix]
(Additional Item 1) Video processing means for performing video signal processing using a first clock subjected to spread spectrum processing;
A video apparatus comprising: a video signal generation unit configured to generate a video signal using a second clock not subjected to spread spectrum processing.

(Additional Item 2) The video device according to Additional Item 1, wherein the video processing means using the first clock performs signal processing of a video camera.

(Additional Item 3) The video apparatus according to Additional Item 1, wherein the video processing means using the first clock performs signal processing of an electronic endoscope.

(Additional Item 4) The video device according to Additional Item 1, wherein the video processing means using the first clock performs image processing signal processing.

(Additional Item 5) The video device according to Additional Item 1, wherein the video processing means using the first clock performs signal processing of an image display device.

(Additional Item 6) The video equipment according to Additional Item 1, wherein the video processing means using the first clock performs signal processing of an image recording apparatus.

(Additional Item 7) The video device according to Additional Item 1, wherein the video processing means using the first clock performs signal processing of a portable communication tool.

(Additional Item 8) The present invention further includes spreading code holding means for inputting and holding a spread code of the spread spectrum processing applied to the first clock as arbitrary spreading information from the outside. Video equipment.

(Additional Item 9) The second clock that has not been subjected to spread spectrum processing is a clock that has not been subjected to spread spectrum processing, or a clock that has been subjected to inverse spread spectrum processing after being subjected to spread spectrum processing. The video equipment according to Supplementary Item 1.

(Additional Item 10) In the signal processing of the video camera,
The video equipment according to item 2, wherein the sample hold processing of the spread spectrum image pickup device is processed by a sample hold pulse correlated with the spread spectrum image pickup device signal output.

1 is a configuration diagram showing the configuration of an analog video camera that is a video device according to a first embodiment of the present invention; The block diagram which shows the structure of SSCG of FIG. Explanatory drawing explaining the effect | action of the spread spectrum process by SSCG of FIG. The figure which shows the result of the EMI measurement at the time of covering the video camera of FIG. 1 with the metal housing The figure which shows the result of the EMI measurement when the video camera of FIG. 1 is covered with a mold housing. The figure explaining the sample hold signal of FIG. The block diagram which shows the structure of the digital video camera which is a video equipment concerning the 2nd Embodiment of this invention FIG. 7 is a block diagram showing the configuration of a modification of the digital video camera of FIG. The block diagram which shows the structure of the medical electronic endoscope apparatus which is a video equipment which concerns on the 3rd Embodiment of this invention. The block diagram which shows the structure of the video equipment which concerns on the 4th Embodiment of this invention. The block diagram which shows the structure of the video equipment which concerns on the 5th Embodiment of this invention The block diagram which shows the structure of the video equipment concerning the 6th Embodiment of this invention Configuration diagram showing the configuration of conventional video equipment The figure explaining the sample hold signal of the video equipment of FIG. The figure explaining the electromagnetic wave radiation level of the video equipment of FIG. The figure which shows an example of the electromagnetic wave radiation countermeasure of the imaging device of FIG. The figure which shows the result of the EMI measurement at the time of covering the video equipment of FIG. 13 with the metal housing The figure which shows the result of the EMI measurement at the time of covering the video equipment of FIG. 13 with the mold housing | casing

Explanation of symbols

1 ... SSCG
21 ... Video camera 22 ... CCD
23 ... CCD driver 24 ... Basic clock oscillator 25 ... SSG
26 ... Frequency divider 27 ... S / H

Claims (4)

Video processing means for performing video signal processing using a first clock subjected to spread spectrum processing;
An electronic endoscope apparatus comprising: a video signal generation unit that generates a video signal using a second clock that has not been subjected to spread spectrum processing.   The electronic endoscope apparatus according to claim 1, wherein the video processing unit drives an imaging element of the electronic endoscope apparatus using the first clock.   The electronic endoscope apparatus according to claim 1, wherein the electronic endoscope apparatus is a medical electronic endoscope apparatus. Furthermore, it has a rewritable memory for storing spread spectrum data for the spread spectrum process,
The electronic endoscope apparatus according to any one of claims 1 to 3, wherein the spread spectrum processing uses the spread spectrum data by reading from the rewritable memory.

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