JPH0654232A - Digital signal processing camera - Google Patents

Abstract

PURPOSE:To reduce the circuit scale and also to reduce the power consumption. CONSTITUTION:An image enhancement circuit 3 receives the signals Ge and Ro having 1/2-shifted phases from an image pickup processing circuit 1 and produces the contour correction signals of both low and high clock rates. An LPF 4 and the interpolation filters 5 and 6 make even the phases of signals Ge, Ro and Bo, and a color correction circuit 7 corrects the colors of the signals having the even phases. The contour correction signal of a low clock rate is added to the signals Ge, Ro and Bo having the even phases and then the Gamma/Nu correction is applied to these signals. Then the contour correction signal of a low clock rate is applied again to the signals Ge, Ro and Bo respectively. Meanwhile the contour correction signal of a high clock rate is added to the signal obtained by applying the up-conversion to the luminance signal Y received from a matrix circuit 17.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing camera for correcting the contour of an image by digital signal processing.

[0002]

2. Description of the Related Art Conventionally, a video camera is equipped with a contour correction circuit. This contour correction circuit is composed of a delay circuit and an addition / subtraction circuit, and is used for compensating the response deterioration of the image pickup device in the video camera and for enhancing the sharpness.

On the one hand, the video signal of this video camera is output as a camera output from a view finder (VF: View Finde).
r) or a monitor, and on the other hand, it is recorded on a video tape recorder (hereinafter referred to as VTR). this house,
The video signal recorded on the VTR has a frequency band of 5 to 6M.
However, the video signal output from the camera is required to have a frequency band of 10 MHz or more (horizontal resolution 800 TVL), since it is a standard for the quality of the camera to have a high resolution.

[0004]

By the way, the above-mentioned VTR
The clock rate of the video signal for frequency (frequency band 5 to 6 MHz) is 13.5 MHz or 4f _sc (f _sc is a subcarrier frequency). On the other hand, the clock rate of the video signal for the camera output (the frequency band is 10 MHz or more) requires that the video signal for the camera output has a high resolution, and thus the clock rate of the video signal for the VTR is required. 27 MHz and 8 f _sc are required.

However, conventionally, there is only one system for a contour correction signal (hereinafter referred to as a detail signal) for performing the contour correction, and 27 MHz or the like so that both the VTR video signal and the camera output video signal can be processed. It was 8 f _sc . Therefore, if the gain of the contour correction is changed, both the video signal for VTR output and the video signal for camera output change at the same time. For example, there is a demand for changing only the contour correction amount of the VTR video signal. I can't answer.

The present invention has been made in view of the above circumstances, and it is possible to separately prepare contour correction signals for a video signal for VTR output and a video signal for camera output, and further for this VTR output. It is an object of the present invention to provide a digital signal processing camera capable of performing contour correction of a video signal output from a camera without affecting contour correction of the video signal.

[0007]

A digital signal processing camera according to the present invention is a digital signal processing camera for correcting an image using a contour correction signal, wherein the contour correction signal is formed into two systems depending on whether the clock rate is high or low. , The low clock rate contour correction signal corrects the frequency characteristics of the video signal recorded on the video tape recorder in addition to the input signal, and the high clock rate contour correction signal adds the low clock rate contour correction signal to the input signal. The above problem is solved by the feature that the frequency characteristic of the video signal output from the camera is corrected in addition to the signal obtained by converting the added signal into a signal of high clock rate.

Here, the bands of the low-frequency contour correction signal and the high-frequency contour correction signal do not interfere with each other.

Further, in the digital signal processing camera according to the present invention, the encoding process is performed by the digital encoder to obtain the video signal output from the camera.

Further, in the digital signal processing camera according to the present invention, the encoding process is performed by the analog encoder to obtain the video signal output from the camera.

[0011]

In the digital signal processing camera according to the present invention,
A contour correction signal with a low clock rate is added to the input signal to correct the frequency characteristics of the video signal recorded on the video tape recorder, and a contour correction signal with a high clock rate adds the contour correction signal in the low range to the input signal. This signal is added to the signal converted into a high clock rate signal to correct the frequency characteristics of the video signal of the camera output, and since the bands of the contour correction signals of these two systems do not interfere with each other, the video tape recorder was reproduced. It is possible to perform contour correction that is optimal at times, and further it is possible to perform contour correction on the video signal output from the camera without affecting the contour correction of the video tape recorder.

Further, in the digital signal processing camera according to the present invention, the video signal of the camera output is obtained by performing the encoding process by the digital encoder.

Further, in the digital signal processing camera according to the present invention, the video signal of the camera output is obtained by performing the encoding processing by the analog encoder.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a digital signal processing camera according to the present invention will be described below with reference to the drawings.

FIG. 1 is a block circuit diagram showing an embodiment of a digital signal processing camera according to the present invention.

In FIG. 1, the image pickup processing circuit 1 is composed of an image pickup element such as a CCD, an amplifier, an A / D converter and the like. The signal G _e , the signal R ₀ , and the signal B ₀ which are the three primary color digital signals obtained by the image pickup processing circuit 1 are supplied to the preprocessor 2.

[0017] The preprocessor 2 signal is corrected shading etc. in G _e, the signal R _0, the low-pass filter with the signal G _e of the signal B ₀ is supplied to the image enhancement circuit 3 (hereinafter, referred to as LPF) 4 Is supplied to. The signal R ₀ is supplied to the image enhancing circuit 3 and the interpolation filter 5. Further, the signal B ₀ is supplied to the interpolation filter 6.

The signal G _e which has the same frequency characteristics as the signals R ₀ and B _{0 by} the low pass filter 4 and the signal R which has been matched with the phase of the signal G _{e by} the interpolation filter 5.
₀ and the signal B ₀ matched with the phase of the signal G _{e by} the interpolation filter 6 are supplied to the color correction circuit 7.

The signals G _e , R _e , and B _e color-corrected by the color correction circuit 7 are supplied to adders 8, 9, and 10.
The low clock rate (18 in this case) output from the image enhancing circuit 3 is supplied to the adders 8, 9 and 10.
(MHz) detail signal is also provided. And
The color corrected signals G _e, R _e, B _e, in the adder 8, 9, 10, so that the detail signal of the low clock rate is added to each.

The addition output signal from the adder 8 is supplied to a gamma / knee correction circuit 11 which performs gamma correction and knee processing. Similarly, the addition output signal from the adder 9 and the addition output signal from the adder 10 are supplied to the gamma / knee correction circuits 12 and 13.

These gamma / knee correction circuits 11, 12,
13 data signals processed signals are added by adders 14, 15, 1
6 is supplied. The low clock rate detail signal output from the image enhancing circuit 3 is again supplied to the adders 14, 15 and 6. Then, the low clock rate detail signal is added to the output signals from the gamma / knee correction circuits 11, 12, and 13 in the adders 14, 15, and 16.

The addition outputs from the adders 14, 15 and 16 are supplied to the matrix circuit 17. The luminance signal Y of the luminance signal Y and the color difference signals RY and BY produced by the matrix circuit 17 is supplied to an up-converter circuit 18 which converts the input signal into a high clock rate signal. Both are also supplied to a rate converter 21 which performs rate conversion of the input signal into a predetermined frequency.

The up converter circuit 18 converts the clock rate of the luminance signal Y from 18 MHz to 36 MHz. The luminance signal Y converted to a high clock rate by the up converter circuit 18 is supplied to the adder 19. The high clock rate (36 MH in this case) output from the image enhance circuit 3 is supplied to the adder 19.
The detail signal of z) is also provided. The high clock rate detail signal is added to the luminance signal Y of 36 MHz in the adder 19.
The addition output from the adder 19 is supplied to the encoder 20.

The color difference signals RY and BY produced by the matrix circuit 17 are the encoder 2
In addition to being supplied to 0, it is also supplied to the rate converter 21. The encoder 20 generates a luminance signal Y having a high clock rate of 36 MHz and color difference signals RY and BY having a low clock rate of 18 MHz to generate a D / A converter 22.
And 23.

The D / A converters 22 and 23 are connected to output terminals 24 and 25 for camera output.

The rate converter 21 has a capacity of 18M.
Hz is converted to _13. 5 MHz used in the VTR system. Then, the rate converter 21 is connected to a video recording / playback Y terminal 26, an RY terminal 27, and a BY terminal 28. Further, the rate converter 21 is supplied with a clock of 13.5 MHz and a reproduction ON / OFF signal from the VTR via the input terminals 29 and 30, respectively. Further, the matrix circuit 17 includes
A reproduction on / off signal from the VTR is supplied via the input terminal 30.

The operation of each section of the present embodiment having such a configuration will be described below.

First, the image pickup processing circuit 1 converts the light incident through a lens (not shown) into image signals R, G and B,
These signals are A / D converted to obtain the three primary color digital signals G _e , R
Output as ₀ and B ₀ . Here, this imaging processing circuit 1
The pixels constituting the CCD are shifted, and the green digital signal G _e and the red digital signal R ₀ and the blue digital signal B ₀ are out of phase with each other by 1/2 pitch. Then, A / D conversion is performed with the phase still being shifted, and the signals G _e , R ₀ , and B ₀ are supplied from the imaging processing circuit 1 to the preprocessor 2.

The preprocessor 2 corrects the defectiveness of the CCD constituting the image pickup processing circuit 1 and the shading distortion which affects white and black due to variations in the sensitivity of the CCD. Digital data G _e and R ₀ which have been subjected to so-called pseudo-correction by the preprocessor 2
And B ₀ are still in a state of being out of phase by ½. G
_e is supplied to the image enhancing circuit 3 and LP
It is also supplied to F4. R _{0 is} also supplied to the image enhancing circuit 3 and the interpolation filter 5. Further, B ₀ is supplied to the interpolation filter 6.

The image enhancing circuit 3 corrects the contour portion of the image on the video signal to improve the apparent resolution. In this embodiment, G _e and R with the phase shifted by ½. _{With 0} as an input, a delay signal, a comb filter, a high-pass filter, a multiplier, etc. are used to distinguish and output a detail signal for camera output and a detail signal for VTR.

FIG. 2 shows a block circuit diagram of the image enhancing circuit 3.

In FIG. 2, a read clock rate 18 MH output from the image pickup processing circuit 1 is input to the input terminal 51.
The z signal G _e is input. Further, the read clock rate 1 output from the image pickup processing circuit 1 is input to the input terminal 52.
The 8 MHz signal R ₀ is input.

The signal G _e via the input terminal 51 is 1
2H delayed signal G _2H through H delay circuit 53 and the 1H delay circuit 54, is supplied to the 1H is divided into delayed signal G _1H and undelayed signal G _0H comb filter 57 through the 1H delay circuit 53. In addition, the signal R _e via the input terminal 52 also receives the 1H delay circuit 55 and the 1H delay circuit 5
6, the signal R 2H delayed by _2H and the 1H delay circuit 55
The signal R _1H delayed by _1H and the signal R _0H not delayed are separated and supplied to the comb filter 57.

The comb filter 57 has the read clock rate of 18 MHz and the delayed signals G _2H , G _1H and R.
_2H , R _1H and the _undelayed signals G _0H , R _0H ,
A signal having a frequency of 36 MHz is obtained. The 36 MHz signal from the comb filter 57 is a high-pass filter (hereinafter referred to as HPF) 58 and the rate converter 5
9 is supplied.

The 36 MHz signal that has passed through the HPF 58 is supplied to the multiplier 61 that operates as a gain adjuster, and is multiplied by the control signal via the input terminal 63. The output of the multiplier 61 is a horizontal detail signal, which is added to the vertical detail signal supplied from the input terminal 67 by the adder 65 and output from the output terminal 69 as a high clock rate (36 MHz) detail signal for camera output. It

The rate converter 59 has a capacity of 36M.
Convert the Hz signal to 18 MHz. The output signal from the rate converter 59 is supplied to the HPF 60. The 18 MHz signal passed through the high pass filter 60 is
It is supplied to a multiplier 62 which operates as a gain adjuster and is multiplied by a control signal via an input terminal 64. This multiplier 62
Is a horizontal detail signal, which is added to the vertical detail signal supplied from the input terminal 68 by the adder 66 and output from the output terminal 70 as a low clock rate (18 MHz) detail signal for VTR output.

In FIG. 1, from the preprocessor 2, signals G _e , R ₀ , whose phases are shifted by 1/2 are kept,
B ₀ is supplied to the LPF 4, the interpolation filter 5, and the interpolation filter 6. The interpolation filters 5 and 6 are the signals R ₀ and B _0.
To the phase of G _e . Further, the LPF 4 makes the frequency characteristics of the signal G _e and the signals R ₀ and B _o the same. Therefore, the signals G _e and the signals R ₀ and B ₀ having different phases before being supplied to the LPF 4 and the interpolation filters 5 and 6 are
By passing through the LPF 4 and the interpolation filters 5 and 6, the signals R _e , G _e , and B _e having the same phase are obtained.

The color correction circuit 7 is a circuit for correcting the color of the video signal output from the CCD constituting the image pickup signal processing circuit 1. Specifically, the signal R with the same phase is
_{e, G e, G e -B} e with B _e, seeking signals such as G _e -R _e are summed for color correction.

The adders 8, 9, and 10 add the image enhancement circuit 3 to the G _e , R _e , and B _e from the color correction circuit 7.
The VTR detail signals supplied from the above are added.
The gamma / knee correction circuits 11, 12, and 13 perform gamma correction and knee correction on the signal to which the VTR detail signal is added.

The gamma / knee correction circuit 11, 12, 1
The gamma correction performed by 3 is to correct the non-linear relationship between the grid signal voltage of the color picture tube and the light emission output on the camera side, and the knee process is a white compression process. The signals which have been subjected to the gamma correction and knee processing by the gamma / knee correction circuits 11, 12 and 13 are added again to the adders 14 and 1, respectively.
The VTR from the image enhancing circuit 3 at 5 and 16
The detail signal for is added. And adder 1
Output signals from 4, 15 and 16 are supplied to the matrix circuit 17.

[0041] The matrix circuit 17 produces a digital video signal G _e supplied, R _e, the luminance signal from the B _e Y and color difference signals R-Y, the B-Y. Then, the luminance signal Y is supplied to the up converter circuit 18. The color difference signals RY and BY are supplied to the encoder circuit 20 and the rate converter circuit 21, respectively.

The up-converter circuit 18 converts the clock rate 18 MHz of the luminance signal Y into 36 MHz. Then, the detail signal for camera output from the image enhancing circuit 3 is added to the luminance signal Y having the clock rate of 36 MHz by the adder 19.

The encoder circuit 20 has a luminance signal Y of 36 MHz to which a detail signal for camera output is added and color difference signals RY and BY from the matrix circuit 17.
The signal is encoded into, for example, an NTSC-compliant video signal. Then, it is converted back to an analog signal by the D / A converter 22 and supplied to the viewfinder or the like from the output terminal 24, or converted back to an analog signal by the D / A converter 23 and output from the output terminal 25 to a composite video signal or a test video. It is output as a signal.

The rate converter circuit 21 receives the clock rate 18 MH supplied from the matrix circuit 17.
The luminance signal Y of z and the color difference signals RY and BY are converted into signals having a clock rate of 13.5 MHz suitable for the VTR and output to the head portion of the VTR via the output terminals 26, 27 and 28.

Next, the overall operation of this embodiment will be described with reference to FIG. FIG. 3 is a diagram showing how the spectrum characteristic of each part used in this embodiment changes.

First, C in the image pickup processing circuit 1 of the present embodiment.
Since the read clock of the CD is 18 MHz, the baseband signal of the signal G is as shown by the solid line in (a) of FIG. Similarly, the baseband signals of the signals R and B are as shown by the solid line in FIG. Where 1
Since sampling is performed at 18 MHz for an 8 MHz signal, aliasing (folding noise) shown by broken lines in FIGS. 3A and 3B occurs. FIG. 3B
The aliasing shown in FIG. 3 is inverted as compared with the aliasing shown in FIG. 3A because the CCD is pixel-shifted.

The signals G, R and B having the above-mentioned spectrum are A / D converted into digital signals G _e , R ₀ and B ₀ , respectively, which are input to the preprocessor 2. The preprocessor 2 corrects black and white due to the above-mentioned sewing distortion, adjusts R, G and B gains, and corrects defects of CCD.

The signals G _e and R ₀ which have been white and black corrected by the preprocessor 2 are supplied to the image enhancing circuit 3. The image enhancing circuit 3 is a circuit that produces a detail signal as described above. In this case, G _e and R ₀ are converted into the detail signal for VTR and the detail signal for camera output after the respective delay components are rearranged so that the frequency of 18 MHz is 36 MHz. That is, the above two detail signals have a spectrum as shown in (c) obtained by adding the signal G _e having the spectrum as shown in (a) of FIG. 3 and the signal R ₀ having the spectrum as shown in (b) of FIG. Is made based on the signal with.

Here, since the aliasing (broken line) existing in (a) and (b) has opposite polarities, they are canceled by being added, and a clean signal without aliasing is used as the detail source signal. Remain.

On the other hand, the signals G _e and R ₀ which have been white and black corrected by the preprocessor 2 are also supplied to the LPF 4 and the interpolation filter 5, respectively. The LPF 4, the interpolation filter 5, and the interpolation filter 6 to which B ₀ is supplied corrects the phase shift and the like due to the pixel shift of the CCD as described above. Therefore, when G _e and R ₀ , B ₀ enter the color correction circuit 7, their phases are aligned.

Here, the LPF 4 has a spectral characteristic as shown in FIG. Further, the interpolation filters 5 and 6 have spectral characteristics as shown in (e). Therefore, when the signal G _e having the spectral characteristic shown in (a) above is passed through the LPF 4, the spectral characteristic shown in (f) is obtained, and R ₀ and B ₀ having the spectral characteristic shown in (b) above are interpolated by an interpolation filter. When it is passed through 5 and 6, the spectrum characteristics as shown in (g) are obtained.

When the G _e passed through the LPF 4 shown in (f) and (g) above and the signal R _e passed through the interpolation filter 5 are added, a luminance signal Y as shown in (h) is produced. You can In this (h), the aliasing which existed with the opposite polarities is canceled, and the sampling frequency f _s
Only the nearby alias remains. Finally, the spectral characteristics shown in (h) are converted to LP after D / A conversion.
After passing through the F filter, it has a spectral characteristic as shown in (i).

Returning to FIG. 1, the color correction circuit 7 is a circuit for correcting the color of the signal output from the CCD as described above, and from the signals G _e and R _e , B _e , for example, GR,
In order to generate a signal such as G-B and correct the color, it is added to the above G _e and R _e , B _e . The VTR detail signal from the image enhancing circuit 3 is added to the signal output from the color correction circuit 7 by the adders 8, 9 and 10.

The VTR detail signal has, for example, a spectrum characteristic as shown in (j) of FIG.
In Figure 1, G _e, R _e, but the detail signal for VTR for each B _e are added, here, for convenience shown above 3 description
The case of addition to the luminance signal Y shown in (i) will be described.

That is, when the detail signal for VTR having the spectrum characteristic of (j) is added to Y of the spectrum characteristic of (i), an addition signal having the spectrum characteristic as shown in (k) is obtained. Actually, as shown in FIG. 1, G _e , R _e ,
Adding the detail signal of a VTR for each B _e, subjected to gamma correction and knee processing on the addition output, further, again V
The detail signal for TR is added. Then, after the second addition of the VTR detail signal, the matrix circuit 17 causes the luminance signal Y and the color difference signals R-Y and B-Y.
Has been created.

The matrix circuit 17 supplies the produced luminance signal Y and color difference signals RY and BY to the rate converter 21. This rate converter 21 has a clock rate from 18 MHz to 13.5M used in VTR.
Convert to Hz. The rate converter 21 is a kind of filter and has a spectrum characteristic as shown in (l) of FIG. Then, by passing the detailed VTR signal having the spectral characteristic of (k), a signal for VTR having the characteristic shown in (m) is obtained.

On the other hand, in order to generate a signal for camera output, the up-converter 18 doubles the clock rate 18 MHz of the luminance signal Y produced by the matrix circuit 17 to 36 MHz, and the image enhance circuit 3 produces it. The produced detail signals for camera output are added, and then the added output and the matrix circuit 1 are added.
The color difference signals R-Y and B-Y from 7 are encoded by the encoder 20 and finally converted into analog signals by the D / A converters 22 and 23. Then, the output terminals 24 and 25
The camera output signal is being output from.

Here, the signal to which the detail signal for camera output is added is a signal to which the detail signal for VTR is added once (strictly, twice), and the spectrum shown in (k) of FIG. It has characteristics. This (k) is 18
Rewrite as (n) with MHz as the sampling frequency f _s . Further, the up-converter 18 is a kind of filter and has a spectrum characteristic as shown in (o).

Therefore, when the signal after the VTR detail signal having the spectral characteristic of (n) is added is passed through the up-converter 18 having the spectral characteristic of (o), the signal having the characteristic shown in (p) is obtained. Remains. And
When the detail signal for camera output having the characteristic shown in (q) is added to the signal having the characteristic of (p), (r)
A signal having a level change up to a high frequency of 18 MHz as shown in is output for a camera.

As described above, in the present embodiment, the processing is performed with the phase shifted until the preprocessor 2, and then R ₀ and B ₀ are processed.
Are fitted with interpolation filters 5 and 6 to match the phase of G _e . Further, the G _e multiplied by LPF 4, G _e and R ₀ and B
_Make the frequency characteristics of ₀ the same. In this way, 18M
Since G _e , R _e , and B _e having the same phase of Hz are obtained,
The signal recorded on the VTR can be processed at a clock rate of 18 MHz. Generally, the VTR has only to have a band of about 5 to 6 MHz, and a clock band of 18 MHz can sufficiently secure the required band. Also, the detail signal for correcting the frequency characteristic of the band of 5 to 6 MHz is 18M.
It is possible to create a detail signal that can be generated in Hz and that is optimum for a VTR. Further, in this way, most of the signal processing can be performed at a low clock rate of 18 MHz, so that the circuit scale can be reduced and power consumption can be reduced.

On the other hand, a camera output signal which requires a horizontal resolution of 800 TVL or more cannot be realized at a clock rate of 18 MHz, but in this embodiment, the up converter 18 doubles the clock rate of the luminance signal Y to 36 MH.
It is set to z. However, since the original signal does not have much signal components at 6 to 9 MHz and only aliasing occurs at frequencies above 9 MHz, the characteristics of the interpolation filter of the up converter 18 are 9 MHz as shown in (o) of FIG.
The above should be attenuated. Then, the camera output detail signal to be added to the camera output video signal may be formed so as to supplement the portion above 6 MHz as shown in (q) of FIG.

By separately producing the VTR detail signal and the camera output detail signal in this way, the detail signal most suitable for reproduction can be added to the VTR output signal and the camera output signal can be added. The optimum camera output detail signal can be added in consideration of the frequency characteristics, resolution, S / N, etc. when the chart is displayed.

Further, since the VTR detail signal and the camera output detail signal have different occupied bands, the adjustment of one does not affect the other.
Furthermore, the part that operates at the clock rate of 36 MHz is the part of the image enhancement circuit 3 and the encoder circuit 20.
The circuit scale can be reduced because it only handles the Y signal of
Most of them operate at a clock rate of 18 MHz, so power consumption does not increase so much.

Here, in this embodiment, the encoder circuit 20 for generating the digital video signal conforming to NTSC has a relatively large circuit scale, and moreover, it operates at a high clock rate of 36 MHz. Although it must be operable, an analog encoder 40 can be used instead of the digital encoder as in the second embodiment shown in FIG.

In the second embodiment shown in FIG. 4, the addition output of the adder 19 for adding the camera output detail signal generated by the image enhance circuit 3 is converted into an analog signal by the D / A converter 41. Analog encoder 4
0, and the color difference signals RY and BY obtained by the matrix circuit 17 are supplied to the D / A converters 42 and 4.
The analog encoder 40 is converted into an analog signal by the signal 3
Is supplied to.

The analog encoder 40 is an NTSC.
Generate an analog video signal compliant with. The analog video signal generated by the analog encoder 40 is
It is supplied to the viewfinder etc. from the output terminal 44,
It is output from the output terminal 45 as a composite video signal or a test video signal.

As described above, by using the analog encoder 40 instead of the digital encoder, it is possible to reduce the power consumption while maintaining the image quality almost equal to that of the digital encoder.

Since the structure of the other parts in the second embodiment is the same as that of the above-mentioned first embodiment, common numbers are given to corresponding components in FIG. Description is omitted.

The digital signal processing camera according to the present invention is not limited to the above embodiments,
For example, when the image enhancing circuit produces a detail source signal, if it is within the range considering S / N, G
And B, or all of G, B and R may be used.

[0070]

According to the digital signal processing camera of the present invention, a contour correction signal of a low clock rate is added to an input signal to correct the frequency characteristic of a video signal recorded on a video tape recorder, and a contour correction signal of a high clock rate is obtained. Is added to the signal obtained by adding the contour correction signal of the above low clock rate to the input signal and converted into the signal of the high clock rate to correct the frequency characteristics of the video signal of the camera output, and the band of these two types of contour correction signals Since they do not interfere with each other, contour correction can be performed that is optimal when the video tape recorder is played back, and the video signal output from the camera can be contoured without affecting the contour correction of this video tape recorder. Can be corrected. Moreover, since only a part of the digital signal processing needs to be operated with a double clock, the circuit scale can be reduced and power consumption can be reduced. Further, since it is sufficient to operate the double clock circuit system only when necessary, it is possible to save power especially when operating with a battery.

Further, in the digital signal processing camera according to the present invention, the analog encoder is used in place of the digital encoder, so that the power consumption can be reduced while maintaining the image quality almost equal to that of the digital encoder.

[Brief description of drawings]

FIG. 1 is a first digital signal processing camera according to the present invention.
3 is a block circuit diagram of the embodiment of FIG.

FIG. 2 is a block circuit diagram of a main part of the digital signal processing camera.

FIG. 3 is a spectrum characteristic diagram of each component used for explaining the operation of the digital signal processing camera.

FIG. 4 is a first digital signal processing camera according to the present invention.
3 is a block circuit diagram of the embodiment of FIG.

[Explanation of symbols]

1. Image processing circuit 2 ... Preprocessor 3 ... ..Image enhancement circuit 4 ... Low pass filter 5, 6 ... Interpolation filter 7 ... ..... color correction circuit 11, 12, 13, ..... gamma / knee correction circuit 17 ..... matrix circuit 18・ ・ ・ ・ ・ ・ ・ ・ Up-converter 20, 40 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Encoder 21 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Rate converter 22 , 23, 41, 42, 43 ... D / A converter

Claims (4)

[Claims] 1. A digital signal processing camera for correcting an image using a contour correction signal, wherein the contour correction signal is formed into two systems according to the lock rate, and a low clock rate contour correction signal is added to an input signal. The frequency characteristics of the video signal recorded on the video tape recorder are corrected, and the high clock rate contour correction signal is converted to a signal obtained by adding the above low clock rate contour correction signal to the high clock rate signal. In addition, a digital signal processing camera characterized by correcting the frequency characteristic of the video signal output from the camera. 2. The digital signal processing camera according to claim 1, wherein the bands of the contour correction signal of the low clock rate and the contour correction signal of the high clock rate do not interfere with each other. 3. The digital signal processing camera according to claim 1, wherein the video signal output from the camera is obtained by performing an encoding process by a digital encoder. 4. The digital signal processing camera according to claim 1, wherein the video signal output from the camera is obtained by performing an encoding process by an analog encoder.