JP3153941B2 - Digital signal processing camera - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing camera for performing image contour correction by digital signal processing.

[0002]

2. Description of the Related Art Conventionally, a video camera is equipped with a contour correction circuit. This contour correction circuit is composed of a delay circuit and an addition / subtraction circuit, and is used for compensating for response deterioration of an imaging device in a video camera and for enhancing sharpness.

On the other hand, the video signal of this video camera is used as a camera output as a view finder (VF).
r) and is visually recognized from a monitor or the like, and on the other hand, recorded on a video tape recorder (hereinafter referred to as VTR). this house,
The video signal recorded on the VTR has a frequency band of 5-6M.
However, since the video signal output from the camera must have a high resolution as a criterion of the quality of the camera, a frequency band of 10 MHz or more (a horizontal resolution of 800 TVL) is required.

[0004]

The above-mentioned VTR
Clock rate of the video signal in use (frequency band 5～6MHz) is, 13.5 MHz and 4f _sc (f _sc is the subcarrier frequency) is. On the other hand, the clock rate of the video signal for camera output (the frequency band is 10 MHz or more) is required to be a high-resolution video signal for camera output. 27 MHz and 8 _fsc are required.

However, conventionally, there is only one outline correction signal (hereinafter referred to as "detail signal") for performing the above-described outline correction, and a 27-MHz or higher frequency signal is used to process both the VTR video signal and the camera output video signal. 8f _sc . Therefore, if the gain of the contour correction is changed, the video signal for VTR output and the video signal for camera output also change at the same time. For example, there is a demand for changing only the contour correction amount of the video signal for VTR. I can't respond.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and it is possible to separately prepare a contour correction signal for a video signal for VTR output and a video signal for camera output. It is an object of the present invention to provide a digital signal processing camera capable of performing contour correction of a video signal output from a camera without affecting contour correction of the video signal.

[0007]

SUMMARY OF THE INVENTION The present invention relates to a digital signal processing camera for correcting an image using a contour correction signal, wherein a low clock rate contour correction signal and a high clock rate contour correction signal are obtained from an input video signal. Means for forming a contour correction signal to be formed, first adding means for adding the contour correction signal at a low clock rate to an input video signal, and the contour correction signal at a low clock rate added by the first adding means. Clock rate conversion means for converting an input video signal into a high clock rate video signal, and second adding means for adding the high clock rate contour correction signal to the high clock rate video signal obtained by the clock rate conversion means A low clock rate video signal to which the low clock rate contour correction signal is added, and the high clock rate video signal. Wherein the contour correction signal rate to output a video signal of a high clock rate of the addition.

Here, the bands of the low-clock-rate contour correction signal and the high-clock-rate contour correction signal formed by the contour correction signal forming means do not interfere with each other.

Further, the digital signal processing camera according to the present invention includes a digital encoder for performing an encoding process on a high clock rate video signal to which the high clock rate contour correction signal is added.

Further, the digital signal processing camera according to the present invention comprises a D / A converter for converting a high clock rate video signal to which the high clock rate contour correction signal is added, into an analog video signal, and the D / A converter. An analog encoder for encoding an analog video signal obtained by the A converter is provided.

[0011]

In the digital signal processing camera according to the present invention,
The contour correction signal forming means forms a low clock rate contour correction signal and a high clock rate contour correction signal from the input video signal, and the first adding means adds the low clock rate contour correction signal to the input video signal. . Thereby, the frequency characteristics of the video signal of the low clock rate are corrected. The low-clock-rate video signal whose frequency characteristic has been corrected is converted into a high-clock-rate video signal by clock-rate conversion means, and the high-clock-rate video signal is converted into the high-clock-rate video signal by second addition means. Add the correction signal. Thereby, the frequency characteristics of the video signal of the high clock rate are corrected. By ensuring that the bands of the low-clock-rate contour correction signal and the high-clock-rate contour correction signal do not interfere with each other, it is possible to perform contour correction that is optimal when reproducing a video tape recorder at a low clock rate. It can be applied to the video signal, and furthermore, the contour correction can be applied to the high clock rate video signal without affecting the contour correction to the low clock rate video signal.

Also, in the digital signal processing camera according to the present invention, the digital encoder encodes and outputs the high clock rate video signal to which the high clock rate contour correction signal is added.

Further, in the digital signal processing camera according to the present invention, the high clock rate video signal to which the high clock rate contour correction signal is added is converted into an analog video signal by a D / A converter, and the analog video signal is converted by an analog encoder. The analog video signal is encoded and output.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a digital signal processing camera according to the present invention will be described below with reference to the drawings.

FIG. 1 is a block circuit diagram showing an embodiment of a digital signal processing camera according to the present invention.

In FIG. 1, an image pickup processing circuit 1 includes an image pickup device such as a CCD, an amplifier, an A / D converter, and the like. Signal G _e the three primary colors digital signal obtained by the imaging processing circuit 1, the signal R _0, signal B ₀ is supplied to the preprocessor 2.

[0017] The preprocessor 2 signal is corrected shading etc. in G _e, the signal R _0, the low-pass filter with the signal G _e of the signal B ₀ is supplied to the image enhancement circuit 3 (hereinafter, referred to as LPF) 4 Supplied to The signal R ₀ is supplied to the image enhancement circuit 3 and to the interpolation filter 5. Further, the signal B ₀ is supplied to the interpolation filter 6.

The signal G _e having the same frequency characteristics as the signal R ₀ and the signal B _{0 by} the low-pass filter 4 and the signal R _e adjusted to the phase of the signal Ge by the interpolation filter 5.
_0, the signal B ₀ which is matched to the phase of the signal G _e above interpolation filter 6 is supplied to the color correction circuit 7.

[0019] The color corrected signals G _e in the color correction circuit 7, R _e, B _e is supplied to the adder 8, 9 and 10.
The adders 8, 9, and 10 have a low clock rate (18 in this case) output from the image enhancer circuit 3.
MHz). And
The color corrected signals G _e, R _e, B _e, in the adder 8, 9, 10, so that the detail signal of the low clock rate is added to each.

The added output signal from the adder 8 is supplied to a gamma / knee correction circuit 11 for performing gamma correction and knee processing. Similarly, the addition output signal from the adder 9 and the addition output signal from the adder 10 are supplied to gamma / knee correction circuits 12 and 13.

The gamma / knee correction circuits 11, 12,
13 The signal subjected to the data signal processing is added to adders 14, 15, 1
6. The detail signals of the low clock rate output from the image enhancement circuit 3 are again supplied to the adders 14, 15, and 6. The low clock rate detail signal is added to the output signals from the gamma / knee correction circuits 11, 12, and 13 by the adders 14, 15, and 16, respectively.

The added outputs from the adders 14, 15, 16 are supplied to a matrix circuit 17. The luminance signal Y of the luminance signal Y and the chrominance signals RY and BY generated by the matrix circuit 17 is supplied to an up-converter circuit 18 which converts the input signal into a high clock rate signal. Both are also supplied to a rate converter 21 that converts the rate of an input signal to a predetermined frequency.

The up-converter circuit 18 converts the clock rate of the luminance signal Y from 18 MHz to 36 MHz. The luminance signal Y converted to a high clock rate by the up-converter circuit 18 is supplied to an adder 19. The adder 19 has a high clock rate (36 MHz in this case) output from the image enhancement circuit 3.
The detail signal of z) is also supplied. The high clock rate detail signal is added by the adder 19 to the 36 MHz luminance signal Y.
The addition output from the adder 19 is supplied to the encoder 20.

Further, the color difference signals RY and BY generated by the matrix circuit 17 are
0 and is also supplied to the rate converter 21. The encoder 20 generates a 36 MHz high clock rate luminance signal Y and a low clock rate 18 MHz color difference signals RY and BY to generate a D / A converter 22.
And 23.

The D / A converters 22 and 23 are connected to output terminals 24 and 25 for camera output.

The rate converter 21 has an 18M
Hz is converted to _13. 5 MHz used in the VTR system. The rate converter 21 is connected to a Y terminal 26, a RY terminal 27, and a BY terminal 28 for recording / reproduction of the VTR. The rate converter 21 is supplied with, for example, a 13.5 MHz clock and a reproduction ON / OFF signal from the VTR via the input terminals 29 and 30. The matrix circuit 17 includes:
A reproduction ON / OFF signal from the VTR is supplied via the input terminal 30.

The operation of each section of the embodiment having the above-described configuration will be described below.

First, the imaging processing circuit 1 converts light incident through a lens (not shown) into video signals R, G, and B,
They are A / D converted and the three primary color digital signals _Ge , R
₀ and B ₀ are output. Here, this imaging processing circuit 1
Is shifted, the phases of the green digital signal _Ge , the red digital signal R ₀ and the blue digital signal B ₀ are shifted by ピ ッ チ pitch. Then, A / D conversion is performed while the phase is shifted, and signals _Ge , R ₀ , and B ₀ are supplied from the imaging processing circuit 1 to the preprocessor 2.

The preprocessor 2 corrects a defect in the CCD constituting the image pickup processing circuit 1 and corrects a shading distortion which affects white and black due to variations in the sensitivity of the CCD. The digital data _Ge and R ₀ that have been subjected to so-called pseudo-correction and the like by the preprocessor 2.
And B ₀ remain out of phase by １ ／. G
_e is supplied to the image enhancement circuit 3 and LP
It is also supplied to F4. R _{0 is} also supplied to the image enhancement circuit 3 and to the interpolation filter 5. B ₀ is supplied to the interpolation filter 6.

The image enhancement circuit 3 corrects the contour of the image on the video signal to improve the apparent resolution. In the present embodiment, the _Ge and R are shifted in phase by 1/2. _{With 0} as an input, a detail signal for camera output and a detail signal for VTR are distinguished and output by a delay element, a comb filter, a high-pass filter, a multiplier and the like.

FIG. 2 is a block circuit diagram of the image enhancement circuit 3.

In FIG. 2, the input terminal 51 has a read clock rate of 18 MH output from the imaging processing circuit 1.
z signal G _e is inputted. The input terminal 52 has a read clock rate 1 output from the imaging processing circuit 1.
An 8 MHz signal R ₀ is input.

The signal G _e via the input terminal 51, 1
2H delayed signal G _2H through H delay circuit 53 and the 1H delay circuit 54, is supplied to the 1H is divided into delayed signal G _1H and undelayed signal G _0H comb filter 57 through the 1H delay circuit 53. Also, the signal R _e via the input terminal 52, 1H delay circuit 55 and the 1H delay circuit 5
6, 2H delayed signal R _2H , 1H delay circuit 55
The signal R _1H delayed by _1H and the signal R _0H not delayed are supplied to the comb filter 57.

The comb-shaped filter 57 outputs the delayed signals G _2H , G _1H , R having a read clock rate of 18 MHz.
_2H , R _1H and the _undelayed signals G _0H , R _0H ,
A signal having a frequency of 36 MHz is obtained. The 36 MHz signal from the comb filter 57 is supplied to a high-pass filter (hereinafter referred to as HPF) 58 and a rate converter 5.
9.

The 36 MHz signal passed through the HPF 58 is supplied to a multiplier 61 which operates as a gain adjuster, and is multiplied by a control signal via an input terminal 63. The output of the multiplier 61 is a horizontal detail signal, which is added to the vertical detail signal supplied from the input terminal 67 by the adder 65 and output from the output terminal 69 as a high clock rate (36 MHz) detail signal for camera output. You.

The rate converter 59 has a capacity of 36M.
Hz signal is converted to 18 MHz. The output signal from the rate converter 59 is supplied to the HPF 60. The 18 MHz signal passed through the high-pass filter 60 is
The signal is supplied to a multiplier 62 which operates as a gain adjuster, and is multiplied by a control signal via an input terminal 64. This multiplier 62
Is a horizontal detail signal, which is added to the vertical detail signal supplied from the input terminal 68 by the adder 66 and output from the output terminal 70 as a low clock rate (18 MHz) detail signal for VTR output.

In FIG. 1, the signals G _e , R ₀ ,
B ₀ is supplied to the LPF 4, the interpolation filter 5, and the interpolation filter 6. Interpolation filters 5 and 6 provide signal R ₀ and signal B ₀
Adjust the phase to the phase of G _e. Further, LPF 4 is the same frequency characteristic of the signal G _e and the signal R _0, B _o. Therefore, the signals G _e and R ₀ and B ₀ having different phases before being supplied to the LPF 4 and the interpolation filters 5 and 6 are
Phases uniform signal R _e by passing the LPF4 and interpolation filters 5 and 6, the G _e, B _e.

The color correction circuit 7 is a circuit for correcting the color of the video signal output from the CCD constituting the imaging signal processing circuit 1. Specifically, the signal R having the same phase
_{e, G e, G e -B} e with B _e, seeking signals such as G _e -R _e are summed for color correction.

[0039] G _e, R _e, the image enhancement circuit 3 to B _e from the adder 8, 9 and 10 the color correction circuit 7
The VTR detail signal supplied from is added.
Gamma / knee correction circuits 11, 12, 13 apply gamma correction and knee correction to the signal to which the VTR detail signal has been added.

The gamma / knee correction circuits 11, 12, 1
The gamma correction performed by 3 is for correcting, on the camera side, the non-linear relationship between the grid signal voltage of the color picture tube and the light emission output, and the knee processing is white compression processing. The signals subjected to gamma correction and knee processing in the gamma / knee correction circuits 11, 12, and 13 are added again to adders 14, 1
VTR from the image enhancement circuit 3 at 5 and 16
Detail signal is added. And adder 1
Output signals from 4, 15, and 16 are supplied to a matrix circuit 17.

[0041] The matrix circuit 17 produces a digital video signal G _e supplied, R _e, the luminance signal from the B _e Y and color difference signals R-Y, the B-Y. Then, the luminance signal Y is supplied to the up-converter circuit 18. The color difference signals RY and BY are supplied to the encoder circuit 20 and the rate converter circuit 21, respectively.

The up-converter circuit 18 converts the clock rate 18 MHz of the luminance signal Y to 36 MHz. The detail signal for camera output from the image enhancement circuit 3 is added to the luminance signal Y having the clock rate of 36 MHz by the adder 19.

The encoder circuit 20 includes a 36 MHz luminance signal Y to which a camera output detail signal is added, and color difference signals RY and BY from the matrix circuit 17.
The signal is encoded into a video signal conforming to, for example, NTSC. Then, the signal is returned to the analog signal by the D / A converter 22 and supplied to the viewfinder or the like from the output terminal 24, or is returned to the analog signal by the D / A converter 23, and the composite image signal or the test image Output as a signal.

The rate converter circuit 21 has a clock rate of 18 MH supplied from the matrix circuit 17.
The luminance signal Y and the color difference signals RY and BY of z are converted into signals having a clock rate of 13.5 MHz suitable for the VTR, and are output to the head of the VTR via output terminals 26, 27 and 28.

Next, the overall operation of this embodiment will be described with reference to FIG. FIG. 3 is a diagram showing how the spectrum characteristics of each unit used in the present embodiment change.

First, C in the imaging processing circuit 1 of this embodiment is
Since the read clock of the CD is 18 MHz, the baseband signal of the signal G is as shown by the solid line in FIG. Similarly, the baseband signals of the signals R and B are as shown by the solid lines in FIG. Where 1
Since sampling is performed on an 8 MHz signal at 18 MHz, aliasing (aliasing noise) occurs as shown by a broken line in FIGS. 3 (a) and 3 (b). FIG. 3 (b)
The reason why the aliasing shown in FIG. 3 is inverted compared to the aliasing shown in FIG. 3A is that the CCD is shifted in pixel.

The signals G, R and B having the above-mentioned spectrum are A / D converted and become digital signals G _e , R ₀ and B ₀ , respectively, and input to the preprocessor 2. The preprocessor 2 performs black and white corrections due to the above-described pseudo-distortion, adjusts R, G, and B gains, and corrects CCD defects.

The signals G _e and R ₀ that have been subjected to white and black corrections and the like by the preprocessor 2 are supplied to an image enhancement circuit 3. The image enhancement circuit 3 is a circuit for generating a detail signal as described above. In this case, G _e, R ₀ is converted from the frequency were both 18MHz reordered each delay component such as is the 36 MHz, the detail signal and the detail signal of the camera output for VTR. That is, the two detail signals, spectrum as shown in the sum of the signals R ₀ having a spectrum as shown in the signal G _e (b) having a spectrum as shown in (a) shown in FIG. 3 (c) Is made based on the signal with.

Here, the aliasing (broken line) existing in (a) and (b) has opposite polarities, and therefore is canceled by being added, and a clean signal without aliasing is used as a detail source signal. Remains.

On the other hand, the signals G _e and R ₀ subjected to white and black corrections and the like by the preprocessor 2 are also supplied to the LPF 4 and the interpolation filter 5, respectively. The LPF 4, the interpolation filter 5, and the interpolation filter 6 to which B ₀ is supplied correct a phase shift or the like due to the pixel shift of the CCD as described above. For this reason, when _Ge and R ₀ and B ₀ enter the color correction circuit 7, their phases are aligned.

Here, the LPF 4 has a spectrum characteristic as shown in FIG. The interpolation filters 5 and 6 have spectral characteristics as shown in FIG. Therefore, when passing the signal through G _e spectral characteristics shown in (a) above to the LPF4 become spectral characteristics (f), the interpolating R _0, B ₀ of the spectral characteristics shown in (b) above filter When the light passes through Nos. 5 and 6, a spectrum characteristic as shown in FIG.

[0052] The above (f), to make the luminance signal Y as shown in G _e having passed through a LPF4 shown in (g), when adding the signals R _e was passed through an interpolation filter 5 (h) Can be. In (h), the aliasing in which the polarities are opposite to each other is canceled, and the sampling frequency f _s
Only the surrounding aliasing remains. Finally, the spectral characteristics shown in (h) are converted to D / A,
After passing through the F filter, it has a spectral characteristic as shown in (i).

[0053] Returning to Figure 1, the color correction circuit 7 is a circuit for correcting the color of the signal output from the CCD as described above, the signal G _e and R _e, from B _e example G-R,
The G _e and R _e in order to correct the color to make a signal such as that G-B, are added to B _e. The VTR detail signal from the image enhancement circuit 3 is added to the signal output from the color correction circuit 7 by the adders 8, 9, and 10.

The VTR detail signal has, for example, a spectral characteristic as shown in FIG.
In Figure 1, G _e, R _e, but the detail signal for VTR for each B _e are added, here, for convenience shown above 3 description
(I) will be described below.

That is, when the VTR detail signal having the spectral characteristic (j) is added to the Y having the spectral characteristic (i), an added signal having the spectral characteristic shown in (k) is obtained. In practice, as shown in FIG. 1, _Ge , _Re ,
Adding the detail signal of a VTR for each B _e, subjected to gamma correction and knee processing on the addition output, further, again V
The detail signal for TR is added. After the addition of the second VTR detail signal, the matrix circuit 17 outputs the luminance signal Y and the color difference signals RY and BY.
Has been produced.

The matrix circuit 17 supplies the produced luminance signal Y and color difference signals RY and BY to the rate converter 21. This rate converter 21 has a clock rate of 18 MHz to 13.5M used in VTR.
Convert to Hz. The rate converter 21 is a kind of filter and has a spectrum characteristic as shown in FIG. Then, by passing a detailed VTR signal having the spectrum characteristic (k), a signal for a VTR having the characteristic shown in (m) is obtained.

On the other hand, in order to generate a signal for camera output, the clock rate 18 MHz of the luminance signal Y generated by the matrix circuit 17 is doubled by the up-converter 18 into 36 MHz, and the image enhancement circuit 3 converts the clock rate into 36 MHz. The generated camera output detail signal is added, and then the added output is added to the matrix circuit 1
The color difference signals RY and BY from the encoder 7 are encoded by an encoder 20 and finally converted into analog signals by D / A converters 22 and 23. And output terminals 24 and 25
Outputs the camera output signal.

Here, the signal to which the detail signal for camera output is added is a signal to which the detail signal for VTR is added once (strictly twice), and the spectrum shown in FIG. Has characteristics. This (k) is 18
Rewrite MHz so as the sampling frequency f _s of the (n). The up-converter 18 is a kind of filter and has a spectral characteristic as shown in FIG.

Therefore, when the signal after the addition of the VTR detail signal having the spectral characteristic (n) is passed through the up-converter 18 having the spectral characteristic (o), the signal having the characteristic (p) is obtained. Remains. And
When the camera output detail signal having the characteristic shown in (q) is added to the signal having the characteristic (p), (r)
A signal having a level change up to a high frequency of 18 MHz as shown in FIG.

As described above, in the present embodiment, processing is performed with the phase shifted up to the preprocessor 2, and then R ₀ and B ₀
It is matched to the phase of the G _e over interpolating filters 5 and 6 in. Further, the G _e multiplied by LPF 4, G _e and R ₀ and B
_Make the frequency characteristics of ₀ the same. In this way, 18M
Hz phase of uniform G _e, R _e, since B _e is obtained,
Signals recorded on the VTR can be processed at a clock rate of 18 MHz. Usually, the VTR only needs to have a band of about 5 to 6 MHz, and a sufficient band can be secured at a clock rate of 18 MHz. The detail signal for correcting the frequency characteristic of the band from 5 to 6 MHz is also 18M.
Hz, and a detail signal that is optimal for a VTR can be generated. Further, since most of the signal processing can be performed at a low clock rate of 18 MHz, the circuit scale can be reduced and the power consumption can be reduced.

On the other hand, a camera output signal requiring a horizontal resolution of 800 TVL or more cannot be realized at a clock rate of 18 MHz. In this embodiment, however, the upconverter 18 doubles the clock rate of the luminance signal Y to 36 MHz.
z. However, the original signal has little signal component at 6 to 9 MHz and has only aliasing up to 9 MHz or more. Therefore, the characteristic of the interpolation filter of the up-converter 18 is 9 MHz as shown in FIG.
The above is attenuated. Then, the camera output detail signal to be added to the camera output video signal may be formed so as to supplement the portion above 6 MHz as shown in FIG. 3 (q).

If the detail signal for the VTR and the detail signal for the camera output are separately generated as described above, the detail signal most suitable for reproduction can be added to the VTR output signal, and the camera output signal can be added to the VTR output signal. An optimal camera output detail signal can be added in consideration of frequency characteristics, resolution, S / N, and the like when the chart is projected.

Since the VTR detail signal and the camera output detail signal occupy different bands, adjustment of one does not affect the other.
Further, a part that operates at a clock rate of 36 MHz includes a part of the image enhancement circuit 3 and the encoder circuit 20.
The circuit scale can be reduced because only the part that handles the Y signal
Most of the devices operate at a clock rate of 18 MHz, so that power consumption is not so large.

Here, in this embodiment, the encoder circuit 20 for generating a digital video signal conforming to NTSC has a relatively large circuit size, and operates at a clock rate of 36 MHz. The operation must be possible, but an analog encoder 40 may be used instead of the digital encoder as in the second embodiment shown in FIG.

In the second embodiment shown in FIG. 4, the addition output of the adder 19 for adding the camera output detail signal generated by the image enhancement circuit 3 is converted into an analog signal by the D / A converter 41. Analog encoder 4
0, and the color difference signals RY and BY obtained by the matrix circuit 17 are converted into D / A converters 42 and 4.
And the analog encoder 40
Supplied to

The analog encoder 40 is an NTSC
Generate an analog video signal conforming to. The analog video signal generated by the analog encoder 40 is
It is supplied from the output terminal 44 to a viewfinder or the like,
It is output from the output terminal 45 as a composite video signal or a test video signal.

As described above, by using the analog encoder 40 instead of the digital encoder, it is possible to reduce the power consumption while maintaining almost the same image quality as that obtained by the digital encoder.

Since the configuration of the other parts in the second embodiment is the same as that of the first embodiment, corresponding components are denoted by common reference numerals in FIG. Detailed description is omitted.

The digital signal processing camera according to the present invention is not limited to the above embodiments, but
For example, when the image enhancement circuit creates a detail source signal, if the S / N is within the range, G
And B, or all of G, B and R may be used.

[0070]

In the digital signal processing camera according to the present invention, the contour correction signal forming means forms the low clock rate contour correction signal and the high clock rate contour correction signal from the input video signal, and the first addition means. By adding the low-clock-rate contour correction signal to the input video signal, the frequency characteristics of the low-clock-rate video signal can be corrected, and the low-clock-rate video signal whose frequency characteristics have been corrected is clocked. By converting the video signal of the high clock rate into the video signal of the high clock rate by the rate converting means and adding the contour correction signal of the high clock rate to the video signal of the high clock rate by the second adding means, Characteristics can be corrected. In this digital signal processing camera, the band of the low-clock-rate contour correction signal and the band of the high-clock-rate contour correction signal are prevented from interfering with each other, so that the video tape recorder becomes optimal when reproduced. Such contour correction can be applied to the low clock rate video signal, and further, the contour correction can be applied to the high clock rate video signal without affecting the low clock rate video signal.
Further, in this digital signal processing camera, only a part of the digital signal processing needs to be operated with a double clock, so that the circuit scale can be reduced and the power consumption can be reduced. Further, since the double clock circuit only needs to be operated when necessary, power saving can be achieved, particularly when operated by a battery.

Further, in the digital signal processing camera according to the present invention, by using an analog encoder instead of the digital encoder, it is possible to reduce power consumption while maintaining almost the same image quality as that of the digital encoder.

[Brief description of the drawings]

FIG. 1 shows a first embodiment of a digital signal processing camera according to the present invention.
FIG. 6 is a block circuit diagram of the embodiment.

FIG. 2 is a block circuit diagram of a main part of the digital signal processing camera.

FIG. 3 is a spectrum characteristic diagram of each component used for explaining the operation of the digital signal processing camera.

FIG. 4 is a first view of a digital signal processing camera according to the present invention.
FIG. 6 is a block circuit diagram of the embodiment.

[Explanation of symbols]

1 ... Imaging processing circuit 2 ... Preprocessor 3 ... ··· Image enhancement circuit 4 ······ Low-pass filters 5 and 6 ····· Interpolation filter 7 ······· ········ Color correction circuit 11, 12, 13 ································· Matrix circuit · · · · · Upconverters 20 and 40 · · · Encoder 21 · · · Rate converter 22 , 23,41,42,43 ... D / A converter

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/14-5/217 H04N 9/68 103

Claims (4)

(57) [Claims] 1. A digital signal processing camera for correcting an image using a contour correction signal, comprising: a contour correction signal forming means for forming a low clock rate contour correction signal and a high clock rate contour correction signal from an input video signal; First adding means for adding the low-clock-rate contour correction signal to an input video signal; and converting the input video signal to which the low-clock-rate contour correction signal has been added by the first adding means into a high-clock-rate. Clock rate conversion means for converting the video signal into a video signal; and second addition means for adding the high clock rate contour correction signal to the high clock rate video signal obtained by the clock rate conversion means; A low clock rate video signal to which the contour correction signal of Digital signal processing camera and outputting a video signal of summed high clock rate. 2. The digital signal according to claim 1, wherein the low-clock-rate contour correction signal and the high-clock-rate contour correction signal formed by the contour correction signal forming means are in a band that does not interfere with each other. Processing camera. 3. The digital signal processing according to claim 1, further comprising a digital encoder for performing an encoding process on the high clock rate video signal to which the high clock rate contour correction signal is added. camera. 4. A D / A converter for converting a high clock rate video signal to which the high clock rate contour correction signal has been added into an analog video signal, and an analog video signal obtained by the D / A converter. The digital signal processing camera according to claim 1, further comprising an analog encoder that performs an encoding process.