JP2785214B2 - Signal processing circuit of solid-state imaging device - Google Patents

Description

The present invention digitizes an imaging output signal from a solid-state image sensor for generating a video signal, and forms a detail signal by digital signal processing to perform image enhancement processing. With regard to the signal processing circuit of the solid-state imaging device as described above, the solid-state image sensor for capturing a green image and the solid-state image sensor for capturing a red image and a blue image are spatially separated by a half of the repetition pitch of each pixel. The present invention relates to a signal processing circuit of a solid-state imaging device that employs a so-called spatial picture element shifting method of displacing and arranging in an imaging unit.

B SUMMARY OF THE INVENTION The present invention provides a so-called space in which a solid-state image sensor for capturing a green image and a solid-state image sensor for capturing a red image and a blue image are spatially shifted by 1/2 of the repetition pitch of each pixel. Signal processing of a solid-state imaging device that adopts a picture element shifting method to digitize an imaging output signal from each solid-state image sensor of an imaging unit and form a detail signal for performing image enhancement processing by digital signal processing. In the circuit, a digital output signal obtained by digitizing each imaging output signal read from each of the solid-state image sensors at a sampling rate of fs at a clock rate equal to the sampling rate fs by analog-to-digital conversion means, a green image imaging signal and a red Image pickup signal, blue image pickup signal or combination of both signals A digital filter is used to form a detail signal having a clock rate of 2fs which is twice the sampling rate fs from the signal obtained by adding the signal and the equal amount, and the digital output signal is interpolated to the detail signal by a digital filter to a clock rate of 2fs. The image enhancement processing can be performed at a clock rate of 2 fs by performing addition by the addition means.

Further, the present invention provides a gamma correction unit that operates at a clock rate of 2 fs by performing a Gaman correction process on the output signal of the adding unit, thereby obtaining a digital output signal that is subjected to image enhancement processing at a clock rate of 2 fs. On the other hand, gamma correction processing can be appropriately performed.

Further, the present invention provides a first clock rate operation of fs.
The gamma correction means performs gamma correction processing on the output signal of the analog-to-digital conversion means.
The gamma correction process is performed on the detail signal by the second gamma correction means operating at the clock rate of 2. The gamma correction process is appropriately performed on the digital output signal subjected to the image enhancement process at the clock rate of 2 fs. It can be applied to.

C. Prior Art In a solid-state imaging device using a solid-state image sensor having a discrete picture element structure formed by a charge coupled device (CCD) or the like as an imaging unit, the solid-state image sensor itself is a sampling system. In addition, as shown by hatching in FIG. 18, an aliasing component from the spatial sampling frequency fs is mixed in the image output signal from the solid-state image sensor.

Conventionally, an imaging optical system is provided with a birefringent optical low-pass filter to suppress the high band side of a baseband component of an imaging signal, thereby satisfying the Nyquist condition of the sampling system using the solid-state image sensor. The generation of the aliasing component of the output signal to the baseband is prevented.

Further, in a color television camera device, a solid-state image sensor for capturing a green image and a solid-state image sensor provided with a color coding filter for red picture elements and blue picture elements, a two-plate solid-state imaging apparatus for taking three primary color images,
2. Description of the Related Art A multi-panel solid-state imaging device such as a three-panel type that captures three primary color images by individual solid-state image sensors has been put to practical use.

Further, as a technique for improving the resolution in the multi-plate type solid-state imaging device, a solid-state image sensor for capturing a green image is 1/1 of a spatial sampling period of a pixel.
There is known a so-called spatial picture element shifting method in which two solid-state image sensors for capturing a red image and a solid-state image sensor for capturing a blue image are shifted from each other. By adopting the spatial picture element shifting method, a high resolution exceeding the limit of the number of images of the solid-state image sensor can be realized in the analog output multi-plate solid-state imaging device.

Also, for digital video tape recorders for business use in broadcasting stations and the like, standardization of so-called D1 / D2 format and the like has been promoted, and digital interfaces for digital video-related equipment conforming to these standards are used in color televisions. There is also a need for camera devices. In the standard of the digital interface for digital video-related equipment, the sampling rate is set to about the sampling rate fs of the current solid-state image sensor.

Further, in general, in a television camera device or the like, in order to improve image quality, a gamma correction process is performed on an imaging output signal obtained by an imaging unit, or a detail signal is formed from the imaging output signal to generate an original signal. An image enhancement process for adding and combining is performed.

D Problems to be Solved by the Invention Meanwhile, as described above, the solid-state image sensor for capturing a green image and the solid-state image sensors for capturing a red image and a blue image are spatially separated by の of the repetition pitch of each pixel. In a solid-state imaging device including an imaging unit that employs a so-called spatial picture element shifting method that is arranged so as to be shifted, when performing gamma correction processing or image enhancement processing by digital signal processing on an imaging output signal, image quality is determined by the aliasing component. There is a problem that deterioration occurs, and there is a problem that when horizontal detail signal components are mixed in the color sub-carrier frequency region, image quality deteriorates due to cross color interference.

Accordingly, the present invention provides a solid-state imaging device including an imaging unit that employs a so-called spatial picture element shifting method, which performs gamma correction processing by digital signal processing on an imaging output signal without image quality deterioration due to aliasing components and cross-color interference. And an image enhancement process.

E. Means for Solving the Problems A signal processing circuit of a solid-state imaging device according to the present invention includes a solid-state image sensor for capturing a green image and a solid-state image sensor for capturing a red image and a blue image. Each of the imaging output signals read out at a sampling rate of fs from each of the solid-state image sensors of the imaging section in which the sensor and the sensor are arranged in a space by 1/2 of the repetition pitch of each pixel are digitally converted at a clock rate equal to the sampling rate fs. Analog-to-digital conversion means,
From the digital output signals of the analog-to-digital conversion means, a signal obtained by adding equal amounts of a green image pickup signal and a red image pickup signal, a blue image pickup signal, or a combined signal of both signals, to a clock twice the sampling rate fs. rate
Detail signal generating means for generating at least a horizontal detail signal of 2 fs, interpolation means for interpolating a digital output signal of the analog / digital conversion means to a clock rate of 2 fs, and an output signal of the detail signal generating means for the interpolation means. And an adding means for adding to the output signal.

Further, the signal processing circuit of the solid-state imaging device according to the present invention,
A gamma correction means for performing a gamma correction process on the output signal of the adding means is provided.

Further, the signal processing circuit of the solid-state imaging device according to the present invention operates at a clock rate of fs to perform a gamma correction process on the output signal of the analog / digital conversion means.
And a second gamma correction means which operates at a clock rate of 2 fs and performs gamma correction processing on the output signal of the detail signal generation means is provided. Things.

F Function In the signal processing circuit of the solid-state imaging device according to the present invention, the analog-to-digital conversion means converts each image output signal read at a sampling rate of fs from each solid-state image sensor of the imaging unit employing the spatial picture element shifting method. For a digital output signal digitized at a clock rate equal to the sampling rate fs, 2 fs
A 2 fs horizontal detail signal is formed by the detail signal generation means, and these signals are added and combined by the addition means to perform image enhancement processing, and a digital output after image enhancement processing is performed. Output signal at 2fs rate.

Further, in the signal processing circuit of the solid-state imaging device according to the present invention, the gamma correction processing is performed on the digital output signal after the image enhancement processing at a rate of 2 fs by the gamma correction means provided on the output side of the addition means.

Further, in the signal processing circuit of the solid-state imaging device according to the present invention, the first gamma correction means operating at the clock rate of fs performs gamma correction processing on the digital output signal of the analog / digital conversion means, and outputs the clock signal of 2 fs. Gamma correction is performed on the horizontal detail signal from the detail signal generation means by the second gamma correction means operating at the rate, and the digital output signal of the gamma correction processing agent by the first gamma correction means is converted into a 2 fs rate signal by the interpolation means. The digital output signal of 2 fs rate is added to the digital output signal of 2 fs rate, and the horizontal detail signal subjected to the gamma correction processing by the second gamma correction means is added by the adding means, whereby the gamma correction processing and the image enhancement processing are performed. To form a digital output signal.

G. Embodiment Hereinafter, an embodiment of the signal processing circuit of the solid-state imaging device according to the present invention will be described in detail with reference to the drawings.

Figure 1 is decomposed into R, G, three primary color light component of B by the color separation prism imaging light L _i is incident through the optical low-pass filter (2) from the image pickup lens (1) (3), The three primary color images of the subject image are converted to three CCD image sensors (4R),
1 shows a color television camera device configured by applying the present invention to a three-plate solid-state imaging device that performs imaging according to (4G) and (4B).

In this embodiment, the three CCD image sensors (4R), (4G), and (4B) constituting the image pickup unit of the color television camera device adopt a spatial picture element shifting method, and As shown in the figure, the CCD image sensor for capturing a red image (4R) and the CCD image sensor for capturing a blue image (4B) are compared with the CCD image sensor for capturing a green image (4G). They are arranged offset by one-half of τ _S. The three CCD image sensors (4R), (4G), and (4B) are driven by a CCD drive circuit (not shown), and the imaging charge of each pixel is four times the color sub-carrier frequency f _SC , that is, 4 f _SC . It is read by the read clock of the sampling frequency fs.

The three CCD image sensors (4R), (4G), and (4B) that adopt the spatial picture element shifting method described above use the CCD image sensor (4G) for capturing the green image and the red image sensor for capturing the three primary colors of the subject image. Each CC for imaging and blue imaging
Spatial sampling is performed at positions where the D image sensors (4R) and (4B) are shifted by τ _S / 2. Thus, the CCD image sensor (4R), (4G), each imaging output signals read from (4B) S _{R *,} as S _{G *,} S _{B *} is that there is shown the spectral components in Figure 3 The sampling frequency fs component of the green imaging output signal SG _* by the CCD image sensor (4G) and the CCD image sensors (4R),
(4B) and a red imaging output signals S _{R *} and the blue image pickup output signals S _{B *} of the respective sampling frequency fs component are opposite phases to each other by.

Then, the sampling frequency fs read clock of the 4f _SF each CCD image sensor (4R), (4
G) and (4B) read out image pickup signals S _{R *} and S
_{G *} and SB _* are the buffer amplifier (5R) and (5
G) and (5B) are supplied to analog-to-digital (A / D) converters (6R), (6G), and (6B).

Each of these A / D converter (6R), (6G), the (6B), each imaging output signals _{S R *, S G *,} S B * clock rate or above CCD image sensor is equal to the sampling rate of the A clock having a clock frequency fs of 4f _SC , which is the same as the read clock of (4R), (4G), and (4B), is provided by a timing generator (not shown). Each of the A / D converters (6R), (6G), and (6B) converts each of the imaging output signals SR _* , _{RG *} , and SB _* to the clock rate of 4f _SC .
fs, digitized as it is, and each of the above imaging output signals S
_{R *, S G *, S} B * of the third respective color data _D having the same output spectra as the spectra shown in FIG _{R *, D G *,} to form a _{D B *.}

The A / D converter (6R), (6G), the color data _D obtained by _{(6B) R *, D G} *, D B * , the signal processing unit (7)
Supplied to

As shown in FIG. 4, the signal processing unit (7) includes a red data DR _* obtained by the A / D converter (6R) and the A / D converter, as shown in FIG. A detail signal generator (11) to which green data _{DG *} obtained by (6G) is supplied, and A / D converters (6R), (6G), (6
Three primary color data DR _* , _{DG *} , _{DB **} obtained by B)
Are supplied through delay circuits (12R), (12G), and (12B), and interpolation processing units (13R), (13G), and (13B), and these interpolation processing units (13R), (13G), and (13B) ) three primary data interpolated image from _{D R **, D G **,} D B ** and the detail signal generator (11) from the detail signal D _{IE **} is supplied adder (14R), ( 14G) and (14B), and gamma correction processing circuits (15R), (15G), and (15B) to which the added outputs of the adders (14R), (14G), and (14B) are supplied.

In the signal processing section (7), the interpolation processing section (13
R), (13G), and (13B) are the A / D converters (6R), (6
G), clock rate f of 4f _SC supplied from (6B)
By subjecting the three primary color data DR _* , _{DG *} , and DB _{* of s} to interpolation processing, the clock rate fs is doubled, that is, 8f.
s clock rate 2fs, 3 primary color data DR _** ,
_{DG **} and _{DB **} are formed.

Then, the interpolation processing units (13R), (13G), (13B)
Are the three primary color data DR _{** at} the clock rate of 2 fs,
_{DG **} , _{DB **} are added to the adders (14R), (14G), (14
B) to supply.

Further, the detail signal generating section (11) is provided with the A / D
Green data D of fs rate obtained by the converter (6G)
_{G *} and red data DR _* of the fs rate obtained by the A / D converter (6R) are multiplexed at a clock rate of ₂ fs and multiplexed at the same rate, and an equalizing addition is performed. And a digital filter for performing processing. The detail signal generator (11) is a detail signal D including a differential output from the digital filter as a horizontal detail signal IEH.
_{IE **} is supplied to the adders (14R), (14G), and (73B).

These adders (14R), (14G), and (73B) are provided with the three primary color data _{DR **} , _{DG **} , and DB _* from the interpolation processing units (13R), (13G), and (13B) _{. *} a by adding the detail signal D _{IE **} from the detail signal generator (11), the three primary color data _{D R **, D G **,} D B **
Is subjected to image enhancement processing. The image enhancement processed three primary color data _{D R **, D G **,} D B ** of the gamma correction processing circuit (15R), (15G), and supplies the (15B).

Then, the gamma correction processing circuits (15R), (15G),
(15B) is operated at a clock rate of 2fs, the adder (14R), (14G), (14B) 3 primary color data _{D R **} image enhancement processed by, _{D G **, D B * *} each subjected to gamma correction processing, and outputs the gamma correction processing each color data D _{R **} in _already, D _{G **,} a D _{B **} in 2fs rate.

As described above, in a color television camera device that employs a spatial picture element shifting method in the imaging unit, cross-color interference due to the incorporation of a detail signal into the aliasing component or the color subcarrier frequency region included in the imaging output becomes a problem. In the detail signal generator (11), the A / D converter (6
The green data DG _{* of the} fs rate obtained by G) and the above A
Data D of fs rate obtained by the / D converter (6R)
_{R *} and _{2 *} are multiplexed at a clock rate of 2 fs and added by equal amounts, and the horizontal detail signal IEH of 2 fs rate formed by differentiating the added output is a primary carrier by the above equal addition processing. All components are canceled. Therefore, the detail signal generator (11)
Can form a wideband horizontal detail signal IEH without aliasing. Therefore, in the adders (14R), (14G), and (73B), the interpolation processing unit (1
3R), (13G), (3 primary color data _{D R **} in 2fs rate from 13B), _{D G **,} horizontal detail signals 2fs rate from the detail signal generator (11) _{D B **} IEH by adding the detail signal D _{IE **} containing said three primary color data _{D R **, D G **,} can be subjected to image enhancement processing of the high resolution _{D B **.} Furthermore, the adder (14R), (14G), (14B) 3 primary color data _{D R **} image enhancement processed by, _{D R **,} D
_The above gamma correction processing circuit (15R) to which _{B **} is supplied,
(15G) and (15B) operate at the clock rate of 2 fs, respectively, so that the three primary color data DR _** , D
_{G **} and DB _** can be subjected to high-resolution gamma correction processing.

Here, the detail signal generation unit (11) adds an equal amount of the green image pickup signal and the red image pickup signal to the image pickup output signal from the image pickup unit adopting the spatial picture element shifting method, Even if the green image pickup signal and the blue image pickup signal are added in equal amounts, or the combined signal of the red image pickup signal and the blue image pickup signal is added in equal amounts with the green image signal, all the primary carrier components are canceled. As a result, it is possible to form a wide-band horizontal detail signal without aliasing.

Further, as shown in FIG. 5, the signal processing unit (7) includes first gamma correction circuits (17R), (17G), and (17B) operating at a clock rate of fs, respectively, as shown in FIG. 13R), (13G), and (13B), and a second gamma correction circuit (18) operating at a clock rate of 2 fs may be provided after the detail signal generator (11). .

The first gamma correction circuits (17R), (17G), (17
B) operates at the respective fs clock rate, fs
Rate three primary color data D _{R *,} D _{G *,} subjected to gamma correction processing D _{B *,} the three primary colors data D gamma-corrected _{R *,} D
_{G *} and DB _* are converted to the interpolation processing units (13R), (13G), (13
B). The interpolation processing units (13R), (13G), (13
B) is the first gamma correction circuit (17R), (17G),
Fs rate 3 with gamma correction by (17B)
Primary color data _{D R *, D G *,} by performing an interpolation process to the _{D B *,} 3 primary color data _{D R **} the 2fs rate, _{D G **, D
B **} is formed and supplied to the adders (14R), (14G) and (14B). Further, the second gamma correction circuit (18)
It operates at a clock rate of 2 fs, performs gamma correction on the 2 fs rate detail signal D _{IE **} output from the detail signal generator (11), and outputs the gamma corrected processed detail signal D _{IE **} as described above. Adder (14R), (14
G), (14B). Then, the adder (14
R), (14G), and (14B) are obtained from the first gamma correction circuits (17R), (17G), and (17B).
R), (13G), and (13B), gamma-corrected 2 fs-rate three-primary-color data D _{R **} , D _{G **} , D
_The image is obtained by adding the gamma-corrected 2fs-rate detail signal D _{IE **} supplied from the detail signal generator (11) via the second gamma correction circuit (18) to _{B **.} Perform enhancement processing.

By the signal processing unit of such a configuration (7), gamma correction processing and the three primary color data D _{R **} in 2fs rate which has been subjected to image enhancement processing with high _resolution, D _{G **,} D
_{B **} can be obtained.

In this embodiment, the above-described interpolation processing unit (13
R), (13G), and (13B) correspond to the interpolation processing unit (13R),
(13G) and (13B) correspond to the interpolation processing units (13R) and (13R).
G) and (13B) are the three primary color data DR _* and D at the fs rate.
H (z) _IPm = (Z ^-1 +1) ^{m where} _{G *} and DB _* operate at a clock rate 2fs of twice the above clock rate fs, that is, 8 fsc, and a unit delay amount of the 2fs rate is z. It is configured to include a digital filter that provides a filter characteristic H (z) _IPm as shown in FIG. 6 having at least one zero at fs indicated by ‥‥. In the detail signal generating section (11), the digital filter for differentiating the added output by the adding means is configured such that H (z) _IEHn = (Z ^-1 +1) ^n} , and the above-described interpolation processing units (13R), (13G), (13
The order n of the digital filter of B) is the same as the order m even and odd.
The differential processing is _performed by giving a filter characteristic H (z) _IEHn as shown in FIG. 7 having at least one zero point to fs.

Here, the interpolation processing units (13R), (13G), (13
If the order m and n of the digital filters of B) and the detail signal generating section (11) do not match, the interpolation processing sections (13R), (13G) and (13B) perform interpolation processing. And the group delay caused by the digital filter for differential processing for generating the detail signal in the detail signal generating section (11) is shifted, and the detail signal is added to the signal of the interpolation processing agent. However, image enhancement processing cannot be performed well. For example, the interpolation processing units (13R), (13G),
When the even-order (secondary) interpolation is performed in (13B) and the odd-order (first-order) differentiation is performed in the detail signal generation unit (11), as shown in FIG. 8, 1 / (2fs) adding the green data D _{R **} and red data D _{R **} in 2fs rate obtained by applying the respective secondary interpolation processing green data D _{G *} and red data D _{R *} of fs rate having a phase difference The center of the group delay of the luminance data Y _** obtained by the above is located at the position indicated by _PGPY in the figure, but the green data DG _* and the red data DR _* having the above fs rate at a clock rate of 2 fs. The center of the group delay of the horizontal detail signal IEH _** obtained by first-order differentiating the signal D _{(G + R) **} of the clock rate of 2fs, which is multiplexed and added by the same _amount , is indicated by _PGPIEH in the figure. As described above, the brightness Y
The group delay _** is _shifted by 1 / (4fs) from the center _PGPY of the group delay, and the horizontal detail signal IEH is added to the luminance data Y _**.
The waveform of the luminance data Y _{IEH **} that has been subjected to the horizontal contour compensation processing and obtained by adding and combining _** is not a point target.

On the other hand, in the signal processing circuit of this embodiment, the evenness and the oddness of the orders m and n of the digital filters of the above-described interpolation processing units (13R), (13G) and (13B) and the detail signal generation unit (11) match. As a result, the group delay by the digital filter for the interpolation processing and the group delay by the digital filter for the differentiation processing match the generation of the detail signal like the generation of the detail signal. Image enhancement processing.

For example, if the interpolation processing units (13R), (13G), and (13B) perform even-order (secondary) interpolation, and the detail signal generation unit (11) performs even-order (0th) differentiation, 9
As shown in FIG, 1 / Green fs rate data having a phase difference of (2fs) D _{G *} and red data D green data 2fs rate obtained _{by R *} each subjected to secondary interpolation processing D _{G * *} the red data D _{R **} center of the group delay of the luminance data Y _** obtained by adding the are there in the position shown by P _GPY in the figure, the green data D of the fs rate
_A horizontal detail signal IEH _* obtained by multiplexing _{G *} and red data DR _* at a clock rate of 2 fs and adding equal amounts of the signals to obtain a 2 fs clock rate signal D _{(G + R) **} and differentiating it to the 0th order _{. *} The center of the group delay is
As shown by _PGPIEH in the figure, the luminance data Y _** coincides with the center _PGPY of the group delay of the luminance data Y _** , and the luminance data Y _**
Luminance data Y of horizontal contour compensation processing agent obtained by adding and combining the horizontal detail signal IEH _** to _**
The waveform of _{IEH **} is point-symmetric with respect to the phase at the center of the group delay.

Also, if the interpolation processing units (13R), (13G), and (13B) perform odd-order (primary) interpolation, and the detail signal generation unit (11) performs odd-order (primary) differentiation, Tenth
As shown in FIG, 1 / Green fs rate data having a phase difference of (2fs) D _{G *} and red data D green data 2fs rate obtained _{by R *} in each primary interpolation performed D _{G * *} the red data D _{R **} luminance data obtained by adding the Y _** in the center of the group delay is in the position indicated by P _GPY in the figure, the green data D of the fs rate
_A horizontal detail signal IEH _** obtained by multiplexing _{G *} and red data DR _* at a clock rate of 2fs and adding equal amounts of the signal D _{(G + R) **} at a clock rate of 2fs and first-order differentiation. the center of the group delay, as shown by P _GPIEH in the figure, coincides with the center P _GPY of the group delay of the above-described luminance data Y _**, the luminance data Y _**
Horizontal detail signal IEH _** addition combined luminance data Y of horizontal contour compensation processed obtained by _{IEH **} in
Is point-symmetric with respect to the phase at the center of the group delay.

In this embodiment, the detail signal generator (1
As shown in FIG. 11, a specific example of the green data D obtained by the A / D converter (6G) is 1).
_A first delay circuit (21) having _{G *} as input data G _IN ;
Red data DR _* obtained by the A / D converter (6R)
_{Is provided} as the input data R _IN .

The first delay circuit (21) includes two 1H delay circuits (21) for applying a delay time equal to one horizontal scanning period 1H to an input signal using a digital delay means such as a D-type flip-flop.
a) and (21b) are connected in series. The first delay circuit (21) is provided for the green input data G _IN supplied from the A / D converter (6G) for the 0H delay output G _IN and the 1H delay output G _IN .
_1HDL and 2H delay output G _2HEDL to first comb filter (23)
To the delay circuit (13)
G) to the interpolation processing unit (14G).

Similarly, the second delay circuit (22) includes two 1H delay circuits (22a), which give a delay time equal to one horizontal scanning period 1H to the input signal using digital delay means such as a D-type flip-flop. (22b) are connected in series. The second delay circuit (22) converts the 0H delay output R _IN , 1H delay output R _1HDL and 2H delay output R _2HDL for the red input data R _IN supplied from the A / D converter (6G). And the 1H delay output is supplied to the interpolation processing unit (14R) via the delay circuit (13R).

The first comb filter (23) is connected to the A / D converter (6
From G) for green input data G _IN supplied to the first delay circuit (21), based on the three types of delay output G _IN from the first delay circuit (21), G _1HDL, the G _2HDL hand, Are given to the mixer circuit (25).

In addition, the second comb filter (24) converts the red input data R _IN supplied from the A / D converter (6R) to the second delay circuit (22) with the second delay circuit (24). twenty two)
Based on the above three types of delayed outputs R _IN , R _1HDL and R _2HDL from Are given to the mixer circuit (25).

The mixer circuit (25) is configured to output the filter outputs GH, GV, DG from the first comb filter (23) and the second
IEH ′ = GH + RH... IEV ′ = GV + α · RV (α = 0, 1/4, 1/2, 1)… LEV = GH + β, based on the filter outputs RH, RV, DR from the comb filter (24) • Outputs the combined output IEH ', IEV', and LEV of RH or LEV = DG + βDR (β = 0, 1).

The combined output IEH ′ by the mixer circuit (25) is
The filter output GH from the first comb filter (23) and the filter output RH from the second comb filter (24) are multiplexed at a clock rate of 2fs, and are added in equal amounts. The detail signal is supplied to the first digital filter circuit (26).

As described above, in this color television camera device employing the spatial picture element shifting method in the imaging unit, the red data DR _* and green obtained by the A / D converters (6R) and (6G) are also used. In the detail signal generator (11) to which the data _{DG *} is supplied, the above comb filter (22)
Filter output GH and the second comb filter (24)
By adding equal amounts of the filter output RH and the filter output RH in the mixer circuit (25), all the primary carrier components are cancelled, and a wideband horizontal detail signal IEH 'can be formed without aliasing. it can.

In addition, the above-described synthesis in which the filter output GV from the first comb filter (23) and the filter output RV from the second comb filter (24) are added at a ratio of 1: α by the mixer circuit (25). The output IEV 'is supplied to the second digital filter circuit (27) as a vertical detail signal.

Further, the filter output GH or DG from the first comb felter (23) and the filter output RH or DH from the second comb filter (24) are combined by the mixer circuit (25).
The combined output LEV added at the ratio of 1: β is supplied as a level signal to the level dependent signal generation circuit (28).

Then, the composite output IE is output from the mixer circuit (25).
The first digital filter circuit (26) wherein H 'is supplied as a horizontal detail signal having a clock rate of 2fs.
A fs having a high-pass filter characteristic having at least two or more even-numbered zeros in fs is used to form a horizontal detail signal at a rate of 2 fs.

The first digital filter circuit (26) has, for example, an equalized block configuration shown in FIG. A first filter block (41) represented by a transfer function H ₁ (z) of A second filter block (42) represented by the transfer function H ₂ (z) of A third filter block (43) represented by the transfer function H ₃ (z) of , A fourth filter block represented by a transfer function H ₄ (z), and a coefficient circuit (4) for providing weighting coefficients ap, β ₁ , β ₂ , and β _3.
5), (46), (47), (48) and the above coefficient circuits (4
6), (47), Adder circuit (4
9).

The first digital filter circuit (26) operates at a processing rate of 2fs, and gives a high-pass filter characteristic as shown in FIG. 13 to the composite output IEH 'from the mixer circuit (25). So, Of each filter output IEH, AP.

Here, the composite output IE is output from the mixer circuit (25).
H 'is the sum of the filter output GH from the first comb filter (23) and the filter output RH from the second comb filter (24). By (24), the band is limited in the vertical direction on the two-dimensional frequency space shown in FIG. The first digital filter circuit (26) having a high-pass filter characteristic having at least two zeros at fs near the color sub-carrier frequency f _SC of the composite color video signal has a horizontal band obtained by horizontal band limiting. The detail signal IEH is expressed by a chrominance subcarrier frequency SC (f _sc , 1/1) on the two-dimensional frequency space shown in FIG.
4) There is little unnecessary leakage component to the area, and high-quality horizontal contour enhancement processing can be performed without cross-color interference.

The filter output IEH from the first digital filter circuit (26) is supplied to the adder (29) as a horizontal detail signal, and the filter output AP is applied to a first core circuit (30) for performing nonlinear processing. The signal is supplied to the adder (34).

Further, the second digital filter circuit (27)
For example, as shown in FIG. 15, the vertical detail signal IE by the mixer circuit (25) is shown as an equalized block configuration.
V ′ A first filter block (51) for providing the transfer function H ₁ (z) of the above, and a filter output signal from the first filter block (51) and the vertical detail signal IEV ′ to select and switch the filter characteristics. 1 switching circuit block (52) and the first switching circuit block (5
2) to the first selected output signal A second filter block (53) that gives the transfer function H ₂ (z) of the above, a filter output signal from the second filter block (53) and the first selected output signal, and the filter characteristics are switched. A second switching circuit block (54), a coefficient circuit (55) for multiplying a second selected output signal by the second switching circuit block (54) by a weighting factor α, and an output from the coefficient circuit (55) At the signal And a third filter block (56) for providing a transfer function H ₃ (z) of

The second digital filter circuit (27) is formed by the above-mentioned comb filters (23) and (24). In response to the vertical detail signal IEV 'at the clock rate of fs given by the filter characteristic H (z), the operation is performed at the processing rate of fs, and as shown by the dashed line in FIG.
A filter characteristic H ₁ (z) having a zero point in the _SC, giving the filter characteristics H ₂ (z) having a zero point 2f _SC, the transfer function as indicated by a solid line in FIG H ₀ (z) , And supplies the vertical detail signal IEV to the addition circuit (29).

Here, the vertical detail signal IEV 'is equal to the first
And the filter output GV from the comb filter (23) and the filter output RV from the second comb filter (24) are added and synthesized. The comb filters (23) and (24) provide The band is limited vertically in the two-dimensional frequency space in FIG. The vertical detail signal IEV obtained by horizontally band-limiting the second digital filter circuit (27) having two or more zeros in the vicinity of the color sub-carrier frequency f _SC of the composite color video signal is the fourteenth signal. In the two-dimensional frequency space shown in the figure, there is little unnecessary leakage component to the color sub-carrier frequency SC (f _SC , 1/4) region, and high-quality vertical contour enhancement processing can be performed without cross-color interference. .

The adder circuit (29) operates at a processing rate of 2fs, and outputs a horizontal detail signal IEH at a clock rate of 2fs supplied from the first digital filter circuit (26) and the second digital filter circuit (27). ) And the vertical detail signal IEV of the clock rate of fs supplied from the above. The addition output signal at the clock rate of 2 fs by the addition circuit (29) is supplied to the multiplication circuit (32) via the second core circuit (31) that performs nonlinear processing.

The level dependent signal generating circuit (28) to which the combined output LEV from the mixer circuit (25) is supplied as a level signal generates a level dependent signal LD corresponding to the level signal LEV. The signal is supplied to the multiplication circuit (32) via a multiplication circuit (33) for multiplying the dependent signal by an LD weighting coefficient.

The multiplying circuit (32) adds the vertical pendant signal LD provided with the weight coefficient by the multiplying circuit (33) by the adding circuit (29) which has been subjected to the non-linear processing by the second core circuit (31). Multiplied by the output signal, the multiplied output signal is supplied to the adding circuit (34).

The addition circuit (34) adds a filter output AP of the first digital filter circuit (25), which has been subjected to the non-linear processing by the first core circuit (30), to a multiplication output signal of the multiplication circuit, The added output is output as a detail signal DIE _** having a clock rate of 2 fs.

The adders (14R), (14G), and (14B), to which the detail signal IE _{IE **} having the clock rate of 2 fs is supplied from the detail signal generating section (11) having such a configuration, are connected to the clock rate of 2 fs. the interpolation processing section the detail signal D _{IE **} of (13R), (13G), 3 primary color data _{D R **} in 2fs rate supplied from _{(13B), D G **,} D B **
To perform image enhancement processing.
The adders (14R), (14G), and (14B) provide the three primary color data _{DR **} , D having undergone the image enhancement processing.
_{G **} , DB _** are _converted to the above gamma correction processing circuit (15R), (1
5G) and (15B).

The above gamma correction processing circuit (15R), (15G), (15B)
Are the two primary color data _{DR **} , image-enhanced processed by the adders (14R), (14G) and (14B).
D _{G **,} subjected to gamma correction processing _{D B **,} 3 primary color data _{D R **} gamma-corrected, _{D G **,} and outputs the _{D B **.}

In this manner, the signal processing unit (7), the image enhancement processing and the three primary color data D _{R **} in 2fs clock rate which has been subjected to gamma correction _processing, D _{G **,} and outputs the D _{B **.} The 2f output from the signal processing unit (7)
s clock rate three primary color data _{DR **} , _{DG **} , D
_{B **} is supplied to a color encoder (8), and a digital / analog (D / A) converter (9R), (9
G), (9B).

And the D / A converters (9R), (9G), and (9B)
The three primary color data DR _** , D which ensure the high resolution of the clock rate of 2 fs supplied from the signal processing unit (7)
_{G **} and DB _** are converted to analog, and the three primary color image pickup output signals R _OUT , G _OUT and B _OUT are converted to signal output terminals (10R), (1
0G) and (10B).

As shown in FIG. 17, a specific configuration of the color encoder (8) is supplied from the signal processing unit (7) to the three primary color data D at a clock rate of 2 fs.
_{R **, D G **,} delay _{circuit D B **} is a matrix circuit (81) supplied, the luminance signal data _{D Y **} formed by the matrix circuit (81) is supplied (82)
And low-pass filters (83), (84) to which the respective color difference signal data DR _{-Y *} , DB _{-Y *} , DI _* , and _{DQ *} formed by the matrix circuit (81) are supplied. , (85),
(86) and D _{I *} and D _{Q *} formed by the matrix circuit (81) are the low-pass filters (85) and (86).
A modulation circuit (87) supplied through the interpolator, an interpolation processing circuit (88) supplied with modulation output data from the modulation circuit (87), and an interpolation processing output data supplied from the interpolation processing circuit (88). And the above matrix circuit (81)
And an adder circuit (89) supplied with the luminance signal data _{DY **} formed through the above-mentioned delay circuit (82).

Said matrix circuit (81), the three primary colors data D _{R **} clock rate of the _2fs, D _{G **,} D _B by performing the matrix calculation processing for _**, the clock rate of 2fs luminance signal data D _{Y **} a dye signal data clock rate _{fs D R-Y *, D} B-Y *, D I *, D
Form _{Q *} .

Then, the color ene emissions coder (8), the three primary color data _{D R **, D R **,} D B as a component color image data for _**, the matrix circuit from (81) the delay circuit (82) and outputs the luminance signal data D _{Y **} through, said matrix circuit (81) from each of the low-pass filter (83), each of the color difference signal data D _{R- *} via _(84), D _{B- Y *} is output. The delay circuit (82) gives the delay characteristics corresponding to the low-pass filters (83) and (84) to the luminance signal data _{DY **} .

Further, in the color encoder (8), the modulation circuit (87) is supplied from the matrix circuit (81) through the low-pass filters (85) and (86).
A modulation process for performing two-phase modulation of _{I *} and _{DQ *} is performed. The modulation output data from this modulation circuit (87) is the color subcarrier frequency
This corresponds to a modulated color difference signal including odd harmonics of f _SC .

Further, the interpolation processing circuit (88) calculates the f _SC component and the 7f _SC component of the modulation output data from the modulation circuit (87).
Perform digital filtering to extract components,
Modulated color difference signal data having a clock rate of 24 fs corresponding to 8 f _SC is formed.

The color encoder (8) includes the luminance signal data _{DY **} output from the matrix circuit (81) via the delay circuit (82) and the interpolation processing circuit (8).
The digital composite video signal D _{CS **} is formed by adding the modulated color difference signal data of the clock rate of 2 fs formed in 8) by the above-mentioned addition circuit (89).

That is, the color encoder (8) performs the 3 fs primary color data D of the clock rate of 2 fs which has been subjected to the image enhancement processing and the gamma compensation processing by the signal processing section (7).
_{R **,} D _{G **,} D _B for _**, the luminance signal data D which ensures a high clock rate of the 2fs resolution
_{Y **} and, each color difference signal data D clock rate of fs _{R-Y *,} and outputs the component color image data consisting of D _{B-Y *} city, ensuring a high clock rate of the 2fs resolution The digital composite video signal D _{CS ** is} output.

The component color image data output from the color encoder (8), that is, the luminance signal data _{DY **} and the respective dye signal data DR _{-Y *} , D
_{BY *} is a digital / analog (D / A) converter (9
Y), (9R-Y) and (9B-Y).

The D / A converters (9Y), (9R-Y), and (9B-Y)
By converting the luminance signal data _{DY **} and the respective color difference signal data DR _{-Y *} and DB _{-Y *} into analog, analog component color video signals Y _OUT , R-Y _OUT , and B-
Y _OUT as a signal output terminal (10Y), (10R-Y ), (10B
-Y).

Further, the digital composite video signal D _{CS **} output from the color encoder (8) is supplied to a digital / analog (D / A) converter (9CS). The D / A converter (9CS), the signal output terminal (1 the digital composite video signal D _{CS **} that ensures a high clock rate of the 2fs resolution as an analog composite video signal OS _OUT by analogized
0CS).

H Effects of the Invention As described above, in the signal processing circuit of the solid-state imaging device according to the present invention, each imaging output signal read at a sampling rate of fs from each solid-state image sensor of the imaging unit that employs the spatial pixel shifting method. For the digital output signal digitized at the clock rate equal to the sampling rate fs by the analog-to-digital conversion means, a 2 fs rate signal is formed by the interpolation means, and a 2 fs wide band wide detail signal is formed by the detail signal generation means. Then, by adding and synthesizing these signals by the adding means, high-resolution image enhancement processing can be performed at a rate of 2 fs.

In the signal processing circuit of the solid-state imaging device according to the present invention, gamma correction is performed on the output signal of the adding means by gamma correction means operating at a clock rate of 2 fs, thereby enhancing image enhancement at the clock rate of 2 fs. For the digital output signal to be processed,
Gamma correction can be properly performed.

Further, according to the present invention, the first gamma correction means operating at the clock rate of fs performs gamma correction processing on the output signal to the analog / digital conversion means,
The second gamma correction means operating at a clock rate of s performs gamma correction processing on the detail signal, thereby performing gamma correction processing on the digital output signal subjected to image enhancement processing at the clock rate of 2 fs. It can be applied properly.

Therefore, according to the present invention, the imaging output signal from each solid-state image sensor of the imaging unit employing the so-called spatial picture element shifting method is digitized, and a detail signal for performing image enhancement processing is formed by digital signal processing. In the signal processing circuit of the solid-state imaging device, the image output signals read from each solid-state image sensor at a sampling rate of fs are appropriately subjected to high-resolution image enhancement processing and gamma correction processing at a 2 fs rate. Can be.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a three-panel color television camera apparatus to which the present invention is applied, FIG. 2 is a schematic view showing an arrangement state of each CCD image sensor in the three-panel color television camera apparatus, and FIG. FIG. 4 is a diagram showing a signal spectrum of each imaging output signal by the CCD image sensor in the color television camera device. FIG. 4 is a block diagram showing a configuration of a signal processing unit constituting the three-panel color television camera device. FIG. 5 is a block diagram showing another configuration example of the signal processing unit, FIG. 6 is a characteristic diagram showing characteristics of a digital filter provided in an interpolation processing unit constituting the signal processing unit, and FIG. FIG. 8 is a characteristic diagram showing the characteristics of a digital filter provided in a detail signal generator constituting a signal processor. FIG. FIG. 9 is an explanatory diagram of the horizontal contour enhancement processing when the detail signal generation section performs odd-order differentiation processing. FIG. 9 shows an even-order interpolation processing performed by the interpolation processing section and performs even-order differentiation processing by the detail signal generation section. FIG. 10 is an explanatory diagram of a horizontal contour emphasizing processing operation when performing, FIG. 10 is an explanatory diagram of a horizontal contour emphasizing processing operation when performing odd-order interpolation processing in the interpolation processing section and performing odd-order differentiation processing in the detail signal generating section, FIG. 11 is a block diagram showing a specific configuration example of a detail signal generation unit of the signal processing unit, and FIG. 12 is a block diagram showing an equivalent block structure of a first digital filter circuit of the detail signal generation unit. FIG. 13 is a characteristic diagram showing the filter characteristics of the first digital filter circuit, and FIG. 14 is a two-dimensional frequency characteristic of the detail signal generated by the detail signal generator. FIG. 15 is a schematic diagram showing a space, FIG. 15 is a block diagram showing an equalizing block configuration of a second digital filter circuit of the detail signal generator, and FIG. 16 is a filter characteristic of the second digital filter circuit. FIG. 17 is a block diagram showing a configuration of a color encoder constituting the three-panel type color television camera device. FIG. 18 is a schematic diagram showing a signal spectrum of an image pickup output signal by a general solid-state image sensor having a discrete picture element structure. (4R), (4G), (4B) CCD image sensor (6R), (6G), (6B) A / D converter (7) Signal processing unit (8) Color encoder ( 11) Detail signal generator (13R), (13G), (13B) Interpolator (14R), (14G), (14B) Adder (15R), (15G), (15B) ... Gamma correction circuit (17R), (17G), (17B) ... First gamma correction circuit (18) ... Second gamma correction circuit (26) ... Digital filter circuit

Claims (3)

(57) [Claims] The solid-state image sensor for capturing a green image and the solid-state image sensors for capturing a red image and a blue image are spatially shifted by a half of a repetition pitch of each pixel. Analog-to-digital conversion means for digitizing each imaging output signal read from the solid-state image sensor at a sampling rate of fs at a clock rate equal to the sampling rate fs; and a green image among the digital output signals of the analog-to-digital conversion means. A clock rate that is twice the sampling rate fs from the signal obtained by adding the image signal and the red image image signal, the blue image image signal, or the combined signal of both signals in equal amounts
Detail signal generating means for generating at least a horizontal detail signal of 2 fs; interpolation means for interpolating the digital output signal of the analog / digital changing means to a clock rate of 2 fs; output signal of the detail signal generating means to the interpolation means A signal processing circuit of a solid-state imaging device, comprising: an adding unit that adds an output signal. 2. The signal processing circuit according to claim 1, further comprising gamma correction means for performing gamma correction processing on an output signal of said adding means. 3. A first gamma correction means, which operates at a clock rate of fs and performs gamma correction processing on an output signal of the analog / digital conversion means, is provided before the interpolation means, and operates at a clock rate of 2 fs. 2. The signal processing circuit according to claim 1, further comprising a second gamma correction unit that performs a gamma correction process on an output signal of the detail signal generation unit.