JP2000124409A - Structure of semiconductor memory device formed by use of ferroelectric substance - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a semiconductor memory device where a ferroelectric substance is used to be enhanced in degree of integration by a method wherein a cell is lessened in area so as to realize a finer cell structure. SOLUTION: A semiconductor memory device is equipped with a ferroelectric film, the ferroelectric film is pinched in between the two opposed electrodes for the formation of a capacitor, the capacitor is capable of holding binary data on a direction in which the ferroelectric film is polarized, a non-volatile semiconductor memory device is equipped with a structure where the capacitor is connected to the source or drain of a control transistor, the adjacent control transistors are possessed of bit lines in common, also the adjacent capacitors are possessed of plate lines in common, and the above capacitors are arranged above the control transistors.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor memory device using a ferroelectric film, and more particularly to a structure of a nonvolatile memory capable of reducing the element area of the semiconductor memory device and enabling a high degree of integration. Things.

[0002]

2. Description of the Related Art The literature name "Semiconductor device and its manufacturing method", Takeo Matsuki, Yoshihiro Hayashi, JP-A-8-17822 Conventional ferroelectric memories include those disclosed in the above-mentioned documents. FIG. 15 is a schematic diagram of a conventional semiconductor memory device using a ferroelectric substance. Hereinafter, a brief description will be given with reference to FIG. First, an element isolation region (102), a gate oxide film (103), and a gate electrode (1) are formed on a semiconductor substrate (101).
04), a base structure including a source / drain region (105) and an interlayer insulating film (106) is formed, and a lower electrode (plate electrode) (109), a ferroelectric film (110), and an upper electrode (111) are separated. It is formed on the region (102) and processed.

After forming an interlayer insulating film, a contact (113) is opened to connect the semiconductor and the capacitor.
The connection is established by the wiring (114). According to this structure,
Since the ferroelectric film can be formed in a flat region, element failure can be prevented, and the wiring can be formed of Al with good workability, so that the capacitor can be easily formed.

[0004]

FIG. 16 is a schematic view of the semiconductor memory device shown in FIG. 15 as viewed from above. Here, a 2 × 2 memory array is shown as an example. FIG.
In the structure shown in the figure, when arranged in an array,
Is a useless space that is hardly stacked. Therefore, there is a problem that the occupied area per cell is large, and high integration is difficult due to a useless space portion.

[0005]

SUMMARY OF THE INVENTION The present invention relates to a semiconductor memory device using a ferroelectric film, which is formed by sandwiching a ferroelectric film between two opposing electrodes. In a nonvolatile semiconductor memory device having a structure in which a capacitor capable of storing binary information according to a polarization direction is connected to a source or a drain of a control transistor, a bit line is shared between adjacent control transistors. In addition, adjacent capacitor elements share each plate line, and the capacitor elements are arranged on the control transistor, so that useless space is eliminated and high integration can be easily performed. .

[0006]

Embodiments of the present invention will be described below with reference to the drawings. The drawings are only schematically shown to the extent that the present invention can be understood, and thus the present invention is not limited to the illustrated examples.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a capacitor structure which can be formed with higher integration and can be easily formed in a semiconductor memory device using a ferroelectric. The underlayer structure, numerical values and the like according to the present invention are not limited at all.

In the present invention, a bismuth strontium tantalate film (SrBi ₂ Ta ₂ O ₉ film: hereinafter referred to as SB) is used as a ferroelectric film.
The following description will be made by taking a T film as an example, but any ferroelectric material having hysteresis characteristics can be used.

FIG. 1 is a sectional view of a semiconductor memory device according to the present invention. FIG. 2 shows a cell circuit diagram of the semiconductor memory device of the present invention. The features of the memory cell structure of the present invention are as follows.
It has a structure in which two capacitive elements are formed in one active region, and a bit line contact is shared between adjacent control transistors, and a bit line is formed below the capacitive element. In addition, the structure is such that plate lines of adjacent capacitance elements are shared.

FIGS. 3 to 8 show one example of a sectional view of a manufacturing process of a semiconductor memory element according to the present invention. Also,
FIGS. 9 to 14 are top views corresponding to respective process cross-sectional views as viewed from above. In each case, the same parts are denoted by the same reference numerals.

FIG. 3 shows an N-type MOS transistor formed on a P-type silicon substrate (1) by a known technique.
This transistor includes an element isolation region (2), an N ⁺ diffusion layer (3), a gate electrode (4), and a gate oxide film (5). On this substrate, an interlayer insulating film (6) is formed at 8000 ° by a known method. Next, CMP (Chemical Mec
The interlayer insulating film is flattened using a hanical polishing technique. A flat surface can be obtained by removing 2000 mm of the interlayer insulating film on the substrate by CMP. This is as shown in FIG. 9 when viewed from above.

Next, a bit line is formed. A W (tungsten) film is used for the bit line. First, a contact hole (7) for a bit line is opened. Then, a titanium nitride film (not shown) is formed as a barrier metal,
A W film is formed by the VD method. Thereafter, the W film and the titanium nitride film are entirely etched back to form a W film (8) only in the contact hole (FIGS. 4 and 1).
0).

A titanium nitride film (not shown) and a W film are sequentially formed again on the entire surface of the substrate. Thereafter, the W film is processed by a known photolithography / etching technique to form a bit line (9) (see FIGS. 5 and 11).

A capacitor is formed on the above substrate. An interlayer insulating film (10) is formed on this substrate, and the above-described CMP is performed.
After the surface is flattened by a technique, a Pt (platinum) film is formed as a lower electrode (11) by 2000 °. Next, a ferroelectric film (12) is formed on the lower electrode. The formation method is as follows. A solution obtained by dissolving the above-mentioned SBT in an organic solvent is spin-coated and dried (by a hot plate for 15 minutes).
After repeating the steps of 0 ° C. for 5 minutes and temporary firing (electric furnace, 650 ° C., 60 minutes in an oxygen atmosphere) five times, main firing (80
(0 ° C., 60 minutes in a dry oxygen atmosphere) to crystallize the ferroelectric film (12).

By this processing, the thickness of the SBT film becomes 2500 °. On this film, a Pt film is formed as an upper electrode (13) at 2000. These films are patterned by a known photolithography technique, and the upper electrode (13) and the SBT film (1) are formed by a known dry etching.
2) Etch the lower electrode (11). At this time, the upper electrode (13) and the SBT film (12) are arranged apart from each other so that the plate lines of adjacent elements can be shared (FIG. 6,
See FIG. 12). Through the above steps, a capacitor is formed.

An interlayer insulating film (14) is further formed on the substrate, a contact hole (15) penetrating to the N + diffusion layer is formed by a known photolithography / etching technique, and then a TiN film (not shown), An AL (aluminum) film (16) containing% silicon is formed. Again, by the known photolithographic etching, the N
⁺ The connection between the diffusion layer (3) and the upper electrode (13) of the capacitor is made (see FIGS. 7 and 13).

Further, an interlayer insulating film (17) is formed, a contact hole (18) penetrating to the lower electrode (11) is opened, and a plate wiring (19) is formed.
A semiconductor memory element as shown in FIG. 14 can be formed. The material of the plate wiring is not particularly limited, but an AL film or the like is preferably used.

[0018]

As described in detail above, not only is the capacitor formed on the control transistor so that the plate line of the adjacent capacitor can be shared, but also the bit line contact of the control transistor can be formed. By sharing, there is no useless space described in the conventional example, so that the occupied area per cell can be significantly reduced as compared with the conventional memory cell, and high integration can be realized.

[Brief description of the drawings]

FIG. 1 is a sectional structural view of a semiconductor memory element of the present invention.

FIG. 2 is a cell circuit diagram of the semiconductor memory device of the present invention.

FIG. 3 is a sectional view (a) of a manufacturing process of the semiconductor memory element of the present invention.

FIG. 4 is a cross-sectional view (b) showing a manufacturing process of the semiconductor memory element of the present invention.

FIG. 5 is a sectional view (c) of a semiconductor memory device according to the present invention during the manufacturing process.

FIG. 6 is a sectional view (d) showing a manufacturing process of the semiconductor memory element of the present invention.

FIG. 7 is a sectional view (e) of a manufacturing process of the semiconductor memory element of the present invention.

FIG. 8 is a sectional view (f) of a semiconductor memory device according to the present invention during the manufacturing process.

9 is a front view (a) corresponding to FIG. 3, as viewed from above.

FIG. 10 is a top view (b) corresponding to FIG.
It is.

11 is a top view corresponding to FIG. 5, as viewed from above (c).
It is.

FIG. 12 is a top view (d) corresponding to FIG.
It is.

FIG. 13 is a top view (e) corresponding to FIG. 7 and viewed from above.
It is.

FIG. 14 is a top view (f) corresponding to FIG.
It is.

FIG. 15 is a schematic view of a conventional semiconductor memory device using a ferroelectric substance.

16 is a schematic view of the semiconductor memory element shown in FIG. 15 as viewed from above.

[Explanation of symbols]

(7) Bit line contact hole (8) Buried W (9) Bit line (11) Lower electrode (12) Ferroelectric film (13) Upper electrode (15) Contact hole penetrating to N ⁺ diffusion layer (16) AL Film (18) Contact hole penetrating to lower electrode (19) Plate wiring

Claims (1)

[Claims] 1. A semiconductor memory device using a ferroelectric film, wherein said ferroelectric film is formed by sandwiching said ferroelectric film between two opposing electrodes, and a binary value is determined according to a polarization direction of said ferroelectric film. In a semiconductor memory device having a structure in which a capacitor capable of storing information is connected to a source or a drain of a control transistor, adjacent control transistors share a bit line, and adjacent capacitors are connected to each other. Wherein the respective capacitor lines share the respective plate lines and the capacitor element is disposed on the control transistor.