JP2000123576A - Volatile semiconductor memory and data processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a cycle time at the time of using the same pre-charge circuit with a read-cycle and a write-cycle. SOLUTION: This device is provided with plural word lines WL, plural bit lines BL, BL* arranged so as to intersect with word lines WL, a pre-charge circuit 10 for pre-charging bit lines, and a control means 7 for controlling word lines selecting operation and pre-charge operation so that a word line selecting time and a pre-charge off-time in a write-cycle are made shorter than a word line selecting time and a pre-charge off-time in a read-cycle respectively, a word line selecting time and a pre-charge time are optimized, and shortening a cycle time is achieved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an internal timing control technique for a semiconductor memory device, for example, an SRAM (Stat
ic Random Access Memory; static random
The present invention relates to a technique for shortening (speeding up) a cycle time by optimizing a word line selection time in an access memory) and a precharge off time in each operation.

[0002]

2. Description of the Related Art In a static memory such as an SRAM, in order to prevent a malfunction, a sense amplifier is activated after a potential difference between a pair of bit lines (complementary bit lines) reaches a level necessary for data reading. It is necessary that the output latch circuit latch the output of the sense amplifier after the output of the sense amplifier is determined. Therefore, in order to synchronize the activation timing of the sense amplifier and the latch timing of the output latch circuit with the operation of changing the state of the complementary bit line according to the storage information of the addressed memory cell, an external signal such as a memory access strobe signal is used. The clock signals are each delayed by a predetermined time by a delay circuit to generate a sense amplifier activation signal and an output latch control signal.

[0003] As an example of a document describing a synchronous RAM, see "Microcomputer Handbook", No. 25, published by Ohm Co., Ltd. on December 25, 1985.
There are 3 pages and 254 pages.

[0004]

As a technique for increasing the operation speed of a semiconductor memory, "ISSCC97 /
SESSION24 / NON-VOLATILE MEMORI AND SRAM / PAPER SP24.
5), the read and write precharge MOS transistors are separately provided.
There is known a technique for increasing the operation speed by changing the size of an S transistor.

However, the provision of separate precharge MOS transistors for read and write is not
As compared with the case where the same precharge circuit is used in the read cycle and the write cycle, the area occupied by the chip of the precharge circuit is increased.

On the other hand, there is a method in which the same precharge circuit is used in a read cycle and a write cycle. In this case, it is advisable to control the precharge operation under exactly the same conditions in the read cycle and the write cycle. is not. This is because when the data line precharge method is used, the write operation is generally faster than the read operation, and the word line selection time can be shorter in the write cycle than in the read cycle. This is because it is necessary to make the write cycle longer than the read cycle. Therefore, when the same precharge circuit is used in the read cycle and the write cycle, the cycle time can be reduced by optimizing the word line selection time and the bit line precharge time in the read cycle and the write cycle. It is possible that
It has been found by the present inventor.

An object of the present invention is to provide a technique for shortening the cycle time when the same precharge circuit is used in a read cycle and a write cycle.

[0008]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, a plurality of word lines (WL), a plurality of bit lines (BL, BL *) arranged to intersect the word lines, and a precharge circuit (precharge circuit) for precharging the bit lines. 10), the word line selection time and the precharge off time in the write cycle are shorter than the word line selection time and the precharge off time in the read cycle, respectively. And control means (7) for controlling the word line selection operation and the precharge operation.

[0010] According to the above means, the control means controls the word line selection time and the precharge off time in the write cycle to be shorter than the word line selection time and the precharge off time in the read cycle, respectively. The selection operation and the precharge operation are controlled. While the word line selection time can be shorter in the write cycle than in the read cycle, the bit line precharge time must be longer in the write cycle than in the read cycle. For this reason, as described above, the word line selection between the read cycle and the write cycle is performed so that the word line selection time and the precharge off time in the write cycle are shorter than the word line selection time and the precharge off time in the read cycle, respectively. Cycle time can be reduced by optimizing bit line precharge.

At this time, a read / write pulse for forming a read clock signal and a write clock signal having a pulse width narrower than the read clock signal based on an externally applied read / write signal as a signal for instructing read / write. A width control circuit (72) and a first control logic (73, 72) for forming control signals for a word line selection operation and a precharge operation based on the read clock signal and the write clock signal output from the read / write pulse width control circuit. 74), the control means can be easily configured.

Also, a second control logic (76) for forming a control signal for selecting a specific bit line from the plurality of bit lines in synchronization with the read clock signal, and in synchronization with the write clock signal A third control logic (75) for forming a control signal for controlling the operation of the write amplifier.

[0013] A data processing device can be configured to include the volatile semiconductor memory device and a central processing unit capable of accessing the same.

[0014]

FIG. 6 shows a configuration example of a computer system including a data processing device according to the present invention.

The computer system shown in FIG.
Microcomputer 3 via system bus BUS
1. SDRAM (synchronous dynamic random access memory) 32, SRAM (static random access memory) 33, ROM (read only memory) 34, peripheral device control unit 35, display control unit 36, etc. Are communicably connected to each other to perform predetermined data processing according to a predetermined program. The microcomputer 31 is an example of a data processing device according to the present invention, and is a logical core of the present system, and mainly includes address designation, information reading and writing, data operation, instruction sequence, and interrupt acceptance. And a function for starting information exchange between the storage device and the input / output device. The SDRAM 32 or the SRAM 3
3, and the ROM 34 are positioned as internal storage devices. Various data are stored in the SDRAM 32.
The OM 34 stores programs required for calculation and control by the CPU 30. The SRAM 33 is used as a main memory, a cache memory, or the like, making use of the high-speed read / write operation. The peripheral device control unit 35 controls the operation of the external storage device 38 and controls the input of information from the keyboard 39 and the like.
The information display on the CRT display 40 is performed by the control of 6.

FIG. 7 shows a configuration example of the microcomputer 31.

As shown in FIG. 7, the microprocessor 1 is not particularly limited, but has a CPU (Central Processing Unit).
53, built-in ROM (read only memory) 51,
It includes various functional blocks such as a built-in RAM (random access memory) 52, a timer 54, an interrupt controller 57, and first to ninth ports 41 to 49 for inputting and outputting various signals. It is commonly connected to the upper data bus DBUSU and the like, and is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique.

Also, external terminals P10-P17, P20-P24, P30-P37, P30 coupled to a number of external terminals, for example, input / output terminals of the first through ninth ports 41-49.
40 to P47, P50 to P57, P60 to P63, P7
0 to P77, P80 to P87, P90 to P97, and the like.

The built-in ROM 51 is a program memory for storing a program to be executed by the CPU 53. Although not particularly limited, the upper data bus DBUSU and the lower data bus DBUS each having an 8-bit width are used.
By being coupled to the CPU 53 via L, 2-state memory access is enabled regardless of byte data or word data. Although not particularly limited, a mask signal ROM in which a program is written in the manufacturing process (photomask) is applied to the built-in ROM 51.

Although not particularly limited, the built-in RAM 52 is a synchronous SRAM (static random access memory) that operates in synchronization with a clock signal generated inside the microcomputer 31. This built-in S
The RAM 52 is not particularly limited.
By being connected via the upper data bus DBUSU and the lower data bus DBUSL each having an 8-bit width, two-state memory access is enabled regardless of byte data or word data.

The timer 54 includes various timers such as a watchdog timer, a 16-bit free running timer, an 8-bit timer, and a PWM (pulse width modulation) timer.

FIG. 1 shows a configuration example of the built-in RAM 52.

Reference numeral 15 denotes a memory cell array in which a plurality of static memory cells are arranged in a matrix. The selection terminals of the memory cells are connected to word lines in each row direction, and the data input / output terminals of the memory cells are complementary in each column direction. It is coupled to a bit line (also called a complementary data line). Each complementary bit line is commonly connected to a complementary common line via a column selection circuit 18 including a plurality of column selection switches coupled one-to-one to the complementary bit lines.

The row address signal AX input from outside the built-in RAM 52 is transmitted to the subsequent row decoder 14 via the row address buffer 13 arranged corresponding thereto and decoded. In addition, this built-in RA
Column address signal AY input from outside of M52
Is transmitted to a subsequent column decoder 17 via a column address buffer 16 arranged corresponding thereto and decoded.

The controller 7 controls the operation of the built-in RAM 52 as a whole. For example, a decode output from the row decoder 14, a decode output from the column decoder 17, a read / write signal R / W supplied from outside the built-in RAM 52, an external clock signal CK, and the like are supplied. Based on these various input signals, a word line selection signal included in the memory cell array 15 and an operation control signal of the write amplifier 8, the precharge circuit 10, the column selection circuit 18, and the sense amplifier 19 are formed.

In a read cycle, when a word line corresponding to an input address signal is driven to a selected level, a memory cell coupled to the word line is selected, and the memory cell data is output to a complementary bit line. The data on the complementary bit line is transmitted to the complementary common line when the column selection switch corresponding to the column address signal is turned on, amplified by the sense amplifier 19, and then output from the internal RAM 52 via the output circuit 20 at the subsequent stage. Is output to

In the write cycle, the built-in RAM
When the data fetched from outside the device 52 via the input circuit 9 is transmitted to the write amplifier 8, the complementary bit line is driven by the write amplifier 8 in accordance with the write data. The charge information corresponding to the data is stored in the memory cell of the above.

Since the built-in RAM 52 is of a clock signal synchronous type, the row address buffer 13, the row decoder 1
4, column address buffer 16, column decoder 17
Are the clock signals CK provided externally, respectively.
In synchronization with the internal clock signal ICK generated based on the Here, the clock signal CK is a clock signal generated by the microcomputer 31.

The precharge circuit 10 recovers the complementary bit line by adjusting the potential of the complementary bit line to the level of the high potential power supply Vdd at a predetermined timing in the read cycle and the write cycle.

The controller 7 performs the word line selection operation and the pre-charge off operation so that the word line selection time and the pre-charge off time in the write cycle are shorter than the word line selection time and the pre-charge off time in the read cycle, respectively. Control means for controlling the charging operation is included. This will be described later in detail.

FIG. 2 shows an example of a main configuration of the controller 7 and an example of a circuit related thereto.

The controller 7 includes a clock signal generator 71 for forming a predetermined internal clock signal ICK based on the external clock signal CK, and a clock signal IC generated by the clock signal generator 71.
K and a read clock signal RCK and a write clock signal WCK based on a read / write signal R / W from outside.
And a read / write pulse width control circuit 72 for forming Further, an OR gate 74 for obtaining an OR logic of the read clock signal RCK and the write clock signal WCK is provided, and the OR gate 74 and the row decoder 1 are provided.
AND gate 7 for obtaining AND logic with output signal Xi
3, the output signal of the OR gate 74 and the row decoder 1
AND gate 73 which obtains AND logic with the output signal of No. 4
And the write clock signal WCK and the column decoder 1
AND gate 7 for obtaining AND logic with output signal Yi
5, a NAND gate 76 for obtaining NAND logic with the read clock signal RCK, and an inverter 77 for inverting an output signal of the NAND gate 76.

The output terminal of the AND gate 73 is coupled to the corresponding word line WL to drive the corresponding word line to a selected level. Here, the word line WL is one representatively shown among a plurality of word lines. One memory cell MC is coupled to a word line WL and complementary bit lines BL, BL * (* indicates low active or signal inversion) arranged so as to cross the word line WL.

The output signal of the OR gate 74 is supplied to the precharge circuit 10 as an operation control signal of the precharge circuit 10. The precharge circuit 10 includes p-channel MOS transistors Q1, Q2, and Q3 in which complementary bit lines BL and BL * are short-circuited.
The p-channel MOS transistors Q1, Q2, Q
The output signal of the OR gate 74 is transmitted to the third gate electrode.

The output signal of the AND gate 75 is supplied to the write amplifier 8 as an operation control signal for the write amplifier 8. The output signal of the NAND gate 76 is supplied to the column selection circuit 1
8 is supplied to the column selection circuit 18 as an operation control signal. Here, the column selection circuit 18 includes p-channel MOS transistors Q4 and Q5 for selectively coupling the complementary bit lines BL and BL * to a common line, and the gate electrodes of the MOS transistors Q4 and Q5 are An output signal of the NAND gate 76 is supplied.

The output signal of the inverter 77 is
The operation control signal of the sense amplifier 19 is supplied to the sense amplifier 19.

The operation will be described.

FIG. 3 shows the operation timing of the main part.

The read cycle and the write cycle are alternately repeated in synchronization with the external clock signal CK.

In the read cycle, the rising and falling timings of the waveform of the internal clock signal ICK are determined in synchronization with the rising edge of the waveform of the external clock signal CK. The read clock signal RCK is synchronized with the rising edge of the internal clock signal ICK.
Is determined, and the falling timing of the read clock signal RCK is determined in synchronization with the falling edge of the waveform of the internal clock signal ICK.

The write clock signal W in the write cycle is synchronized with the rising edge of the internal clock ICK.
The rising and falling timings of the CK waveform are determined.

The OR logic of the read clock signal RCK and the write clock signal WCK is obtained by the OR gate 74, and the AND logic of the OR gate 74 and the output signal Xi of the row decoder 14 is obtained by the AND gate 73. The period during which the word line is driven to the selected level by the gate 73 is shorter in the read cycle than in the write cycle.

The OR logic of the read clock signal RCK and the write clock signal WCK is obtained by the OR gate 74, and the operation of the precharge circuit 10 is controlled by the output signal of the OR gate 74. The period during which the charge signal PC * is negated to the high level, that is, the precharge off period (precharge off time) is longer in the read cycle than in the write cycle. The reason why the word line selection time and the precharge off time in the write cycle are controlled to be shorter than the word line selection time and the precharge off time in the read cycle, respectively, is as follows.

First, the reason for lengthening the word line selection time in the read cycle is to obtain a signal amplitude sufficient for reading. That is, a large number of memory cells are arranged in the bit line direction, and M
When the bit line capacitance as viewed from the OS transistor is large, the driving capability of the MOS transistor constituting the memory cell is small, and the output signal from such a memory cell MC makes the level of the complementary bit line sufficient for reading the memory cell data. It takes time to drive to a certain level. Therefore, by setting the word line selection time in the read cycle to be relatively long, a signal amplitude sufficient for reading can be obtained (see waveform 301). During this word line selection time, the precharge control signal PC * is negated to the high level, and no precharge is performed (precharge off time).

In the read cycle, during the period from when the word line WL is deselected to the next drive to the selected level, the precharge control signal PC * is asserted to the low level, and the bit line BL is asserted. , BL * are precharged. Since the word line selection time in the read cycle is set to a relatively long time as described above, the non-selection time of the word line is inevitably shortened. Would. In other words, the precharge time from the word line selection in the read cycle to the next drive of the word line to the selected level is shortened. However, the precharging of the complementary bit lines is still performed sufficiently. In other words, the potential difference between the complementary bit lines in the read cycle is small due to the data from the memory cell MC, so that sufficient recovery can be performed even if the time required for precharge is short.

Next, the reason why the selection time of the word line WL in the write cycle is short is that the writing by the write amplifier is completed in a relatively short time. That is, as the element applied to the write amplifier, an element having a wider channel width and a higher driving capability than the element constituting the memory cell MC is applied. Therefore, in the write cycle, the complementary bit lines BL and BL * are not used. By quickly pulling out one of the charges, the level can be set to the low potential side power supply Vss level.
Therefore, the word line drive time in the write cycle may be relatively short. Since the word line drive time in the write cycle is set relatively short, the precharge off time (precharge off period) in the write cycle may be short. By shortening the precharge off time in this way, the precharge start timing after data writing in the write cycle is advanced,
As a result, the word line non-selection time and the precharge time after data writing in the write cycle can be lengthened. In other words, the data write is completed in a short period in the first half of the write cycle, and the precharge period for bit line recovery after the data write is extended. In the write cycle, the complementary bit line B
When one of L and BL * is pulled down to the low-potential-side power supply Vss level, the level difference between the complementary bit lines increases. However, as described above, the data write is completed in the short period of the first half of the write cycle. Since the precharge period for recovering the bit line after the data write is lengthened, the complementary bit line can be sufficiently precharged to the level of the high potential side power supply Vdd in the write cycle (see waveform 302).

FIG. 4 shows a configuration example of the read / write pulse width control circuit 72.

An inverter 721 for inverting an external read / write signal R / W, an inverter 722 for inverting its output logic, and an inverter 723 for inverting its output logic are provided. In order to synchronize the read clock signal RCK and the write clock signal WCK generated by the read / write pulse width control circuit 72 with the internal clock signal ICK, an n-channel type M which is turned on / off by the internal clock signal ICK
In order to prevent the OS transistors Q11, Q13 and the MOS transistors Q11, Q13 from turning into a floating level during the off-period, the signal lines are pulled to the high potential side power supply Vdd level based on the internal clock signal ICK. There are provided p-channel type MOS transistors Q12 and Q14 for raising.

The output signal of the inverter 722 is transmitted to the subsequent inverter 724 via the n-channel MOS transistor Q11. Inverters 725, 726, and 727 are connected in series to delay the output signal of inverter 724. The output signal of inverter 727 is transmitted to one input terminal of two-input AND gate 728. Also,
The output signal of the inverter 724 is AND gate 728
, And the output signal of the inverter 727 and AND logic are obtained. Then, the write clock signal WCK is obtained from the output terminal of the AND gate 728.

The output signal of the inverter 723 is transmitted to the subsequent inverter 729 via the n-channel MOS transistor Q13. Inverters 730, 731, 732, 7 for delaying the output signal of inverter 729
33 are connected in series. The output signal of inverter 729 is transmitted to one input terminal of two-input OR gate 734. The output signal of the inverter 729 is transmitted to the other input terminal of the OR gate 734,
Nine output signals and OR logic are obtained.
Then, a read clock signal RCK is obtained from the output terminal of the OR gate 734.

FIG. 5 shows the operation timing of the main part in the read / write width pulse control circuit 72 shown in FIG.

As shown in FIG. 5, a period in which the read / write signal R / W is at a high level is a read cycle, and a period in which the read / write signal R / W is at a low level is a write cycle. By obtaining the AND logic of the output of the inverter 724 and the output of the inverter 727, the write clock signal WCK is obtained from the AND gate 728, and the OR logic of the output of the inverter 729 and the output of the inverter 733 is obtained. A read clock signal WCK having a wider pulse width than the write clock signal is formed.

According to the above embodiment, the following effects can be obtained.

(1) Since the word line drive time in the write cycle is set relatively short, the precharge off time in the write cycle may be short. By shortening the precharge off time in this manner, the precharge start timing after data write in the write cycle is advanced, and as a result, the word line non-selection time and precharge time after data write in the write cycle are reduced. Can be longer. That is, data write is completed in a short period in the first half of the write cycle, and a precharge period for bit line recovery after the data write is lengthened. In the write cycle, when one of the complementary bit lines BL and BL * is pulled out to the low-potential-side power supply Vss level, the level difference between the complementary bit lines increases. However, as described above, in the short period in the first half of the write cycle, Since the data write is completed and the precharge period for recovering the bit line after the data write is extended, the complementary bit lines are sufficiently precharged to the level of the high potential side power supply Vdd in the write cycle. it can. By optimizing the word line selection and the precharge operation in this way, it is possible to reduce the cycle time when the same precharge circuit is used in the read cycle and the write cycle.

(2) Based on a read / write signal externally given as a signal for instructing read and write,
A read / write pulse width control circuit 72 for forming a read clock signal and a write clock signal having a pulse width narrower than the read clock signal; a read clock signal and a write clock signal output from the read / write pulse width control circuit 72 Gate 74 for forming a control signal for the word line selection operation and the precharge operation based on
By providing the AND gate 73, the controller 7 can be easily configured.

(3) A NAND gate 76 for forming a control signal for selecting a specific bit line from the plurality of bit lines in synchronization with the read clock signal, and an operation of the write amplifier in synchronization with the write clock signal By providing the AND gate 75 that forms a control signal for controlling, the column selection system and the write amplifier operation can be optimized.

(4) Since the cycle time can be reduced as described above, when a computer system is configured to include such a built-in RAM 52 and a CPU 53 that can access the same, The processing can be speeded up.

Although the invention made by the present inventor has been specifically described above, the present invention is not limited to this, and it goes without saying that various modifications can be made without departing from the gist of the invention.

For example, the RAM 52 in the above-described example is built in the microcomputer, but the SRAM may be configured as a single unit as a memory LSI, and the present invention can be provided in such a case.

In the above description, the case where the invention made by the present inventor is mainly applied to the built-in RAM which is the application field as the background has been described. However, the present invention is not limited to this, and various data It can be widely applied to processing equipment.

The present invention can be provided on condition that a precharge circuit for precharging a bit line is included at least during a non-selection period of a word line.

[0062]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, while the word line selection time can be shorter in the write cycle than in the read cycle, the precharge time of the bit line needs to be longer in the write cycle than in the read cycle. ,
The word line selection time and the precharge off time in the write cycle are controlled to be shorter than the word line selection time and the precharge off time in the read cycle, respectively. By optimizing the charge, the cycle time of the volatile semiconductor memory device can be reduced.

A read / write pulse width control circuit for forming a read clock signal and a write clock signal having a smaller pulse width than the read clock signal based on an externally applied read / write signal as a signal for instructing reading and writing. And a control logic for forming control signals for the word line selection operation and the precharge operation based on the read clock signal and the write clock signal output from the read / write pulse width control circuit, thereby facilitating the control means. Can be configured.

A second control logic for forming a control signal for selecting a specific bit line from the plurality of bit lines in synchronization with the read clock signal, and a write amplifier for a write amplifier in synchronization with the write clock signal By providing the third control logic for forming a control signal for controlling the operation, the operation of the column selection system and the write amplifier can be optimized.

Further, since the cycle time can be shortened as described above, a data processing device including such a volatile semiconductor memory device and a central processing unit capable of accessing the same can be used. Can speed up the processing in the data processing device.

[Brief description of the drawings]

FIG. 1 is a block diagram of an overall configuration example of a built-in RAM included in a microcomputer which is an example of a data processing device according to the present invention.

FIG. 2 is a circuit diagram showing a configuration example of a main part of a controller included in the built-in RAM and blocks related thereto.

FIG. 3 is an operation timing chart of a main part in the built-in RAM.

FIG. 4 is a circuit diagram illustrating a configuration example of a read / write pulse width control circuit included in FIG. 2;

FIG. 5 is an operation timing chart of a main part in the read / write pulse width control circuit shown in FIG. 4;

FIG. 6 is a block diagram illustrating an overall configuration example of a computer system including the microcomputer.

FIG. 7 is a block diagram illustrating a configuration example of the microcomputer.

[Explanation of symbols]

 7 Controller 8 Write amplifier 9 Input circuit 10 Precharge circuit 13 Row address buffer 14 Row decoder 15 Memory cell array 16 Column address buffer 17 Column decoder 18 Column selection circuit 19 Sense amplifier 20 Output circuit 52 Built-in RAM 71 Clock generator 72 Read / write pulse control Circuit 73, 75 AND gate 74 OR gate 76 NAND gate 77 Inverter

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hitoshi Endo 5-22-1, Josuihonmachi, Kodaira-shi, Tokyo Inside Hitachi Super LSI Systems Co., Ltd. (72) Inventor Yukitoshi Tamura Tokyo 5-22-1, Josuihoncho, Kodaira-shi, Tokyo Hitachi Ultra-SII Systems, Inc. (72) Inventor Shinya Yamada 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Hitachi, Ltd. (72) Inventor Kan Shimono 5-22-1, Josuihonmachi, Kodaira-shi, Tokyo Inside Hitachi Super LSI Systems Inc. (72) Inventor Sato F-term (reference) 5-1615 HH01 HH03 JJ24 KA23 KA33 KA38 KB82 KB91 KB92 NN03 PP06

Claims (4)

[Claims] 1. A word line, a bit line arranged to intersect the word line, a volatile memory cell coupled to the word line and the bit line, and the bit line during a non-selection period of the word line. And a precharge circuit for precharging a line, wherein a read operation and a write operation are performed in synchronization with an externally applied clock signal. Control means for controlling the word line selection operation and the bit line precharge operation such that the off time is shorter than the word line selection time and the precharge off time in the read cycle, respectively. Volatile semiconductor storage device. 2. The control means forms a read clock signal and a write clock signal having a pulse width smaller than the read clock signal based on a read / write signal externally given as a signal for instructing read and write. A read / write pulse width control circuit, and control logic for forming control signals for a word line selection operation and a precharge operation based on the read clock signal and the write clock signal output from the read / write pulse width control circuit. 2. The volatile semiconductor memory device according to claim 1, comprising: 3. The control means forms a read clock signal and a write clock signal having a pulse width narrower than the read clock signal based on a read / write signal externally provided as a signal for instructing read and write. A read / write pulse width control circuit, a first control logic for forming a control signal for a word line selection operation and a precharge operation based on a read clock signal and a write clock signal output from the read / write pulse width control circuit, A second control logic for forming a control signal for selecting a specific bit line from the plurality of bit lines in synchronization with the read clock signal; and controlling an operation of a write amplifier in synchronization with the write clock signal. 3. The volatile semiconductor memory device according to claim 1, further comprising: a third control logic for forming the control signal. 4. A data processing device comprising: the volatile semiconductor memory device according to claim 1; and a central processing unit capable of accessing the volatile semiconductor memory device.