JPH0384796A - Synchronous storage device - Google Patents

Abstract

PURPOSE:To shorten the time needed to the initialization by providing a connecting means where each one side of bit line of a pair of bits is connected to a second electric potential source in response to an initialization instructing signal. CONSTITUTION:One side of bit lines 1b, 1d of a pair of bit lines, the connecting means 9a, 9b where are activated in response to the initialization instructing signal, and connect the corresponding bit lines 1b, 1d to the second electric potential source (grounded electric potential)11 are provided. The connecting circuits 9a, 9b are constituted with NMOS transistors TR1, TR2 receiving the initialization instructing signal 8 to respective gates. In such a manner, the initialization of setting or resetting of all memory cells to be connected so a piece of word line in attained in a cycle (or an instruction), and with the cycle (or the instruction) for all word lines number the initialization of setting or resetting of all the memory cells is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly relates to an improvement in a synchronous memory device.

C. Prior Art] In highly integrated gate arrays, microprocessors, etc., high-speed static random access memory (SRAM) is often used, for example, as a register for temporarily storing calculation results. be.

Static random access to semiconductor integrated circuits
When built-in memory, this static type random
Access memory is often synchronous. This is mainly due to the following reasons. ■If you use the system clock to synchronize with, for example, a CPU (central processing unit), this static type random access
Improved memory usage. ■ Static random access using an asynchronous method ◆ When operating a memory, it is necessary to provide a margin for operation timing to prevent malfunctions such as multiple selection of memory cells.

The main cause of this malfunction in multiple selection of memory cells is skew in the timing of input signals such as addresses. When such an operation timing margin is provided, the timing design of the system becomes complicated and the high-speed operation of the integrated circuit device is impaired. ■In the case of synchronous method,
It becomes possible to reduce the power consumption of static random access memory. In the case of an asynchronous static random access memory, a through current continues to flow through the selected memory cell.

In this case, if a latch synchronized with an external clock is provided in the output circuit, for example, it is possible to shorten the period during which a through current flows through the memory cell.

FIG. 9 shows an overall schematic configuration of a conventional synchronous storage device. Referring to FIG. 9, a conventional synchronous memory device includes a memory cell array 20c in which memory cells are arranged in a matrix of rows and columns.

The memory cell array 20c has a word for selecting one row of memory cells! 112 and a bit line 1 for selecting one column of memory cells are provided.

Bit line 1 includes bit lines 1a, lb, lc and 1d. Bit lines 1a and 1b form a pair, and bit line 1c and bit line 1d form a pair.

An X decoder 22 and a Y decoder 23 are provided to select rows and columns of memory cell array 20c, respectively. The X decoder 22 receives an external address signal 21a (
For example, the word line 2 is decoded (given from an address buffer) and a signal for activating the corresponding word line 2 is generated. Y
The decoder 23 decodes the external address signal 21b and derives Y select signals 24g and 24b. The external address signal 21 is composed of a most significant address signal 21b and a lower address signal 21a.

A Y select gate 2 is used to select a column of the memory cell array 20c in response to the Y select signals 24a and 24b.
5 is provided. The Y select gate 25 is a Y select NMOS transistor (N channel insulated gate field effect transistor) 25 a # 25 b t 2
．． 5c and 25d. Bit 1lla is NMO
8) Connected to common data line 26a via transistor 25a. Bit line 1b is NMO8) transistor 25
It is connected to the common data line 26b via the line 26b. The bit line IC is connected to a common data line 26a via an NMOS transistor 25c. Bit line 1d is connected to common data line 26b via NMOS transistor 25d. NMOS) transistor 25a.

25b is turned on in response to the Y select signal 24a. NMOS transistors 25c and 25d are turned on in response to Y select signal 24b.

A sense amplifier/write driver 27 is provided for writing/reading data. When the write enable signal 29 becomes "°H", the write driver is activated and the output data line (this also serves as a signal line for transmitting input data) 28
The data given above is transmitted onto the common data line pair 26 (common data lines 26a, 26b). When the write enable signal 29 is low, the data transmitted onto the common data line pair 26 is amplified and transmitted onto the output data line 28 via the sense amplifier.

In the above configuration, 2 bits of input/output data
The configuration is such that two bit line pairs are provided. Therefore, when the number of word lines 2 is 21-1, the memory cell array 20c stores 2" words.

A precharge signal 12 is transmitted to memory cell array 20c to precharge each bit line 1 of memory cell array 20C.

This precharge signal 12 is generated in response to an external clock signal, a chip select signal, etc., and in response to this precharge signal 12, an external address is taken in, decoded, input/output data is latched, etc.

FIG. 10 shows the configuration of a main part of the memory cell array 20C shown in FIG. 9. Referring to FIG. 10, memory cells 3a, 3
b, 3c, and 3d are arranged in a matrix. Memory cells 3a and 3c are connected to word line 2a. Word line 2a
When selected, data in memory cell 3a is transmitted onto bit lines 1a and lb, and data in memory cell 3c is transmitted onto bit lines 1c and 1d.

Memory cells 3b and 3d are connected to word line 2b. When word line 2b is selected, data held in memory cell 3b is transmitted to bit lines 1a and 1b, and data held in memory cell 3d is transmitted onto bit lines 1c and ld.

Bits 1lla and lb form a pair, and mutually complementary signal potentials are transmitted. Similarly, bit lines 1c and ld form a pair, and signal potentials complementary to each other are transmitted.

NMOS transistors 4a, 4b, 4c are turned on in response to a precharge signal 12 in order to precharge bit lines 1a, lb, lc, and 1d to a predetermined potential (operating power supply potential in the figure) 5.

4d are provided respectively.

An example of the above-mentioned synchronous storage device is, for example, Japanese Patent Application Laid-open No. 6
1-133094. In this prior art document, the precharge signal 12 is generated by delaying the chip select signal by a predetermined time.

In the above-mentioned synchronous memory device, a precharge signal defines a memory cycle, and the fetching of an address into the device and the input/output of data are performed in synchronization with this precharge signal.

When such a synchronous memory device is built into a semiconductor integrated circuit, the memory cell data of this memory device is set or reset when power is turned on to the semiconductor integrated circuit device, that is, at system startup or system reset. It is necessary to initialize it. Here, the set operation indicates an operation of writing "1" to all memory cells of the storage device, and the reset operation indicates an operation of writing "0'" to all memory cells.

During such an initialization operation, a normal write operation is performed on all data (2" words) in the storage device. Hereinafter, with reference to the operation waveform diagram shown in FIG. The initialization operation will be explained.However, in the following explanation, the set operation will be explained.

The address signal 21 is counted up sequentially starting from address 0. At the start of the initialization operation, the highest address signal 21b becomes 'L'. In response, first, the Y select signal 24a becomes an active state of 'H', while the Y select signal 24b becomes 'Ll'. The state becomes inactive.As a result, the NMOS transistors 25a and 25b for Y selection are turned on, while the NMOS transistors 25c and 25d for Y selection are turned off.As a result, the common data lines 26&, 26b are connected to the bit line 1a and lb. In this state, the address signal 21
a is sequentially counted up in synchronization with the precharge signal 12, and word line 2 (2
a, 2b) are selected sequentially.

On the other hand, the write enable signal 29 indicates data writing.
H#, and the write driver of sense amplifier/write driver 27 is activated. Therefore, the data "1" transmitted to the output data line 28 is transmitted to the common data line 26a.
, 26bSY selection NMO8) transistor 25a,
The signal is transmitted to the bit lines 1a and lb via 25b. In this way, data "1" is written to all word lines (2''-' words).

As described above, data "1" is written to all memory cells connected to bit lines 1a and lb, that is, 1/2 memory cells of the total number of words (2"-"1 word memory cells). When the operation is completed, the address signal 21a
This means that the count-up operation from O is completed, and then the address signal 21b becomes "H".

As a result, the Y select signal 24b from the Y decoder 23
is in the active state "H", while the Y select signal 24a is in the inactive state al L IT.

Therefore, bit lines 1c and ld are connected to common data lines 26a and 26b via Y selection NMOS transistors 25c and 25d. As a result, this bit line 1c.

1d (memory cell 3 in Figure 10)
Writing of data "1" to the memory cells 2c and 3d) is performed by sequentially selecting and activating the word lines 2 in the same manner as the above-described operation.

The above operation has been explained for one bit input/output connected to the common data lines 26a and 26b, but the same operation can be performed for other input/output bits (common data line 26).
The memory cells are connected to the same word line and write operations are performed at the same time.

In addition, in the above description, the Y select signals 24a, 2
4b and write enable signal 29 are not given new states every cycle specified by the precharge signal during the initialization operation, but their signal levels are continuously fixed. This speeds up the write operation to the memory cell during the initialization operation.

Further, in the above description, the set operation of the synchronous storage device has been described, but the same operation is performed in the reset operation as well, with the data applied to the output data line 28 only being "0°."

[Problems to be Solved by the Invention] Generally, when a system is configured using a semiconductor integrated circuit with a built-in synchronous storage device, immediately after the system is started, such as immediately after power is turned on or immediately after a system reset, It is necessary to initialize (set or reset) the synchronous storage device. However, since the conventional synchronous storage device is configured as described above, when initializing the synchronous storage device, it is necessary to perform a write operation on all words. A write operation for one word requires one command (address count up or count down and data write instruction), that is, one cycle (one cycle of the precharge signal shown in Figure 11). Writing requires a number of instructions, or a number of cycles, corresponding to the number of words in the synchronous storage device. Therefore, as the number of words in a synchronous storage device increases, a problem arises in that the time required for this initialization increases.

It is therefore an object of the present invention to provide an improved synchronous storage device which eliminates the drawbacks of the above-mentioned conventional synchronous storage devices.

Another object of the present invention is to provide a synchronous storage device that can be initialized at high speed.

[Means for Solving the Problems] The present invention provides initialization means for setting or resetting data for all bit lines, and at the time of initialization, initial data for setting or resetting memory cells is set or reset for all bit lines. The bit line is fixed by this initialization means, and all memory cells connected to one word line are initialized at one time.
This is done in cycles (or instructions).

That is, the first synchronous memory device according to the present invention includes means for coupling one bit line of each bit line pair to a second potential source in response to an initialization instruction signal, and a means for coupling one bit line of each bit line pair to a second potential source in response to an initialization instruction signal; means for selectively activating a precharge element provided on one of the bit lines in response to an activation instruction signal; and means for transmitting information to the element. The selective activation means includes means for inactivating the precharge element provided on the one bit line during initialization when the initialization instruction signal is in the active state.

A second synchronous storage device according to the present invention switches one bit line of each bit line pair to a second bit line in response to an initialization instruction signal.
a first means for selectively activating a precharge element provided on one of the bit lines of each bit line pair in response to the initialization instruction signal and the precharge signal; activating means; and second activating means for selectively activating a precharge element provided on the other bit line of each bit line pair in response to the initialization instruction signal and the precharge signal. Be prepared.

The first activation means includes means for inactivating the precharge element provided on the one bit line during the initialization operation when the initialization instruction signal is in the active state. Further, the second activation means activates a precharge element provided on the other bit line of the bit line pair in response to the initialization instruction signal during an initialization operation when the initialization instruction signal is in an active state. The bit line includes means for activating a precharge element provided on the other bit line in response to a precharge signal when the activation instruction signal is in an inactive state.

[Operation] In the above configuration, at the time of initialization, the activation means or the first and second activation means are activated, and all bit lines are supplied with initialization data (signal potential) for setting or resetting memory cells. Since it is fixed, it is possible to initialize the set or reset of all memory cells connected to one word line in one cycle (or instruction).

Therefore, it is possible to initialize the set or reset of all memory cells in cycles (or instructions) for the total number of hood lines.

[Embodiment of the Invention] FIG. 2 schematically shows the overall configuration of a synchronous storage device that is an embodiment of the invention. Referring to FIG. 2, the synchronous storage device according to the present invention performs initialization to fix all bit lines to initialization data for setting or resetting memory cells included in memory cell array 20a. an instruction signal transmission line 8; a control circuit 7 for inhibiting a precharge operation on one bit line of the bit line pair during initialization in response to the initialization instruction signal 8 and the precharge signal 12; The precharge signal transmission line 12 is used to precharge the bit line of the bit line even at the time of initial disconnection. In the following description, a signal transmission line and a signal transmitted onto the signal transmission line will be described using the same reference numerals. The other configurations are similar to the conventional synchronous storage device shown in FIG. 9, and parts corresponding to those of the device shown in FIG. 9 are given the same reference numerals.

FIG. 1 shows the configuration of the main parts when setting a synchronous memory device, that is, writing data "11" to all memory cells during initialization operation. Referring to FIG. Coupling means 9a, 9b are provided for the bit lines 1b, ld, which are activated in response to an initialization instruction signal and couple the corresponding bit lines 1b, 1d to a second potential source (ground potential in the figure) 11. .

The coupling circuits 9a and 9b are each constituted by NMOS transistors Tr1 and Tr2 which receive the initialization instruction signal 8 at their gates.

The control circuit 7 includes an AND gate 80 which receives a precharge signal 12 at its true input and receives an initialization instruction signal 8 at its false input. An output signal 10 of the control circuit 7 is supplied to a precharge transistor 4b provided on one of the bit lines 1b and 1d.

4d gate. A precharge signal 12 is transmitted to the gates of precharge transistors 4a and 4c provided on the other bit line 1a and 1c of each bit line pair. Next, the initialization operation of the synchronous memory device according to the present invention will be described with reference to FIG. 3, which is an operation waveform diagram, taking as an example a case where all memory cells are set.

First, during the initialization operation, the initialization instruction signal (third control signal) 8 is raised. In response, coupling circuit 9a
, 9b are both turned on, and the potentials of the bit lines 1b and ld are set to the ground potential (second power supply potential). At this time, since the precharge signal 12 is repeatedly applied, the precharge transistors 4a and 4c perform a precharge operation on the bit lines 1a and lc, respectively, at a predetermined cycle. Since the initialization instruction signal 8 is "Ho", the second control signal 10 of "L" is generated from the control circuit 7 and is applied to the gates of the precharge transistors 4b and 4d. As a result, during the initialization operation, the bit lines 1b and 4d are turned off.
ld is fixed to ground potential, while bit lines 1a, lc
The precharge is repeated at a predetermined period. However, at this time, bit lines 1a and lc are precharged to power supply potential 5, so their potentials maintain the "H" level.

Also, during initialization, the write enable signal 29 is “
It is set to Lo, data reading is instructed, and the sense amplifier is activated. The purpose of this is, for example, to prevent contention between data from the write driver and the fixed potential of the bit line when the write driver is activated. Then, as in the conventional case, the address signal is sequentially counted up in synchronization with the precharge signal 12, and word lines 2 (2a, 2b) are sequentially selected and activated. The potential level of the bit lines 1a and lc is such that when the precharge signal 12 is inactive, the bit line is
Since it is not coupled to the potential source 5 of
becomes. That is, data of '1' is held in each bit line pair.

Therefore, data "1" is written in all memory cells connected to the selected word line. That is, when word line 2a (see FIG. 1) is selected, memory cells 3a, 3
When the word line 2b is selected, the data "1" is written to the memory cells 3b and 3d.

During the data write operation to the memory cell, the "H" level of the bit line is a dynamic "H" level as described above, while the "L-level" of the bit line is the dynamic "H" level as described above.
, 9b to the ground potential, and becomes static 'L'.

If the memory cells 3a, 3b, 3c and 3d are static random access memories, they have a flip-flop configuration, so that data a1'' is reliably written into the memory cells.

As mentioned above, data '11' is held in all bit line pairs while the initialization instruction signal 8 is active, so data can be written simply by performing a read operation to the memory cell. Furthermore, data can be written to all memory cells connected to one word line at the same time. Furthermore, by configuring the memory cell to be initialized only by reading data, rather than activating and operating the write driver to write external data during initialization, it is possible to simply This is because driving the amplifier is faster, thereby increasing the speed of initializing the storage device.

In the above configuration, when the number of word lines is 21-1,
Even if the total number of words is 2a, data in all memory cells can be set in 2°-1 cycles.

When the initialization operation is completed, the initialization instruction signal 8 falls to the "L" level. As a result, the coupling circuits 9a and 9b become inactive, and the bit line 1b becomes inactive.

1d are each disconnected from the second potential source 11. On the other hand, the control circuit 7 functions as a buffer and transmits the precharge signal 12 onto the signal line 10. As a result, precharging transistors 4a, 4b, 4
Bit lines c and 4d each perform a precharge operation on the corresponding bit line in response to the precharge signal 12.

In the above-described embodiment, the bit line 1a and the IC are not fixed at the static gHe level during the initialization operation, but are connected to the dynamic "H" level every half cycle to the potential source 5. Become. Instead, it is also possible to set the bit lines 1a and lc to a static "H" level during the initialization operation. Fig. 4 shows a synchronous storage device according to another embodiment of the present invention. The overall configuration is shown below.

Referring to FIG. 4, a synchronous storage device according to another embodiment of the present invention has a second bit line for fixing the other bit line of the bit line pair to a static "H° level" at the time of initialization. It further includes a control circuit 13.The control circuit 13 includes:
Upon receiving the precharge signal 12 and the initialization instruction signal 8, the fourth control signal 14 is transmitted to the precharge transistor provided on the other bit line of the bit line pair.

FIG. 5 specifically shows the configuration of the main parts of the synchronous storage device shown in FIG. 4. Referring to FIG. 5, second control circuit 13 is comprised of an OR gate receiving precharge signal 12 and initialization instruction signal 8. Referring to FIG. The rest of the configuration is similar to that shown in FIG. 1, and the configuration is shown in which all memory cells are set at the time of initialization. According to this configuration, when the initialization instruction signal becomes active "H", the fourth control signal 14 always becomes mHe, the precharging transistors 4a and 4c are turned on, and the bit lines 1a and l
c is connected to potential source 5 and bit line 1a.

1C is fixed at "H" level. On the other hand, when the initialization instruction signal 8 is "Lo", the control circuit 13 simply functions as a buffer, and the precharge signal 12 is transmitted as the control signal 14 to the gates of the precharge transistors 4a and 4c.

Next, the operation will be briefly explained with reference to FIG. 6, which is an operation waveform diagram. During the initialization operation, the initialization instruction signal (third control signal) 8 is “H”.

stand up. Next, the address signal 21 is taken in and decoded in synchronization with the precharge signal 12, and the Y select signal 24a output from the Y decoder 23 falls to "H" and the Y select signal 24b falls to "L". The decode signals from 22 are sequentially counted up in synchronization with the precharge signal 12, and the word lines 2 are sequentially activated.At this time, the fourth control signal 14 is
Due to the function 3, there is a “■” relationship with the precharge signal.
It is. Therefore, during the initialization operation, precharging transistors 4a and 4c are turned on, and bit lines 1a and lc are fixed at the "H" level. Similarly, from the function of the control circuit 7, the precharging transistor 4b,
4d is turned off, and coupling circuits 9a and 9b are activated in response to initialization instruction signal 8. As a result, bit lines 1b and ld are fixed at the "L" level, and each bit line pair is fixed at data '1#. Therefore, word line 2a
, 2b, .
° will be written. At this time, the bit lines 1a,
Since both lc are fixed at a static "H° level," data "1" can be written more reliably.

When all word lines are sequentially activated, data writing to all memory cells is completed.

When the initialization operation is completed, the initialization instruction signal 8 falls to "L", the control signal 10 from the control circuit 7 becomes a signal similar to the precharge signal 12, and the second control circuit 1
The three-output control signal 14 also becomes a signal similar to the precharge signal 12, and the bit line precharge operation is performed.

In the above-described embodiment, reading of memory cell data is performed at the time of initialization, and a high speed ratio of the initialization operation is achieved. In this case, since writing of memory cell data is performed regardless of the state of the Y select signal, the Y select signal 24a.

24b are both "L" at the same time, and even if the sense amplifier/write driver 27 and the memory cell array 20a (20b) are separated, the same effect as in the above embodiment can be obtained. In this case, the initialization instruction signal 8 may be applied to the Y decoder 23, and when the initialization instruction signal 8 is in the active state, the Y select signals 24a and 24b may both be set to 'L'.

Further, the bit line precharge potential does not need to be the operating power supply potential, and may be, for example, 1/2 Vcc.

Furthermore, in the above embodiment, a synchronous storage device in which two bit line pairs correspond to one output (or input) has been described, but four bit line pairs correspond to one output (or input). Similarly, the set operation can be performed for a corresponding storage device or a synchronous storage device in which eight bit line pairs correspond to one output (or input), and it is possible to perform the set operation in the same way for each storage device. It is possible to initialize the storage device in a data read operation period (cycle) with the number of words/4 and the total number of words being 78.

That is, in a memory device in which N bit line pairs correspond to one output (or human power), initialization can be performed in a data read operation period (cycle) equal to the total number of words/N. Although the coupling circuits 9 (9a, 9b) are provided for each bit line, they may be provided for all bit lines if sufficient discharge capacity is provided.

Furthermore, in the above-mentioned operation, the operation of setting all memory cells at the time of initialization has been explained, but also in the reset operation of the memory device, the signal potential level of the bit line pair is reversed from that in the above two embodiments. ie, bit line 1a.

If the configuration provided for 1C and bit lines 1b and ld (see Figures 1 and 5) is reversed, it is possible to perform a reset operation in which data of 0'' is written to all memory cells at the time of initialization. Become.

Next, a method of generating the initialization instruction signal 8 will be explained. FIG. 7 shows a configuration in which an initialization instruction signal is applied from the outside.

In FIG. 7, a synchronous memory device 30 is built into a semiconductor integrated circuit formed on a semiconductor chip 50. In FIG. The initialization instruction signal 8 is applied via the input pad section 31 and an external signal line 8a provided outside the semiconductor integrated circuit. The external initialization instruction signal 8a is used, for example, when starting up the system at power-on or resetting the system.
It is generated for a predetermined period from a pulse generator connected to U (central processing unit), a reset switch, or a power-on detector. The period during which this external initialization instruction signal 8a is generated is the period required to set or reset the synchronous storage device 30, and in the case of the configuration shown in FIGS. 2 and 4, all the hood lines/ This period corresponds to two cycles (one cycle is one precharge cycle).

FIG. 8 shows an example of a configuration in which an initialization instruction signal is generated internally. In FIG. 8, the synchronous memory device 30 is built into a semiconductor integrated circuit formed on a semiconductor chip 60. In FIG. This semiconductor integrated circuit has an instruction register 32 that stores generation control of the initialization instruction signal 8 in the form of a program.
and an instruction decoder 33 that decodes the instruction from the instruction register 32 and generates the initialization instruction signal 8. The instruction register 32 also stores various operation control programs for this semiconductor integrated circuit, so the instruction decoder 33 outputs control signals 3 for controlling various operations.
4 is also output.

The initialization program stored in the instruction register 32 is activated when an initial operation is required, keeps the initialization instruction signal 8 active for a predetermined period, and
A program can be considered that reads data from all word lines/2 of 0 (in the case of the configurations shown in FIGS. 2 and 4) (that is, sequentially activates all word lines).

Note that the precharge signal 12 and the address signal 21 (this is the lower address signal 21a and the highest address signal 2
1b is also included. ) and the combined light of the output data line 28 is:
It is appropriately determined in various ways depending on the configuration of the semiconductor integrated circuit incorporating the storage device 30.

For example, if the semiconductor integrated circuit includes a synchronization clock generator, the precharge signal 12 may be generated within the chip 50 (or 60) in response to clock pulses from the clock generator. Further, the precharge signal 12 may be generated in response to a chip select signal that activates the semiconductor memory device. Furthermore, if the semiconductor integrated circuit is operated by an external clock signal (for example, a system clock), the precharge signal 12 may be applied from the outside in response to this external clock signal.

Further, the address signal 21 may be similarly applied from the outside, or may be generated internally from a built-in address counter or the like.

Furthermore, the output data line 28 is also connected to the chip 50 (or 60
) may be externally connected to an appropriate external circuit via a pad, or may be coupled to a data processing circuit, an arithmetic circuit, etc. inside the chip 50 (or 60). All of these are determined by the configuration of the semiconductor integrated circuit incorporating this synchronous storage device 30.

[Effects of the Invention] As described above, according to the present invention, in order to set or reset data for all bit lines of a synchronous storage device, initialization means that is activated at the time of initialization is provided. At the time of initialization, this initialization means is activated and all bit lines are fixed to initialization data that sets or resets all memory cells, so all memory cells connected to one word line can be set or reset. can be executed in one cycle (or instruction).

Normally, in the configuration of a synchronous storage device, the number of memory cells connected to a word line is N (N-2, 3, 4,...) times the bit line (the number of bit lines of human output data). ,
Reading and writing are performed to memory cells selected by the Y decoder. Therefore, by simultaneously performing the set or reset initialization of all memory cells connected to one word line, all data can be set or reset initialized in cycles corresponding to the total number of word lines. can reduce the number of cycles required to initialize a synchronous storage device by 1/2.
It becomes possible to reduce it to N (N-2, 3, 4, . . . ).

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a main part of a synchronous storage device that is an embodiment of the present invention. FIG. 2 is a diagram showing the overall schematic configuration of the synchronous storage device shown in FIG. 1. FIG. 3 is a diagram showing the operation timing during the initialization operation of the synchronous storage device shown in FIGS. 1 and 2. FIG. 4 is a diagram showing the overall general configuration of a synchronous storage device according to another embodiment of the present invention. FIG. 5 is a diagram showing the configuration of essential parts of the synchronous storage device shown in FIG. 4. FIG. 6 is a timing waveform diagram showing the operation of the synchronous storage device shown in FIGS. 4 and 5 during the initialization operation. FIG. 7 is a diagram showing an example of the configuration of a semiconductor integrated circuit incorporating a synchronous memory device according to the present invention. FIG. 8 is a diagram illustrating another configuration of a semiconductor integrated circuit incorporating a synchronous memory device according to the present invention. FIG. 9 is a diagram showing the overall general configuration of a conventional synchronous storage device. FIG. 10 is a diagram showing the configuration of main parts of the conventional synchronous storage device shown in FIG. 9. FIG. 11 is a timing diagram showing the initialization operation of the synchronous storage device shown in FIGS. 9 and 10. In the figure, 1. la, lb, lc, ld are bit lines,
3a, 3b, 3c, 3d are memory cells, 4a, 4b, 4
c, 4d are NMOS transistors for precharging, 5 is a power supply, 7 is a first control circuit, 8 is an initialization instruction signal, 9
a, 9b are coupling circuits, 10 is a second control signal, 11 is a ground potential, 12 is a precharge signal, 13 is a second control circuit, and 20a. 20b is a memory cell array, 22 is an X decoder, 23 is a Y decoder, 30 is a synchronous storage device, and 50.degree. and 60 are semiconductor chips. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (2)

[Claims] (1) A plurality of memory cells arranged in a matrix, a plurality of bit lines to which one column of the plurality of memory cells is connected, and a corresponding bit line provided to each of the plurality of bit lines. a plurality of precharge elements for precharging to a first potential, the plurality of bit lines are arranged in pairs to form a plurality of bit line pairs, and a synchronous memory device in which mutually complementary signal potentials are transmitted to paired bit lines, wherein one bit line of each bit line pair is connected to a second potential source in response to an initialization instruction signal. means for coupling to, in response to a precharge signal and the initialization instruction signal;
means for selectively activating a precharge element provided on the one bit line; the activation means activates the precharge element provided on the one bit line when the initialization instruction signal is in an active state; A synchronous memory device, comprising means for inactivating the precharge signal and transmitting the precharge signal to a precharge element provided on the other bit line of each of the bit line pairs. (2) a plurality of memory cells arranged in rows and columns, a plurality of bit lines each connected to one column of the plurality of memory cells, and a plurality of bit lines provided corresponding to each of the plurality of bit lines;
and a plurality of precharge elements that precharge corresponding bit lines to a first potential, and the plurality of bit lines are two bit lines arranged in pairs to form a plurality of bit line pairs. , and in which mutually complementary signal potentials are transmitted to the paired bit lines, wherein one bit line of each bit line pair is connected to a second bit line in response to an initialization instruction signal. means for coupling to a potential source, responsive to the initialization instruction signal and the precharge signal;
first means for selectively activating a precharge element provided on the one bit line of each of the bit line pairs;
The first activation means includes means for inactivating the precharge element provided on the one bit line when the initialization instruction signal is active, and the first activation means includes means for inactivating the precharge element provided on the one bit line, and a second activation means for selectively activating a precharge element provided on the other bit line of each of the bit line pairs in response to a charge signal; , when the initialization instruction signal is active, the precharge element of the other bit line is activated in response to the initialization instruction signal, and when the initialization instruction signal is inactive, the precharge signal is activated. A synchronous memory device comprising means for activating the precharge element of the other bit line in response to the precharge element of the other bit line.