JP2000122027A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the deterioration in the quality of display images by the influence of the power-supply voltage fluctuation generated in the distribution operation of clock signals. SOLUTION: The liquid crystal display device has an array substrate 2A including plural pixel electrodes 8, plural scanning lines 5, plural signal lines 3, plural switching elements 7 for impressing the signal voltage on the corresponding signal lines to the corresponding pixel electrodes by control via the respective corresponding scanning lines, a scanning line driving circuit 20 for driving the plural scanning lines 5 and a signal line driving circuit 10 for driving the plural signal lines 3. The scanning line driving circuit 20 includes a clock buffer circuit 29 for amplifying the clock signals supplied from the outside of this array substrate 2A, a scanning output circuit SCV for successively scanning the plural scanning lines in accordance with the clock signals supplied from the clock buffer circuit 29, power source lines 24a and 24b for the clock buffer circuit and power source lines 22a and 22b for the scanning output circuit disposed separately from these power source lines 24a and 24b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit integrated type active matrix liquid crystal display device.

[0002]

2. Description of the Related Art Generally, an active matrix liquid crystal display device has a structure in which a liquid crystal layer is sandwiched between an array substrate formed of a transparent glass plate and a counter substrate. The array substrate includes a plurality of pixel electrodes arranged in a matrix and a plurality of scanning lines arranged along rows of the pixel electrodes.
A plurality of signal lines arranged along the columns of these pixel electrodes,
A plurality of switching elements are arranged near the intersection of the plurality of scanning lines and the plurality of signal lines, and each is controlled via the corresponding scanning line to apply a signal voltage on the corresponding signal line to the corresponding pixel electrode. When the liquid crystal display device is of a driving circuit integrated type, a plurality of scanning lines are driven by a scanning line driving circuit formed on an array substrate, and a plurality of signal lines are driven by a signal line driving circuit formed on the array substrate. You.

In a scanning line driving circuit, a vertical clock buffer circuit amplifies a vertical clock signal supplied from outside the array substrate and supplies the amplified signal to a shift register. The vertical shift register shifts the vertical scanning pulse in response to the vertical clock signal, and sequentially outputs the shifted horizontal scanning pulse from a plurality of output terminals to the scanning line buffer circuit. The scanning line buffer circuit amplifies a scanning pulse obtained from each output terminal of the vertical shift register and drives a corresponding scanning line.

In a signal line driving circuit, a plurality of signal lines are connected to a video signal bus for transmitting a video signal supplied from outside the array substrate via a plurality of switches, and a horizontal clock buffer circuit is connected from outside the array substrate. The supplied horizontal clock signal is amplified and supplied to the horizontal shift register. The horizontal shift register shifts the horizontal scanning pulse in response to the horizontal clock signal, and sequentially outputs the horizontal scanning pulse from a plurality of output terminals to a transmission gate (TG) buffer circuit. The TG buffer circuit drives the corresponding switch by amplifying the scanning pulse obtained from each output terminal of the horizontal shift register. Each switch conducts in response to this scan pulse,
The signal voltage on the video signal bus is supplied to the corresponding signal line.

[0005]

In the above-described active matrix liquid crystal display device, the number of power supplies input to the array substrate is reduced by the power supply wiring in each of the circuit area of the scanning line drive circuit and the circuit area of the signal line drive circuit. Are standardized. Specifically, the power supply wiring for the vertical clock buffer circuit is shared with the power supply wiring for the vertical shift register and the scanning line buffer circuit, and the power supply wiring for the horizontal clock buffer circuit is shared with the power supply wiring for the horizontal shift register and the TG buffer circuit. Is done. On the other hand,
The vertical clock buffer circuit is connected by a first clock wiring to all of a plurality of flip-flops connected in cascade to form a vertical shift register. The horizontal clock buffer circuit is connected to all of a plurality of flip-flops connected in cascade to form a horizontal shift register by a second clock wiring.

Each of the first and second clock lines has a very large parasitic capacitance. Therefore, the power supply voltage of the scanning line driving circuit and the power supply voltage of the signal line driving circuit fluctuate due to the operations of the vertical clock buffer circuit and the horizontal clock buffer circuit that change the voltage levels of the first and second clock wirings according to the clock signal, respectively. Cheap. Since the vertical shift register and the scanning line buffer circuit use the same power supply wiring as the vertical clock buffer circuit adjacent to the vertical clock buffer circuit, the operation is significantly affected by the power supply voltage fluctuation caused by the operation of the vertical clock buffer circuit. The reliability has been hindered. Also, regarding the horizontal shift register and the TG buffer circuit,
Since these use the power supply wiring common to the horizontal clock buffer circuit adjacent to the horizontal clock buffer circuit, they are significantly affected by the power supply voltage fluctuation caused by the operation of the horizontal clock buffer circuit, and hinder the operation reliability. I have.

For example, when the operation of the scanning line buffer circuit is affected by the above-described power supply voltage fluctuation, the switching state of a switching element connected to the scanning line buffer circuit via the scanning line becomes unstable, and the displayed image is displayed. The result is a deterioration in quality.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a liquid crystal display device which can prevent the quality of a displayed image from being degraded by the influence of a power supply voltage fluctuation generated in a clock signal distribution operation. The purpose is to provide.

[0009]

According to the present invention, a plurality of pixel electrodes are arranged in a matrix, a plurality of scanning lines are arranged along rows of these pixel electrodes, and a plurality of scanning lines are arranged along columns of these pixel electrodes. A plurality of signal lines, a plurality of scanning lines, and a plurality of signal lines, which are arranged near intersections of the plurality of signal lines, each of which is controlled via the corresponding scanning line to apply a signal voltage on the corresponding signal line to the corresponding pixel electrode; A switching element, a scanning line driving circuit for driving a plurality of scanning lines, and an array substrate including a signal line driving circuit for driving a plurality of signal lines, and a counter substrate including a counter electrode facing the plurality of pixel electrodes, A liquid crystal layer sandwiched between the array substrate and the counter substrate, wherein at least one of the scanning line drive circuit and the signal line drive circuit amplifies a clock signal supplied from outside the array substrate. A scan output circuit for sequentially scanning a plurality of scan lines or signal lines in response to a clock signal supplied from the clock circuit, a clock buffer circuit power supply line, and a clock buffer circuit power supply line. A liquid crystal display device including a power supply line for a scan output circuit is provided.

In this liquid crystal display device, the power supply line for the scan output circuit is provided separately from the power supply line for the clock buffer circuit. Accordingly, even if the power supply voltage on the power supply line for the clock buffer circuit fluctuates due to the operation of the clock buffer circuit, this does not significantly affect the power supply voltage on the power supply line for the scan output circuit. Reliability can be improved. When the scanning output circuit controls the switching element via the scanning line, the switching element can operate stably. That is, the switching element is surely turned on for the writing operation of applying the signal voltage on the signal line to the pixel electrode, and for the holding operation of holding the pixel electrode voltage by electrically separating the pixel electrode from the signal line. The switching element can be reliably turned off. Therefore, good image quality without writing unevenness, holding unevenness and the like can be obtained.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A drive circuit integrated type active matrix liquid crystal display device according to a first embodiment of the present invention will be described below with reference to FIGS. FIG. 1 shows the configuration of this active matrix liquid crystal display device.

This liquid crystal display device has a structure in which a liquid crystal layer 1 is sandwiched between an array substrate 2A and a counter substrate 2B formed of a transparent glass plate as in the conventional case. The array substrate 2A includes a plurality of pixel electrodes 8 arranged in a matrix.
And a plurality of scanning lines 5 arranged along the rows of the pixel electrodes 8, a plurality of signal lines 3 arranged along the columns of the pixel electrodes 8, the plurality of scanning lines 5 and the plurality of signal lines 3. Transparent having a plurality of polysilicon thin film transistors (TFTs) 7 arranged as switching elements near the intersection positions and controlled via corresponding scanning lines 5 to apply signal voltages on corresponding signal lines 3 to corresponding pixel electrodes 8 respectively. Glass plate. The array substrate 2A further has a scanning line driving circuit 20 for driving the plurality of scanning lines 5 and a signal line driving circuit 10 for driving the plurality of signal lines 8. Each of the scanning line driving circuit 20 and the signal line driving circuit 10 is constituted by a plurality of polysilicon thin film transistors formed together with the TFT 7 serving as a switching element.

The scanning line driving circuit 20 includes a vertical clock buffer circuit 29 for amplifying a vertical clock signal supplied from outside the array substrate 2A, and a vertical clock buffer circuit 2
9 includes a vertical scan output circuit SCV that sequentially scans a plurality of scan lines 5 in response to a vertical clock signal supplied from 9.
The scan output circuit SCV shifts a vertical scan pulse in response to a vertical clock signal supplied from a vertical clock buffer circuit 29 and sequentially outputs the shift pulse from a plurality of output terminals. The scanning line buffer circuit 23 amplifies the scanning pulse obtained from the end and supplies the amplified scanning pulse to the corresponding scanning line 5. The vertical shift register 21 is composed of a plurality of flip-flops connected in cascade, and their output terminals are output terminals of the vertical shift register 21, respectively. Vertical clock buffer circuit 29
Are connected by a first clock wiring 26 to all of these flip-flops to supply a vertical clock signal.

The signal line driving circuit 10 includes a horizontal clock buffer circuit 19 for amplifying a horizontal clock signal supplied from outside the array substrate 2A, and a horizontal clock buffer circuit 1
9 includes a horizontal scanning output circuit SCH that sequentially scans a plurality of signal lines 8 in response to a horizontal clock signal supplied from 9.
The horizontal scanning output circuit SCH includes a video signal bus 17 for transmitting a video signal supplied from outside the array substrate 2A, and a plurality of transmission gates each connected as an analog switch between the video signal bus 17 and the corresponding signal line 8. (TG) 18, a horizontal shift register 11 that shifts a horizontal scanning pulse in response to a horizontal clock signal supplied from a horizontal clock buffer circuit 19, and sequentially outputs the output from a plurality of output terminals, and from each output terminal of the horizontal shift register 11. It includes a TG buffer circuit 13 that amplifies the obtained scan pulse and drives the corresponding transmission gate 18.
Each transmission gate 18 becomes conductive in response to the scanning pulse, and supplies the signal voltage on the video signal bus 17 to the corresponding signal line 8. The horizontal shift register 11 is composed of a plurality of flip-flops connected in cascade, and their output terminals are output terminals of the horizontal shift register 11, respectively. The horizontal clock buffer circuit 19 applies a second clock to all of these flip-flops to supply a horizontal clock signal.
Are connected by the clock wiring 16. Each transmission gate 18 is a polysilicon thin film transistor (T
FT).

In this liquid crystal display device, the power supply line for the vertical scan output circuit SCV is provided separately from the power supply line for the vertical clock buffer circuit 29, and the horizontal scan output circuit SCH
Power supply wiring is provided separately from the power supply wiring for the horizontal clock buffer circuit 19. That is, each of the TG buffer circuit 13 and the horizontal shift register 11 has the power supply voltage V
Power supply lines 12a and 12b for transmitting DDX1 and VSSX1
And the horizontal clock buffer circuit 19 is connected to the power supply lines 14a, 14x for transmitting the power supply voltages VDDX2, VSSX2.
b. On the other hand, each of the scanning line buffer circuit 23 and the vertical shift register 21 has a power supply voltage VDDY1,
The vertical clock buffer circuit 29 is connected to the power supply lines 22a and 22b transmitting the VSSY1, and the power supply voltage VDDY
2, power supply lines 24a and 24b for transmitting VSSY2. The array board 2A has a connector section 1A arranged at an end of the board. Power lines 12a, 12b, power line 14
a, 14b, power supply lines 22a, 22b, and power supply line 24
a and 24b are connected to an external power supply via this connector 1A.

FIG. 2 shows a detailed configuration of the scanning line driving circuit 20. The vertical clock buffer circuit 29 is connected to receive the clock signal φ and the inverted clock signal φ bar supplied as the vertical clock signal, and includes a clock signal φ buffer and a column of inverters 29a, 29b, 29c, 29d connected in cascade. It has an inverted clock signal φ bar buffer composed of connected inverters 29e, 29f, 29g and 29h. These inverters 29
a, 29b, 29c, 29d, 29e, 29f, 29
g and 29h are P channel and N channel TF
T, and is operated by power supply voltages VDDY2 and VSSY2 supplied via power supply lines 24a and 24b. The buffer for the clock signal φ and the buffer for the inverted clock signal φ bar drive the clock line 26a and the inverted clock line 26b used as the first clock wiring, respectively, to transfer the clock signal φ and the inverted clock signal φ bar to the vertical shift register 21. Supply.

The flip-flops of the vertical shift register 21 are D-type flip-flops which are respectively assigned to a plurality of scanning lines 5 and connected in cascade. Each flip-flop is composed of clocked inverters 21a, 21b, 21d, 21e and inverters 21c, 21f. Each of these clocked inverters 21a, 21b, 21d, 21e and inverters 21c, 21f is configured by combining P-channel and N-channel TFTs.
Power supply voltages VDDY1, 2 supplied via
Operated by VSSY1. Clocked inverter 2
1a, 21b, 21d, and 21e are clock lines 26 for receiving clock signal φ and inverted clock signal φ bar.
a and the inverted clock line 26b. The clocked inverter 21a of each flip-flop sends the scan pulse supplied from the preceding flip-flop to the scan line buffer circuit 23 via the clocked inverter 21d and also sends it to the next flip-flop.

The scanning line buffer circuit 23 includes a plurality of buffers respectively assigned to a plurality of scanning lines.
Each buffer is connected in cascade with inverters 23a, 23
b, 23c and 23d. Each of these inverters 23 a, 23 b, 23 c, and 23 d is configured by combining P-channel and N-channel TFTs, and supplies power supply lines 22 a, 22
b, power supply voltages VDDY1 and VSSY1
Work by.

In the scanning line driving circuit 20 having such a configuration, the clock line 26a and the inverted clock line 26b are cascaded in the vertical shift register 21 and connected to all flip-flops respectively assigned to the plurality of scanning lines 5. Therefore, it has a very large parasitic capacitance. The vertical clock buffer circuit 29 has such a clock line 26a.
And the inverted clock line 26b is driven by the power supply voltages VDDY2 and VSSY2 supplied via the power supply lines 24a and 24b. By the operation of the vertical clock buffer circuit 29, the power supply voltages VDDY2 and VSSY2 are
Large voltage fluctuations occur on 4a and 24b in synchronization with the vertical clock signal. However, since the power supply lines 22a and 22b of the vertical shift register 21 and the scanning line buffer circuit 23 are different from the power supply lines 24a and 24b, the power supply voltage V
DDY1 and VSSY1 do not cause a large voltage fluctuation synchronized with the vertical clock signal. Therefore, the vertical scan output circuit SCV can output a stable scan pulse to the scan line 5 without causing a pulse delay or a malfunction due to a power supply voltage fluctuation. Further, in the vertical shift register 21 and the scanning line buffer circuit 23, since no TFT is affected by the above-described power supply voltage fluctuation, good operation reliability can be maintained. Further, the scanning line buffer circuit 23 includes the power supply lines 22a and 22 that are not affected by the voltage fluctuation as described above.
b, power supply voltages VDDY1, VSSY1
Drive the scanning lines 5, so that T
FT7 can be controlled stably. That is, a TFT for writing operation for applying a signal voltage on the signal line 3 to the pixel electrode 8 is used.
7 can be reliably turned on, and the TFT 7 can be reliably turned off for the holding operation of holding the pixel electrode voltage by electrically separating the pixel electrode 8 from the signal line 3. Therefore,
It is possible to obtain good image quality without writing unevenness, holding unevenness, and the like due to the fluctuation of the scanning line voltage.

FIG. 3 shows a detailed configuration of the signal line driving circuit 10. The horizontal clock buffer circuit 19 is connected to receive a clock signal φ and an inverted clock signal φ bar supplied as a horizontal clock signal, and includes a clock signal φ buffer and a column of inverters 19a, 19b, 19c, and 19d connected in cascade. It has an inverted clock signal φ bar buffer composed of connected inverters 19e, 19f, 19g, and 19h. These inverters 19
a, 19b, 19c, 19d, 19e, 19f, 19
g and 19h are P channel and N channel TF
T, and operates with power supply voltages VDDX2 and VSSX2 supplied via power supply lines 14a and 14b. The buffer for the clock signal φ and the buffer for the inverted clock signal φ bar drive the clock line 16a and the inverted clock line 16b used as the second clock wiring, respectively, to thereby transfer the clock signal φ and the inverted clock signal φ bar to the horizontal shift register 11. Supply.

The flip-flops of the horizontal shift register 11 are D-type flip-flops respectively assigned to the plurality of signal lines 3 and connected in cascade. Each flip-flop is connected to a clocked inverter 11a, 11b, 11d, 11e.
And inverters 11c and 11f. These clocked inverters 11a, 11b, 11d, 11e
And each of inverters 11c and 11f is configured by combining P-channel and N-channel TFTs, and is provided with power supply voltage VDDX supplied through power supply lines 12a and 12b.
1, operated by VSSX1. Clocked inverters 11a, 11b, 11d and 11e are connected to clock line 16a and inverted clock line 16b to receive clock signal φ and inverted clock signal φ bar. The clocked inverter 11a of each flip-flop sends the scan pulse supplied from the preceding flip-flop to the TG buffer circuit 13 via the clocked inverter 11d and also sends it to the next flip-flop.

The TG buffer circuit 13 includes a plurality of signal lines 3
Is composed of a plurality of buffers respectively assigned.
Each buffer is connected to inverters 13a, 13 connected in cascade.
b, 13c and 13d. Each of these inverters 13 a, 13 b, 13 c, 13 d is configured by combining P-channel and N-channel TFTs, and supplies power lines 12 a, 12
b, power supply voltages VDDX1, VSSX1
Work by.

In the signal line driving circuit 10 having such a configuration, the clock line 16a and the inverted clock line 16b are cascaded in the horizontal shift register 11 and connected to all flip-flops respectively assigned to the plurality of signal lines 3. Therefore, it has a very large parasitic capacitance. The horizontal clock buffer circuit 19 is connected to such a clock line 16a.
And the inverted clock line 16b is driven by the power supply voltages VDDX2 and VSSX2 supplied via the power supply lines 14a and 14b. By the operation of the horizontal clock buffer circuit 19, the power supply voltages VDDX2 and VSSX2 are changed to the power supply line 1
Large voltage fluctuations occur on 4a and 14b in synchronization with the horizontal clock signal. However, since the power supply lines 12a and 12b of the horizontal shift register 11 and the TG buffer circuit 13 are different from the power supply lines 14a and 14b, the power supply voltage VD
DX1 and VSSX1 do not cause a large voltage fluctuation synchronized with the horizontal clock signal. Therefore, the horizontal scanning output circuit S
The CH can output a stable scanning pulse to the transmission gate 18 without causing a pulse delay or a malfunction due to power supply voltage fluctuation. Further, in the horizontal shift register 11 and the TG buffer circuit 13, since no TFT is affected by the above-described power supply voltage fluctuation, good operation reliability can be maintained. Further, the TG buffer circuit 13 is connected to the power supply voltage VDDX supplied via the power supply lines 12a and 12b which are not affected by the above-described voltage fluctuation.
1, the transmission gate 18 can be stably controlled by the VSSX1. That is, the transmission gate 18 is reliably turned on for the writing operation of applying the signal voltage on the video signal bus 17 to the signal line 3, and the signal line 3 is electrically separated from the video signal bus 17 to be turned on. Therefore, the transmission gate 18 can be surely turned off for the holding operation for holding the transmission. Therefore, it is possible to obtain good image quality without writing unevenness, holding unevenness, and the like caused by the fluctuation of the signal line voltage.

Next, a drive circuit integrated type active matrix liquid crystal display device according to a second embodiment of the present invention will be described with reference to FIG. FIG. 4 shows the configuration of this active matrix liquid crystal display device. This liquid crystal display device is configured similarly to the liquid crystal display device of the first embodiment shown in FIG. 1 except for the following points. 4, the same parts as those shown in FIG. 1 are denoted by the same reference numerals, and the description thereof will be omitted.

In this liquid crystal display device, the array substrate 2A,
The opposing substrate 2B and the liquid crystal layer 1 have the same structure as in the first embodiment. The power supply lines 14a and 12a are connected to the power supply voltage VDD.
X1 is connected in the connector 1A outside the array substrate 2A so as to receive the power supply voltage VDDX1, the power supply lines 14b and 12b are connected outside the connector 1A so as to receive the power supply voltage VDDX1 in common, and the power supply lines 24a and 22a are Power supply voltage VD
The power supply lines 24b and 22b are connected to the array substrate 2A so as to receive the power supply voltage VSSY1 in common within the connector portion 1A outside the array substrate 2A so as to receive the DY1 in common.
Are connected in the connector section 1A outside the connector. That is, the power supply lines 24a for the vertical clock buffer circuit 29,
24b is a power supply line 22a, 2 for the vertical scanning output circuit CSV.
As shown in FIG. 4, the power supply lines 14a and 14b for the horizontal clock buffer circuit 19 are different from the power supply lines 12a and 12b for the horizontal scan output circuit CSH as shown in FIG. Thus, it is a separate system in the array substrate 2A.

Even with such a configuration, the vertical scanning output circuit CSV and the horizontal scanning output circuit CSH are hardly affected by power supply voltage fluctuations caused by the operations of the vertical clock buffer circuit 29 and the horizontal clock buffer circuit 19, respectively. The same effect as in the first embodiment can be obtained.

Next, a drive circuit integrated type active matrix liquid crystal display device according to a third embodiment of the present invention will be described with reference to FIG. FIG. 5 shows the configuration of this active matrix liquid crystal display device. This liquid crystal display device is configured similarly to the liquid crystal display device of the first embodiment shown in FIG. 1 except for the following points. 5, the same parts as those shown in FIG. 1 are denoted by the same reference numerals, and the description thereof will be omitted.

In this liquid crystal display device, the opposing substrate 2B and the liquid crystal layer 1 have the same structure as in the first embodiment. Regarding array substrate 2A, power supply lines 14a and 12a are connected on array substrate 2A inside connector portion 1A so as to receive power supply voltage VDDX1 in common, and power supply lines 14b and 1a are connected.
2b is connected within the array board 2A inside the connector section 1A so as to receive the power supply voltage VDDX1 in common, and the power supply lines 24a and 22a are connected inside the array board 2A inside the connector section 1A so as to receive the power supply voltage VDDY1 in common. The power supply lines 24b and 22b are connected to the array substrate 2A inside the connector 1A so as to receive the power supply voltage VSSY1 in common.
Connected within. That is, the power supply lines 24a and 24b for the vertical clock buffer circuit 29 are connected to the vertical scanning output circuit CS.
The power supply lines 22a and 22b for V and the power supply lines 14a and 14b for the horizontal clock buffer circuit 19 are separated from each other in the array substrate 2A except for the periphery of the connector section 1A as shown in FIG. As shown in FIG. 5, the power supply lines 12a and 12b for the circuit CSH are separated from the power supply lines 12a and 12b in the array substrate 2A except for the periphery of the connector 1A.

With this configuration, the same effects as those of the first and second embodiments can be obtained. The present invention is not limited to the above-described embodiment, and can be variously modified without departing from the gist of the invention. For example, the clock buffer circuits 19 and 29 shown in FIG. 1 may be arranged in several places in the signal line driving circuit 10 and the scanning line driving circuit 20 as shown in FIG.

In the liquid crystal display devices according to the first to third embodiments, the signal line driving circuit 10 and the scanning line driving circuit 20 include clock buffer circuits 19 and 29, respectively. Also, the present invention can be applied to a liquid crystal display device in which only one of the scanning line driving circuits 20 includes a clock buffer circuit.

[0031]

As described above, according to the present invention, it is possible to provide a liquid crystal display device which can prevent the quality of the displayed image from being deteriorated by the influence of the power supply voltage fluctuation generated in the clock signal distribution operation.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a drive circuit integrated type active matrix liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of a scanning line driving circuit illustrated in FIG. 1;

FIG. 3 is a diagram illustrating a configuration of a signal line driving circuit illustrated in FIG. 1;

FIG. 4 is a diagram showing a configuration of a drive circuit integrated type active matrix liquid crystal display device according to a second embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a drive circuit integrated liquid crystal display device according to a third embodiment of the present invention.

FIG. 6 is a diagram showing a modification of the clock buffer circuit shown in FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Liquid crystal layer 2A ... Array substrate 2B ... Counter substrate 3 ... Signal line 5 ... Scanning line 7 ... TFT 8 ... Pixel electrode 10 ... Signal line drive circuit 11 ... Shift register 12a, 12b ... Power supply line 13 ... TG buffer circuit 14a. 14b power line 15a, 15b power line 16 clock line 16a clock line 16b inverted clock line 17 video signal bus 18 transmission gate 19 horizontal clock buffer circuit 1A connector part for array substrate 20 scanning line drive Circuit 21 shift register 22a, 22b power line 23 scanning line buffer circuit 24a, 24b power line 25a, 25b power line 26 clock line 26a clock line 26b inverted clock line 29 vertical clock buffer circuit

Claims (7)

[Claims] A plurality of pixel electrodes arranged in a matrix; a plurality of scanning lines arranged along rows of the pixel electrodes; a plurality of signal lines arranged along columns of the pixel electrodes; A plurality of switching elements which are arranged near intersections of the scanning lines and the plurality of signal lines, and which are controlled via the corresponding scanning lines to apply a signal voltage on the corresponding signal lines to the corresponding pixel electrodes, and the plurality of scanning lines Substrate including a scanning line driving circuit for driving a pixel line and a signal line driving circuit for driving a plurality of signal lines, a counter substrate including a counter electrode facing the plurality of pixel electrodes, the array substrate and the counter substrate A liquid crystal layer interposed therebetween, wherein at least one of the scanning line drive circuit and the signal line drive circuit amplifies a clock signal supplied from outside the array substrate. A buffer circuit, a scan output circuit for sequentially scanning the plurality of scan lines or signal lines in response to a clock signal supplied from the clock buffer circuit, a power supply line for a clock buffer circuit, and a power supply line for the clock buffer circuit. A liquid crystal display device including a separately provided power supply line for a scanning output circuit. 2. The array substrate includes a plurality of pixel electrodes,
The liquid crystal display device according to claim 1, wherein the liquid crystal display device is a glass plate including the plurality of scanning lines, the plurality of signal lines, the plurality of switching elements, the scanning line driving circuit, and the signal line driving circuit. 3. The liquid crystal display device according to claim 1, wherein the clock buffer circuit and the scan output circuit are configured by combining a plurality of thin film transistors. 4. The liquid crystal display device according to claim 3, wherein each of the plurality of thin film transistors is a polysilicon thin film transistor. 5. The shift register according to claim 1, wherein the scan output circuit shifts a scan pulse in response to a clock signal supplied from the clock buffer circuit, and sequentially outputs the scan pulse from a plurality of output terminals. 2. The liquid crystal display device according to claim 1, further comprising a scanning line buffer circuit that amplifies a scanning pulse obtained from each output terminal of the register and drives a corresponding scanning line. 6. The signal line drive circuit, wherein the scan output circuit is connected to a video signal bus for transmitting a video signal supplied from outside the array substrate, and is connected between the video signal bus and a corresponding signal line. A plurality of switches, a shift register for shifting a scan pulse in response to a clock signal supplied from the clock buffer circuit and sequentially outputting the shift pulse from a plurality of output terminals, and amplifying a scan pulse obtained from each output terminal of the shift register. 2. The liquid crystal display device according to claim 1, further comprising a switch buffer circuit for driving a corresponding switch. 7. The liquid crystal display according to claim 1, wherein the power supply wiring for the clock buffer circuit has no electrical contact with the power supply wiring for the scan output circuit except in the vicinity of an end of the array substrate. apparatus.