JP2000114458A - Trenched capacitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a trenched capacitor by which reduction in yields due to cracking or the like can be suppressed and whose time constant can be shortened. SOLUTION: An outer semiconductor layer 3 and an inner conductive layers 5 and 6 comprise a pair of electrodes in a capacitor. Since the inner conductive layers 5 and 6 comprising one of the electrodes of the capacitor are made of polysilicon whose inner concentration of impurities is set lower than the outer concentration, the stress in a concave can be reduced as compared with a conventional capacitor. Accordingly, the yields in manufacture and characteristics can be improved. Further, with the density set in the above way, high-speed operations can be performed by reducing the resistance and the parasitic capacitance.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a trench capacitor.

[0002]

2. Description of the Related Art A conventional trench type capacitor using polysilicon is described in Japanese Patent Application Laid-Open No. Hei 2-165661. In this trench capacitor, an insulator layer is formed in a concave portion formed on the surface of the semiconductor substrate, and the inner surface of the insulator layer is covered with a polysilicon layer. further,
The BP constituting the core of the trench is located inside the polysilicon layer.
SG (boron-added phosphorus glass) is embedded.

[0003]

However, in conventional trench capacitors, cracks are formed in the trench capacitor due to thermal stress between the BPSG and the polysilicon, thereby lowering the yield. Further, since BPSG is an insulator, the time constant as a capacitor is increased, and its high-speed operation is suppressed. Therefore, in order to solve these problems, it is conceivable that the core of the trench type capacitor is also formed of polysilicon. The time constant will increase.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a trench capacitor capable of suppressing a decrease in yield due to factors such as cracks and shortening the time constant.

[0005]

In order to solve the above-mentioned problems, a trench capacitor according to the present invention comprises an outer conductive layer forming a concave portion on a surface of a semiconductor substrate, an insulator layer covering an inner surface of the outer conductive layer, And a trench-type capacitor including an inner conductive layer covering an inner surface of the insulator layer, wherein the inner conductive layer is made of polysilicon having an inner impurity concentration set lower than that of the outer.

According to this trench capacitor, the outer and inner conductive layers form a pair of electrodes in the capacitor. Since the inner conductive layer forming one electrode of the capacitor is made of polysilicon whose impurity concentration on the inside is set lower than that on the outside, the stress in the concave portion can be reduced as compared with the related art.

Further, by lowering the impurity concentration inside the inner conductive layer, the filling property of polysilicon at the time of manufacturing can be improved. Further, since the impurity concentration on the outside is set relatively higher than that on the inside, a reduction in the resistance value can be achieved in synergy with the improvement of the embedding property, and the high-speed operation can be achieved by reducing the resistance value and the parasitic capacitance. Can be made possible.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A trench capacitor according to an embodiment will be described below. The same reference numerals are used for the same elements or elements having the same functions, and overlapping descriptions are omitted.

FIG. 1 is a sectional view of a semiconductor substrate on which a trench capacitor is formed. The trench capacitor according to the present embodiment has a high-concentration n-type semiconductor layer 2 forming a flat surface of an n-type semiconductor substrate 1 and an outer conductive layer 3 formed of a high-concentration p-type semiconductor layer forming a recess of the substrate 1. And The inner surface of the outer conductive layer 3 is covered with an insulator layer 4 (trench portion) made of SiO _2.
The (flat portion) also covers the surface of the n-type semiconductor layer 2. Note that the high-concentration n-type semiconductor layer 2 may be provided as necessary, for example, for connection to another functional element.

The inner surface of the concave portion of the insulator layer 4 is covered with first and second inner conductive layers 5 and 6 made of polysilicon so that the concave portion is not closed. Note that the width of the trench is 0.8 μm or more.

The first inner semiconductor layer 5 is in contact with the surface of the insulator layer 4 and is made of high-concentration polysilicon. The second inner semiconductor layer 6 is located inside the first inner semiconductor layer 5 in the recess, and is made of non-doped or low-concentration polysilicon. In other words, the inner conductive layers 5 and 6 are made of polysilicon whose impurity concentration on the inside is set lower than that on the outside. The conductivity type of the inner semiconductor layers 5 and 6 may be either p-type or n-type, but is assumed to be n-type here.

According to this trench capacitor, the outer semiconductor layer 3 and the inner conductive layers 5 and 6 form a pair of electrodes in the capacitor. Since the inner conductive layers 5 and 6 constituting one electrode of the capacitor are made of polysilicon in which the inner impurity concentration is set lower than that of the outer, the stress in the concave portion can be reduced as compared with the related art. The generation of cracks can be suppressed, and the production yield and its characteristics can be improved.

Further, by lowering the impurity concentration inside the inner conductive layers 5 and 6, the filling property of polysilicon at the time of manufacturing can be improved. Also,
Since the impurity concentration on the outside is set relatively higher than that on the inside, it is possible to achieve a reduction in the resistance value synergistically with the improvement of the embedding property, and reduce the resistance value and the parasitic capacitance to achieve high-speed operation. Can be possible.

Although the second inner semiconductor layer 6 is non-doped when deposited on the substrate 1, impurities in the first inner semiconductor layer 5 diffuse into the second inner semiconductor layer 6 by a subsequent heat treatment. are doing. In the second inner semiconductor layer 6, in addition to the increase of the impurity concentration due to the diffusion, the improvement of the crystallinity by the heat treatment and the activation of the impurity are simultaneously performed, and accordingly, the resistance value is reduced.

[0015] The method of manufacturing the trench capacitor is as follows.
Various examples are conceivable, and a preferred example will be described below.

First, a semiconductor substrate 1 made of low-concentration n-type Si is prepared, and a flat portion of an insulator layer 4 made of SiO ₂ is formed on the surface by thermal oxidation. Next, the insulating layer 4 in the region where the concave portion to be the trench is to be formed is removed by etching, and dry etching is performed using the insulating layer 4 as a mask to form a concave portion extending from the substrate surface to a deep portion.

The outer semiconductor layer 3 is formed by adding a p-type impurity such as boron to the surface in the concave portion by using thermal diffusion or ion implantation. Further, by performing thermal oxidation, a trench portion of the insulator layer 4 made of SiO ₂ is formed on the surface in the concave portion. Thereafter, ions are implanted into the surface of the substrate 1 via the insulator layer 4 to form the high-concentration n-type semiconductor layer 2 immediately below the flat portion of the insulator layer 4.

Subsequently, low pressure chemical vapor deposition (LPCV)
Using the method D), the impurity concentration is 5 × 10 ^{20 to} 5 × 10 ^22.
A first inner semiconductor layer 5 made of approximately high-concentration n-type polysilicon is formed on the surface of the insulator layer 4 with a thickness of approximately 100 to 300 nm. The thickness at this time is set to such an extent that the trench is not closed. As a source gas, phosphine containing phosphorus as a dopant is used in addition to silane containing silicon and the like, and the formation temperature is set to 620 ° C. Next, a second inner semiconductor layer 6 made of non-doped silicon is formed with a thickness of 1 μm on the first inner semiconductor layer 5 using the same method, and the inside of the recess is filled with the second inner semiconductor layer 6. Here, the second inner semiconductor layer 6 is formed immediately and continuously after the formation of the first inner semiconductor layer 5, thereby shortening the manufacturing time.

Finally, the substrate 1 is annealed at 950 ° C. By this heat treatment, the high concentration first inner semiconductor layer 5
The impurity diffuses into the non-doped second inner semiconductor layer 6 to increase the impurity (carrier) concentration of the second inner semiconductor layer 6 and perform the above-described improvement in crystallinity and activation. In addition, the above process suppresses the generation of voids in the trenches and the accompanying cracks.

As described above, the trench type capacitor according to the above-described embodiment includes the outer conductive layer 3 forming the concave portion on the surface of the semiconductor substrate 1, the insulator layer 4 covering the inner surface of the outer conductive layer 3, In the trench capacitor including the inner conductive layers 5 and 6 covering the inner surface of the body layer 4, the inner conductive layers 5 and 6 are made of polysilicon whose inner impurity concentration is set lower than that of the outer. According to the trench capacitor of the present embodiment, high-speed operation can be achieved, and the yield during manufacturing can be improved. Such a trench type capacitor is a UMOS
-Applicable to IGBT devices and trench isolation.

FIG. 2 is a cross-sectional view of an IGBT (insulated gate bipolar transistor) using the same trench type capacitor as described above. The surface layer of the n-type semiconductor substrate 10 has a p-type semiconductor layer 1
Has been replaced by 1. A high-concentration n-type semiconductor region 12 is formed on the surface of a p-type semiconductor layer 11, and a high-concentration p-type semiconductor region 13 is formed adjacent to the n-type semiconductor region 12. The exposed surface of the n-type semiconductor region 12 is covered with an insulator layer 14 made of SiO ₂ , and the insulator layer 14 extends inside the trench to constitute a part 14 ′ of the capacitor.

As described above, the insulator layer 1 in the trench
A high-concentration polysilicon layer 15 is formed inside 4 ′, and a low-concentration polysilicon layer 16 is formed further inside. The polysilicon layer 16 is connected to a gate electrode 17 made of aluminum, and the n-type semiconductor region 12 and the p-type
The type semiconductor region 13 is connected to an emitter electrode 18 made of aluminum. The electrodes 17 and 18 are NS
It penetrates through holes provided in an interlayer film made of G, BPSG, or the like.

A back electrode 19 is provided on the back side of the semiconductor substrate 10.
Are formed. The n-type semiconductor region 12 functions as an emitter of the transistor. When a positive potential is applied to the gate electrode 17 of the trench-type capacitor having the MOS structure with a forward bias applied thereto, electrons gather outside the trench-type capacitor. This serves as an n-type channel and connects the emitter and the substrate 10 as a collector. Note that this channel formation region forms an outer conductive layer of the capacitor.

In addition, holes remaining in the p-type semiconductor layer 11 during the switching operation of the transistor can be extracted from the emitter electrode 18 through the p-type semiconductor region 13, thereby improving the operation speed. it can.

[0025]

As described above, according to the trench capacitor of the present invention, high-speed operation and the like can be achieved by setting the impurity concentration of the inner conductive layer made of polysilicon.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor substrate on which a trench capacitor is formed.

FIG. 2 is a cross-sectional view of a semiconductor substrate on which an IGBT is formed.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 3 ... Outer conductive layer, 4 ... Insulator layer, 5,
6 ... inner conductive layer.

Claims (1)

[Claims] 1. A trench capacitor comprising: an outer conductive layer forming a recess in a surface of a semiconductor substrate; an insulator layer covering an inner surface of the outer conductive layer; and an inner conductive layer covering an inner surface of the insulator layer. 3. The trench-type capacitor according to claim 1, wherein the inner conductive layer is made of polysilicon whose impurity concentration on the inside is set lower than that on the outside.