JP2000114142A - Manufacture of semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve positioning accuracy by utilizing an alignment mark, and to remove the alignment mark without performing processes dedicated to the removal. SOLUTION: When an LED array element 11 is formed on an AlGaInP wafer 10, a protruding part 2 is formed by mesa etching performed on dicing lines 12 as an alignment mark. When a metal film is utilized as an alignment mark in the middle of a manufacturing process, the width of the metal film is widened twice the amount of side etching, so that the metal film an be removed by the side etching contained in the process to be performed later such as photolithography, etc. Since the alignment mark is formed within a dicing line region 3, the LED array element 11 can be formed efficiently, and the dicing mark can be removed by a dicing process which is performed along the dicing line 12. As there is no cutting of alignment mark by a metal film, the dicing process can be performed in an efficient manner.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method of manufacturing a semiconductor device in which a plurality of semiconductor elements are formed on a semiconductor wafer, and more particularly to the formation and removal of an alignment mark for performing alignment between a plurality of manufacturing steps.

[0002]

2. Description of the Related Art Many steps are performed when semiconductor elements are formed on a semiconductor wafer. In particular, in a photolithographic step or a wafer test step, it is necessary to prevent a displacement between the steps. In particular, in the photolithographic step, it is necessary to perform alignment for accurately aligning a photomask pattern with a wafer pattern, which is a circuit pattern formed on a semiconductor wafer in a previous process.
However, when the wafer pattern shape is smaller than the photomask pattern shape, alignment with the photomask pattern may not be possible with only a circuit pattern actually required as a semiconductor element, or alignment accuracy may be reduced. In such a case, it is necessary to form an alignment mark used only for positioning in addition to the pattern actually used in the semiconductor element. Further, by using the alignment mark as the origin of positioning in a wafer test process or the like, work efficiency can be improved and errors can be reduced.

Prior art techniques for providing alignment marks on dicing lines or scribe lines for cutting individual semiconductor elements from a semiconductor wafer are disclosed in, for example, Japanese Patent Application Laid-Open No. Sho 60-170935 and Japanese Utility Model Application Laid-Open No. Sho 60-181.
034 and the like. JP-A-60-17093
In No. 5, a wafer alignment mark is provided in a scribe pattern and is formed on the surface of a semiconductor wafer used as a semiconductor element, and the surface area of the semiconductor wafer is effectively used to increase the number of semiconductor elements to be obtained. . In Japanese Utility Model Application Laid-Open No. 60-10342, an alignment mark for dicing is provided on the scribe line to improve the accuracy of the alignment work before dicing.

Japanese Patent Application Laid-Open No. Hei 2-1188641 discloses that a length is regulated when an alignment mark is formed with a metal film such as aluminum on a dicing line, and a bonding wire or the like is formed even when a residue is turned up during dicing. Prior art that prevents short circuits has been disclosed. Japanese Patent Application Laid-Open No. 2-152218 discloses a prior art in which an alignment mark is formed on a convex portion formed in a dicing line, and the detection accuracy when a resist film is applied thereon is improved. In Japanese Patent Application Laid-Open No. 5-129176, an alignment mark is formed on a scribe line, a photoresist pattern is formed so that only a used alignment mark portion is exposed before a scribe step, and the alignment mark is removed by an etching process. Prior art is disclosed.

[0005]

When an alignment mark is used in a manufacturing process for forming a semiconductor light emitting device on a semiconductor wafer as a semiconductor device, there are the following problems.

When an alignment mark is provided in a semiconductor light emitting device, the alignment mark itself can be a partial light emitting device. For this reason, the contact of the bonding wire at the time of wire bonding may cause light emission, leakage, or the like, resulting in poor characteristics and lowering the yield.

When a metal film or the like is used as an alignment mark when the alignment mark is placed on the dicing line without placing the alignment mark in the semiconductor light emitting element, the dicing blade must also cut the metal film portion. It is necessary to cut not only hard and brittle semiconductor wafers, but also relatively soft and viscous metal parts, so that the sharpness of the dicing blade deteriorates, dicing yield decreases due to increased chipping, and maintenance frequency is reduced. The problem that the number increases.

[0008] Identification ink is usually applied to semiconductor light emitting devices that fail the wafer test.
In the case of a semiconductor wafer surface with good wettability or a mesa-type device, the ink easily flows, and the ink flows to the adjacent semiconductor light emitting device chip portion having good characteristics, and a good product in the wafer test is defective. There is a risk of becoming. Further, in order to avoid such a situation, a high positioning accuracy of the inker for attaching the ink is required. Although an alignment mark is used to indicate the origin as a reference in a wafer test, a more effective function is required in relation to ink.

[0009] Japanese Patent Application Laid-Open No.
In the prior art of 181034, it is described that an alignment mark is provided in a scribe area and used for positioning, which is an intended use, but nothing is described about how to process a used alignment mark. Absent. If a metal layer, which is a metal film for electric wiring, is used as the alignment mark, the sharpness of the blade is reduced during dicing as described above, which causes a problem. Even in the prior art of Japanese Patent Application Laid-Open No. Hei 2-1188641, the sharpness of the dicing blade should be poor. Also,
Even in the prior art of Japanese Patent Application Laid-Open No. 2-152218, since the alignment mark is formed in the dicing line, there must be a problem that the blade becomes dull during dicing. To solve such a problem, Japanese Patent Application Laid-Open No. 5-129
At 176, the alignment mark is removed by performing a dedicated etching process before the scribe process. However, since the etching process is performed to remove the alignment mark, the number of processing steps increases, and the manufacturing cost increases.

An object of the present invention is to provide a method of manufacturing a semiconductor device which can improve the positioning accuracy and the like by using an alignment mark and can easily remove an unnecessary alignment mark without providing a dedicated process. It is to be.

[0011]

SUMMARY OF THE INVENTION According to the present invention, in a method of manufacturing a semiconductor device in which a plurality of semiconductor devices are simultaneously formed on a semiconductor wafer through a plurality of processes, a subsequent process is used for alignment. An alignment mark is formed on a semiconductor wafer in a preceding step, and after the subsequent step and before a dicing step of dividing the semiconductor wafer into semiconductor elements, an alignment mark is formed on the semiconductor wafer. A method for manufacturing a semiconductor device, comprising: removing the semiconductor element.

According to the present invention, when a plurality of semiconductor elements are simultaneously formed on a semiconductor wafer through a plurality of processes, an alignment mark used for alignment in a subsequent process is formed on the semiconductor wafer. It is formed. In the subsequent step, positioning of a photolithographic mask, a wafer test using the position of the mask as an origin, and the like can be performed using the alignment marks formed in the preceding step. When it becomes unnecessary to use the alignment mark, unnecessary alignment marks can be removed by an etching process such as a lithographic process after the subsequent step. Since the width of the alignment mark is less than twice the amount of the side etch, the alignment mark can be easily removed by performing the side etch from both sides.

In the present invention, the alignment mark is
The semiconductor wafer is formed on a dicing line that is cut to divide the semiconductor wafer in the dicing step.

According to the present invention, an alignment mark can be formed on a dicing line that is cut to divide a semiconductor wafer in a dicing process, and the number of chips of a semiconductor element can be increased. In the dicing process,
The alignment mark can be removed.

Further, in the present invention, the alignment mark is formed so as to have a line width of less than twice the amount of side etching in the etching process of the metal film at the time of the electrode wiring forming process,
It is characterized in that it is removed by an etching process included after the subsequent step.

According to the present invention, the alignment mark of the metal film can be removed by utilizing the side etching.

Further, the present invention, through a plurality of processes,
In a method of manufacturing a semiconductor device in which a plurality of semiconductor devices are simultaneously formed on a semiconductor wafer, an alignment mark used for alignment in a subsequent process is formed on a dicing line so as to become a convex portion by mesa etching. A method for manufacturing a semiconductor device, comprising:

According to the present invention, the alignment marks formed on the dicing lines are formed so as to be convex portions by mesa etching. Therefore, even if a photoresist film or the like is formed on the alignment, the alignment marks can be easily formed. And can be easily used for positioning in a later process.

In the present invention, the alignment mark formed so as to be a projection on the dicing line is subjected to a characteristic test on each semiconductor element, and identification ink is applied to the semiconductor element determined to be defective in characteristics. It is removed after the wafer test step.

According to the present invention, when a discriminating ink is applied to a semiconductor element determined to be defective in a wafer test, an alignment mark is formed on a dicing line surrounding each semiconductor element so as to have a convex portion. Is formed.
Even if the identification ink is adhered to the surface of the semiconductor element which is determined to be defective based on the result of the wafer test of the semiconductor element, the ink is blocked by the convex portion and does not flow out to the chip region of the adjacent semiconductor element. It is possible to avoid a situation where a semiconductor element determined to be non-defective in the test is determined to be defective due to the flow of ink.

In the present invention, the semiconductor device is a semiconductor light emitting device.

According to the present invention, a semiconductor light emitting device can be formed by forming an alignment mark on a dicing line and effectively utilizing the surface area of a semiconductor wafer. In addition, since no extra pattern is provided on the surface of the semiconductor wafer on which the semiconductor light emitting device is formed, the semiconductor light emitting device can be formed without causing poor characteristics or the like.

[0023]

FIG. 1 shows an embodiment of the present invention, in which a light emitting portion 1 and a convex portion 2 serving as an alignment mark are provided.
Is shown. FIG. 1A shows a state as viewed in plan, and FIG. 1B shows a state as viewed from the section line AA in FIG. 1A. The convex portion 2 is provided in the dicing region 3 and is formed by mesa-etching the P-clad layer 5 from the current diffusion layer 4 together with the light emitting portion 1. The current diffusion layer 4 is an AlGaInP wafer 1 formed by epitaxial growth on an N-substrate 9 together with a P-cladding layer 5, a PN junction 6, an N-active layer 7, and an N-cladding layer 8.
On 0, it becomes a component of a light emitting diode (hereinafter abbreviated as “LED”) array element 11. The convex part 2 is LE
The D array element 11 is formed on a dicing line 12 indicating a position where the D array element 11 is separated from the AlGaInP wafer 10. That is, the LED array element 11 is a monolithic semiconductor element in which a plurality of LED array elements are simultaneously formed on a quaternary semiconductor wafer which is the AlGaInP wafer 10.

FIG. 2 shows an outline of the overall manufacturing process of a monolithic semiconductor device such as the LED array device 11 of FIG. Manufacturing starts from step s1, and an N-substrate 9 is prepared. In step s2, N-
The cladding layer 8, the N-active layer 7, the PN-junction 6, the P-cladding layer 5, and the current spreading layer 4 are sequentially formed by epitaxial growth. In step s3, as shown in FIG. 1, the light emitting portion 1 and the convex portion 2 are formed by mesa etching on the current diffusion layer 4.

Next, in step s4, an insulating film is formed.
In step s5, an electrode wiring is formed. In these steps, a mask is used in photolithographic processing, etching is performed to remove unnecessary portions, and a necessary insulating film is formed, a contact region with an electrode is formed, and a metal film is formed. In these steps, the intersection of the projections 2 in FIG. 1 indicates the origin of the alignment mark, and the mask used in the subsequent process performs relative positioning with respect to the intersection of the projections 2. Alignment marks made of a metal film which are not required in a later step are removed at the same time as the etching process.

Insulating film formation in step s4 and step s5
Of the LED array element 11
Is formed, a wafer test is performed in step s6. In the wafer test, an electrical characteristic test is performed on each of the LED array elements 11, and the L is determined to be defective.
Identification ink is applied to the ED array element 11. In the present embodiment, the convex portion formed by the mesa etching is provided along the dicing line 12, so that the attached ink is prevented from flowing into the adjacent chip area of the LED array element 11 determined to be a good product. can do. When the wafer test is completed, dicing for cutting the dicing region 3 is performed in step s7. By the dicing step, at least the alignment mark formed of the metal film has been removed by etching, so that it is possible to avoid a problem that the sharpness of the dicing blade is deteriorated. When the dicing in step s7 is completed, in step s8 AlGaIn
The individual LED array elements 11 are separated from the P wafer 10, and the basic manufacturing process of the LED array elements 11 is completed.

FIG. 3 shows a state after the completion of the electrode forming photolithographic processing in the electrode wiring forming step of step s5 in FIG. As shown in FIG. 3A, an electrode pattern 22 is formed of a photoresist for each light emitting unit 1 using the alignment mark 20 at the intersection of the convex portions 2 in FIG. 1 as an origin which is a reference for alignment. 3B, an alignment mark 23 made of photoresist is formed near the alignment mark 20 at the intersection of the projections 2. As shown in FIG. The alignment mark 20 does not include a metal film because it is an intersection of the convex portions 2 formed by the mesa etching of the current diffusion layer. The alignment mark 23 has a shape capable of vertical and horizontal alignment with respect to the alignment mark 20, and has a line width w of not more than twice the side etch amount a in the next etching step (w ≦ 2a). Design to be. Since the fluctuation of the etching can be considered, it is preferable to design w <2a. Since the alignment mark 23 is a photomask-like pattern, a metal film remains on the AlGaInP wafer 10 together with the photoresist in this shape. However, since the metal film is subjected to side etching a from both sides in the etching step, the alignment mark of the metal film having the line width w is removed.

FIG. 3C shows an example of the alignment mark 24 designed to have a large width. The alignment mark of the metal film covered with such a large photoresist is
As shown as the alignment mark 25 in FIG. 3D, it remains after the etching. The alignment mark 25 is a
Although the width is narrowed by the side etch amount, the blade remains on the dicing line 12 and may be clogged when cut with a blade in the dicing process.

FIG. 4 shows a state after the photolithographic processing shown in FIG. 3A has been completed and after a further etching step. FIG. 4A is a plan view, FIG.
FIG. 4B shows the state as viewed from the section line BB in FIG. Electrode pattern 2 that contacts light emitting unit 1
2 are formed, and many concave portions are formed on the surface of the LED array element 11. In such a state,
When a wafer test is performed in step s6 in FIG. 2 and ink is applied as a bad mark to the LED array element 11 determined to be defective, the ink is in a state of being very easy to flow.

FIG. 5 shows a state in which a bad mark 30 is displayed with ink on the LED array element 11 determined to be defective. FIG. 5A shows a case in which the LED array element 11 is formed on a semiconductor substrate by a conventional method, and shows that the tip 30 a of the ink applied as the bad mark 30 may spread to the adjacent LED array element 11. Show. As shown in FIG. 5B, the dicing line 12
If the convex portion 2 is formed on the top, the convex portion 2 blocks the flow of the ink, and the tip 30b of the bad mark 30 spreads over the adjacent chip of the LED array element 11 which is determined to be a good product. Can be prevented.

In the embodiment described above, the LED array elements 11 as the semiconductor light emitting elements are formed on the AlGaInP wafer 10 as the quaternary wafer of the compound semiconductor. The present invention can be similarly applied to the case of forming a semiconductor element, a semiconductor integrated circuit element, and the like.

[0032]

As described above, according to the present invention, the alignment mark is removed before the dicing step, so that the characteristics of the semiconductor element and the dicing step are not affected. In the semiconductor device manufacturing process, the mask alignment and the etching process are repeated in a plurality of photolithographic steps, so that the alignment mark formed in the preceding step is used in the subsequent step to perform the mask alignment, etc. Since unnecessary alignment marks are removed in the subsequent steps, problems caused by the alignment marks can be avoided.

Further, according to the present invention, since the alignment mark is formed on the dicing line, it is not necessary to secure the surface of the semiconductor wafer for forming the semiconductor element for forming the alignment mark, and it is effectively used for improving the characteristics of the semiconductor element. can do. Even if the alignment mark is formed on the dicing line, the alignment mark is removed before the dicing step, so that it is possible to prevent a dicing problem due to the presence of the alignment mark.

Further, according to the present invention, the alignment mark of the metal film can be removed by a subsequent etching process without providing a dedicated process.

Further, according to the present invention, since the alignment mark is formed as a projection on the dicing line,
The alignment mark has good discrimination, and positioning using the alignment mark can be performed accurately. The alignment mark can be removed in a dicing process.

Further, according to the present invention, the alignment mark formed as a projection on the dicing line is removed after the wafer test process. Therefore, even if ink is adhered to a semiconductor element determined to be defective in the wafer test. In addition, it is possible to prevent the ink from being blocked by the alignment mark and from flowing into the chip region of the semiconductor element determined to be non-defective in the adjacent wafer test, thereby avoiding a decrease in yield.

Further, according to the present invention, when manufacturing a semiconductor light emitting device, a photolithographic process and a wafer test process can be performed with high accuracy by effectively utilizing an alignment mark, and a problem occurs in a dicing process. The alignment mark can be removed before the dicing step so that the alignment mark does not occur.

[Brief description of the drawings]

FIGS. 1A and 1B are a plan view and a cross-sectional view illustrating a state in which a projection 2 serving as an alignment mark is formed according to an embodiment of the present invention.

FIG. 2 is a flowchart schematically showing an overall manufacturing process of a semiconductor device including the formation of the alignment mark of FIG. 1;

FIG. 3 shows an intersection of the protrusions 2 in FIG.
FIG. 9 is a partial plan view showing a limitation on a width when a metal film is used as an alignment mark in an electrode forming step used as an electrode.

4A and 4B are a plan view and a cross-sectional view showing a state where an etching step has been completed from the state shown in FIG.

FIG. 5 shows a state in which ink as a bad mark 30 is applied to a chip determined to be defective in a wafer test.
FIG. 9 is a partial plan view showing a comparison between a conventional manufacturing method and the present embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Light-emitting part 2 Convex part 3 Dicing area 4 Current diffusion layer 5 P-cladding layer 6 PN junction 7 N-active layer 8 N-cladding layer 9 N-substrate 10 AlGaInP wafer 11 LED array element 12 Dicing line 20,23, 24,25 alignment mark 22 electrode pattern 30 bad mark

Claims (6)

[Claims] 1. A method of manufacturing a semiconductor device, wherein a plurality of semiconductor devices are simultaneously formed on a semiconductor wafer through a plurality of processes, wherein an alignment mark used for alignment in a subsequent process is used in a preceding process. A semiconductor formed on a semiconductor wafer, wherein the alignment mark is removed from the semiconductor wafer after the subsequent step and before the dicing step of dividing the semiconductor wafer into semiconductor elements. Device manufacturing method. 2. The method according to claim 1, wherein the alignment mark is formed on a dicing line that is cut to divide the semiconductor wafer in the dicing step. 3. The alignment mark is formed so as to have a line width less than twice as much as a side etch amount in an etching process of a metal film during an electrode wiring forming process, and is performed by an etching process included in the subsequent steps. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is removed. 4. A method of manufacturing a semiconductor device in which a plurality of semiconductor devices are simultaneously formed on a semiconductor wafer through a plurality of processes, wherein an alignment mark used for alignment in a subsequent process is formed on a dicing line. Forming a convex portion by mesa etching. 5. An alignment mark formed on the dicing line so as to be a convex portion, a characteristic test is performed on each semiconductor element, and a wafer for attaching identification ink to a semiconductor element determined to be defective in characteristic is attached. 5. The method according to claim 4, wherein the removing is performed after the test step. 6. The method for manufacturing a semiconductor device according to claim 1, wherein said semiconductor device is a semiconductor light emitting device.