JP3563976B2 - Method for manufacturing semiconductor device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device in which a plurality of semiconductor elements are formed on a semiconductor wafer, and more particularly, to the formation and removal of an alignment mark for performing alignment between a plurality of manufacturing steps.
[0002]
[Prior art]
When a semiconductor element is formed on a semiconductor wafer, many steps are performed. In particular, in a photolithographic step or a wafer test step, it is necessary to prevent a positional shift or the like from occurring between the steps. In particular, in the photolithographic process, it is necessary to perform alignment for accurately aligning a photomask pattern with a wafer pattern, which is a circuit pattern formed on a semiconductor wafer in an earlier process. However, when the wafer pattern shape is smaller than the photomask pattern shape, alignment with the photomask pattern may not be possible with only a circuit pattern actually required as a semiconductor element, or alignment accuracy may be reduced. In such a case, it is necessary to form an alignment mark used only for positioning in addition to the pattern actually used in the semiconductor element. In addition, by using the alignment mark as the origin of positioning in a wafer test process or the like, work efficiency can be improved and errors can be reduced.
[0003]
Prior art in which an alignment mark is provided on a dicing line or a scribe line for cutting an individual semiconductor element from a semiconductor wafer when it is divided is disclosed in, for example, Japanese Patent Application Laid-Open No. Sho 60-170935 and Japanese Utility Model Application Laid-open No. Sho 60-181034. I have. In Japanese Patent Application Laid-Open No. Sho 60-170935, a wafer alignment mark is provided in a scribe pattern and is formed on the surface of a semiconductor wafer used as a semiconductor element, thereby effectively utilizing the surface area of the semiconductor wafer and increasing the number of semiconductor elements to be obtained. I am planning. In Japanese Utility Model Application Laid-Open No. 60-10342, an alignment mark for dicing is provided on the scribe line to improve the accuracy of the alignment work before dicing.
[0004]
Further, Japanese Patent Application Laid-Open No. Hei 2-1188641 discloses that the length is restricted when forming an alignment mark with a metal film such as aluminum on a dicing line so that even if a residue is turned up during dicing, a short circuit with a bonding wire or the like is prevented. Prior art is disclosed. Japanese Patent Application Laid-Open No. 2-152218 discloses a prior art in which an alignment mark is formed on a convex portion formed in a dicing line, and the detection accuracy when a resist film is applied thereon is improved. In Japanese Patent Application Laid-Open No. 5-129176, an alignment mark is formed on a scribe line, a photoresist pattern is formed so that only a used alignment mark portion is exposed before a scribe step, and the alignment mark is removed by an etching process. Prior art is disclosed.
[0005]
[Problems to be solved by the invention]
When an alignment mark is used in a manufacturing process of forming a semiconductor light emitting element on a semiconductor wafer as a semiconductor element, there are the following problems.
[0006]
{Circle around (1)} When an alignment mark is provided in a semiconductor light emitting device, the alignment mark itself can be a partial light emitting device. For this reason, the contact of the bonding wire at the time of wire bonding may cause light emission, leakage, or the like, resulting in poor characteristics and lowering the yield.
[0007]
{Circle around (2)} When a metal film or the like is used as an alignment mark when a metal film or the like is used as an alignment mark when the alignment mark is not provided in the semiconductor light emitting element, the dicing blade also needs to cut the metal film portion. It is necessary to cut not only hard and brittle semiconductor wafers, but also relatively soft and viscous metal parts, so the sharpness of the dicing blade deteriorates, the chipping increases, the dicing yield decreases, and the maintenance frequency decreases. Or a problem such as an increase in
[0008]
{Circle around (3)} Normally identifying ink is applied to semiconductor light-emitting elements that fail the wafer test. In the case of a semiconductor wafer surface with good wettability or a mesa-type device, ink easily flows, and ink flows to the chip portion of a semiconductor light-emitting device having good characteristics adjacent thereto, and a good product in a wafer test is defective. There is a risk of becoming. Further, in order to avoid such a situation, a high positioning accuracy of the inker to which the ink is attached is required. Although an alignment mark is used to indicate the origin as a reference in a wafer test, a more effective function is required in relation to ink.
[0009]
Although the prior arts of Japanese Patent Application Laid-Open Nos. 60-170935 and 60-181034 describe that alignment marks are provided in a scribe area and used for positioning, which is an intended use, any used alignment marks can be used. Nothing is described as to how to process. If a metal layer, which is a metal film for electric wiring, is used as the alignment mark, the sharpness of the blade is deteriorated at the time of dicing as described above, causing a problem. Even in the prior art of Japanese Patent Application Laid-Open No. Hei 2-1188641, the sharpness of the dicing blade should be poor. Further, even in the prior art of Japanese Patent Application Laid-Open No. 2-152218, since the alignment mark is formed in the dicing line, there must be a problem that the blade becomes dull during dicing. To cope with such a problem, in Japanese Patent Laid-Open No. 5-129176, an alignment mark is removed by performing a dedicated etching process before the scribe process. However, since the etching process is performed to remove the alignment mark, the number of processing steps increases, and the manufacturing cost increases.
[0010]
An object of the present invention is to provide a method of manufacturing a semiconductor element which can improve positioning accuracy and the like by using alignment marks and can easily remove unnecessary alignment marks without providing a dedicated process. is there.
[0011]
[Means for Solving the Problems]
The present invention provides a method for generating a semiconductor element, which simultaneously generates a plurality of semiconductor elements on a semiconductor wafer through a plurality of processes,
A process in which a subsequent process uses an alignment mark used for alignment in an electrode wiring forming process in the preceding process and after the subsequent process and before a dicing process for dividing a semiconductor wafer into semiconductor elements. A metal film for electrode wiring is formed on a semiconductor wafer so that the line width is less than twice the amount of side etching in the etching process included therein.
A method of manufacturing a semiconductor device, comprising: removing an alignment mark by a metal film from a semiconductor wafer by the etching process.
[0012]
According to the present invention, when a plurality of semiconductor elements are simultaneously formed on a semiconductor wafer through a plurality of processes, an alignment mark used for alignment by a subsequent process is formed on the semiconductor wafer. deep. In the subsequent step, positioning of a photolithographic mask, a wafer test using the position of the mask as an origin, and the like can be performed using the alignment marks formed in the preceding step. When the use of the alignment mark becomes unnecessary, unnecessary alignment marks can be removed by an etching process such as a lithographic process after the subsequent step. Since the width of the alignment mark is less than twice the amount of side etching, the alignment mark can be easily removed by performing side etching from both side surfaces.
[0013]
Further, in the present invention, the alignment mark is formed on a dicing line which is cut to divide the semiconductor wafer in the dicing step.
[0014]
According to the present invention, an alignment mark can be formed on a dicing line that is cut to divide a semiconductor wafer in a dicing process, and the number of chips of a semiconductor element can be increased. In the dicing step, the alignment mark can be removed.
[0017]
Further, in the present invention, a part of an alignment mark used for alignment in the subsequent step is formed on a dicing line so as to become a convex portion by mesa etching in the preceding step, and the dicing is performed. It is characterized in that it is removed in a process.
[0018]
According to the present invention, a part of the alignment mark used for alignment in the subsequent process is formed so as to be a convex portion by mesa etching. Therefore, even if a photoresist film or the like is formed on the alignment, it can be easily formed. Can be identified as an alignment mark, and can be easily used for positioning in a later step. Since the alignment line is formed on the dicing line, it can be removed in the dicing step.
[0019]
Further, the present invention is characterized in that, before the dicing step, a characteristic test is performed on each semiconductor element, and a wafer test step of attaching identification ink to the semiconductor element determined to have characteristic defects is performed.
[0020]
According to the present invention, the alignment marks are formed on the dicing lines surrounding each semiconductor element when the identification ink is applied to the semiconductor elements determined to be defective in the wafer test. ing. Even if the identification ink is applied to the surface of the semiconductor element which is determined to be defective based on the result of the wafer test of the semiconductor element, the ink is blocked by the convex portion and does not flow out to the chip region of the adjacent semiconductor element. It is possible to avoid a situation in which a semiconductor element determined as a non-defective product in a test is determined to be defective due to flowing of ink.
[0021]
Further, in the present invention, the semiconductor element is a semiconductor light emitting element.
[0022]
According to the present invention, a semiconductor light emitting device can be formed by forming an alignment mark on a dicing line and effectively utilizing the surface area of a semiconductor wafer. In addition, since no extra pattern is provided on the surface of the semiconductor wafer on which the semiconductor light emitting device is formed, the semiconductor light emitting device can be formed without causing poor characteristics or the like.
[0023]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 shows an embodiment of the present invention, in which a projection 2 serving as an alignment mark is formed together with a light emitting section 1. FIG. 1A shows a state as viewed in plan, and FIG. 1B shows a state as viewed from a section line AA in FIG. 1A. The convex portion 2 is provided in the dicing region 3 and is formed by mesa-etching the P-clad layer 5 from the current diffusion layer 4 together with the light emitting portion 1. The current diffusion layer 4, together with the P-cladding layer 5, the PN junction 6, the N-active layer 7, and the N-cladding layer 8, is formed on an AlGaInP wafer 10 formed on the N-substrate 9 by epitaxial growth. Hereinafter, these are referred to as “LEDs”. The convex portion 2 is formed on a dicing line 12 indicating a position at which the LED array element 11 is separated from the AlGaInP wafer 10. That is, the LED array element 11 is a monolithic semiconductor element in which a plurality of LED array elements are simultaneously formed on a quaternary semiconductor wafer that is the AlGaInP wafer 10.
[0024]
FIG. 2 shows an outline of the overall manufacturing process of a monolithic semiconductor device such as the LED array device 11 of FIG. Manufacturing starts from step s1, and an N-substrate 9 is prepared. In step s2, an N-clad layer 8, an N-active layer 7, a PN-junction 6, a P-clad layer 5, and a current diffusion layer 4 are sequentially formed on the N-substrate 9 by epitaxial growth. In step s3, as shown in FIG. 1, the light emitting portion 1 and the convex portion 2 are formed by mesa etching on the current diffusion layer 4.
[0025]
Next, in step s4, an insulating film is formed, and in step s5, an electrode wiring is formed. In these steps, a mask is used in photolithographic processing, etching is performed to remove unnecessary portions, and a necessary insulating film is formed, a contact region with an electrode is formed, and a metal film is formed. In these steps, the intersection of the projections 2 in FIG. 1 indicates the origin of the alignment mark, and the mask used in the subsequent process performs relative positioning with respect to the intersection of the projections 2. Alignment marks made of a metal film that are not required in a later step are removed at the same time as the etching process.
[0026]
When the formation of the insulating film in step s4 and the formation of the electrode wiring in step s5 are completed and the LED array element 11 is formed, a wafer test is performed in step s6. In the wafer test, an electrical characteristic test is performed on each of the LED array elements 11, and identification ink is applied to the LED array elements 11 determined to be defective. In the present embodiment, the convex portion formed by the mesa etching is provided along the dicing line 12, so that the adhered ink is prevented from flowing into the adjacent chip area of the LED array element 11 determined to be a good product. can do. When the wafer test is completed, dicing for cutting the dicing region 3 is performed in step s7. By the dicing step, at least the alignment mark formed of the metal film has been removed by etching, so that it is possible to avoid a problem that the sharpness of the dicing blade is deteriorated. When the dicing in step s7 ends, the individual LED array elements 11 are separated from the AlGaInP wafer 10 in step s8, and the basic manufacturing process of the LED array elements 11 ends.
[0027]
FIG. 3 shows a state after the completion of the electrode forming photolithographic processing in the electrode wiring forming step of step s5 in FIG. As shown in FIG. 3A, an electrode pattern 22 is formed of a photoresist for each light emitting unit 1 using the alignment mark 20 at the intersection of the projections 2 in FIG. 1 as an origin which is a reference for alignment. 3B, an alignment mark 23 made of a photoresist is formed near the alignment mark 20 at the intersection of the projections 2. As shown in FIG. The alignment mark 20 does not include a metal film because it is an intersection of the convex portions 2 formed by the mesa etching of the current diffusion layer. The alignment mark 23 has a shape capable of vertical and horizontal alignment with respect to the alignment mark 20 and has a line width w of not more than twice the side etch amount a in the next etching step (w ≦ 2a). Design to be. Since fluctuations in etching can be considered, it is preferable to design w <2a. Since the alignment mark 23 is a photomask-like pattern, the metal film remains on the AlGaInP wafer 10 together with the photoresist in this shape. However, since the metal film is subjected to side etching of a from both sides in the etching process, the alignment mark of the metal film having the line width w is removed.
[0028]
FIG. 3C shows an example of the alignment mark 24 designed to have a large width. The alignment mark of the metal film covered with such a large photoresist remains after the etching as shown as the alignment mark 25 in FIG. Although the width of the alignment mark 25 is reduced by the side etch amount of a from the photoresist alignment mark 24, the alignment mark 25 remains on the dicing line 12 and can be clogged with the blade when cut by the blade in the dicing process. There is.
[0029]
FIG. 4 shows a state after the completion of the photolithographic processing shown in FIG. 3A and a state after an etching step is further performed. FIG. 4A shows a state as viewed in plan, and FIG. 4B shows a state as viewed from section line BB in FIG. 4A. The electrode pattern 22 that contacts the light emitting unit 1 is formed, and many recesses are formed on the surface of the LED array element 11. In such a state, when a wafer test is performed in step s6 of FIG. 2 and ink is applied as a bad mark to the LED array element 11 determined to be defective, the ink is in a state of being very easy to flow.
[0030]
FIG. 5 shows a state in which a bad mark 30 is displayed with ink on the LED array element 11 determined to be defective. FIG. 5A shows a case in which the LED array element 11 is formed on a semiconductor substrate by a conventional method, and shows that the tip 30 a of the ink applied as the bad mark 30 may spread to the adjacent LED array element 11. Show. As shown in FIG. 5B, if the convex portion 2 is formed on the dicing line 12, the convex portion 2 blocks the flow of the ink, and the tip 30b of the bad mark 30 is determined to be an adjacent good product. It is possible to prevent the ink from spreading on the chip of the LED array element 11.
[0031]
In the embodiment described above, the LED array element 11 as the semiconductor light emitting element is formed on the AlGaInP wafer 10 as the quaternary wafer of the compound semiconductor. The present invention can be similarly applied to the case of forming a semiconductor integrated circuit element or the like.
[0032]
【The invention's effect】
As described above, according to the present invention, the alignment mark of the metal film is removed by the etching process before the dicing process, so that the characteristics of the semiconductor element and the dicing process are not affected. In the semiconductor element manufacturing process, the mask alignment and the etching process are repeated in a plurality of photolithographic steps, so that the alignment marks formed in the preceding step are used in the subsequent steps to perform the mask alignment, etc. Since the alignment marks that are not required in the subsequent steps are removed by the etching process, problems caused by the alignment marks can be avoided without providing a dedicated step.
[0033]
Further, according to the present invention, since the alignment mark is formed on the dicing line, it is not necessary to secure the surface of the semiconductor wafer on which the semiconductor element is formed for forming the alignment mark, and it is possible to effectively use the semiconductor element for improving the characteristics of the semiconductor element. it can. Even if the alignment mark is formed on the dicing line, the alignment mark is removed before the dicing step, so that the problem of dicing due to the presence of the alignment mark can be prevented.
[0035]
Further, according to the present invention, since the alignment mark is formed as a protrusion on the dicing line, the alignment mark can be distinguished well, and positioning using the alignment mark can be performed accurately. The alignment mark can be removed in a dicing process.
[0036]
Further, according to the present invention, the alignment mark formed as a convex portion on the dicing line is removed after the wafer test process. Therefore, even if the ink is attached to the semiconductor element determined to be defective in the wafer test, the ink is not removed. Blocked by the alignment mark, it can be prevented from flowing into a chip region of a semiconductor element determined to be non-defective in an adjacent wafer test, and a decrease in yield can be avoided.
[0037]
Further, according to the present invention, when manufacturing a semiconductor light emitting device, the photolithography process and the wafer test process can be executed with high accuracy by effectively utilizing the alignment marks, and the problem does not occur in the dicing process. The alignment mark can be removed before the dicing step.
[Brief description of the drawings]
FIGS. 1A and 1B are a plan view and a cross-sectional view illustrating a state in which a projection 2 serving as an alignment mark is formed according to an embodiment of the present invention.
FIG. 2 is a flowchart schematically showing an overall semiconductor device manufacturing process including the formation of the alignment mark of FIG. 1;
FIG. 3 is a partial plan view showing a limitation on a width in a case where a metal film is used as an alignment mark in an electrode forming step in which an intersection of a convex portion 2 in FIG. 1 is used as an alignment mark 20;
4A and 4B are a plan view and a cross-sectional view showing a state where an etching process has been completed from the state shown in FIG.
FIG. 5 is a partial plan view showing a state in which ink as a bad mark 30 is applied to a chip determined to be defective in a wafer test by a conventional manufacturing method and the present embodiment.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Light emitting part 2 Convex part 3 Dicing area 4 Current diffusion layer 5 P-cladding layer 6 PN junction part 7 N-active layer 8 N-cladding layer 9 N-substrate 10 AlGaInP wafer 11 LED array element 12 Dicing lines 20, 23, 24, 25 Alignment mark 22 Electrode pattern 30 Bad mark

Claims (5)

In a method for generating a semiconductor element, which simultaneously generates a plurality of semiconductor elements on a semiconductor wafer through a plurality of processes,
A process in which a subsequent process uses an alignment mark used for alignment in an electrode wiring forming process in the preceding process and after the subsequent process and before a dicing process for dividing a semiconductor wafer into semiconductor elements. A metal film for electrode wiring is formed on a semiconductor wafer so that the line width is less than twice the amount of side etching in the etching process included therein.
A method of manufacturing a semiconductor device, comprising: removing an alignment mark by a metal film from a semiconductor wafer in the etching process. 2. The method according to claim 1, wherein the alignment mark is formed on a dicing line that is cut to divide the semiconductor wafer in the dicing step. Part of the alignment mark used for alignment in the subsequent process is formed on a dicing line so as to be a convex portion by the mesa etching of the preceding process, and is removed in the dicing process. 2. The method for manufacturing a semiconductor device according to claim 1, wherein: 4. The semiconductor device according to claim 3, wherein before the dicing step, a characteristic test is performed on each semiconductor element, and a wafer test step of attaching identification ink to the semiconductor element determined to be defective is performed. Device manufacturing method. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor light emitting device.

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