JP2000106509A - Compensation device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize the compensation device that compensates a DC fluctuation and offset component caused at a differential output of an operational amplifier or the like with a simpler circuit configuration. SOLUTION: An RDX output signal (a) and an RDY output signal (b) being differential outputs are passed through 1st and 2nd low PASS filters 21a, 21b respectively to obtain DC fluctuation and offset component signals (c), (d) from which high frequency components are eliminated. A first (second) adder 22a (22b) sums a DC fluctuation and offset component d (c) resulting from eliminating a high frequency component from the RDY, RDX output signal b(a) and the RDX, RDY output signal a(b) respectively to correct the DC fluctuation and offset component of the RDX, RDY output signals a, b. Thus, the device that compensates the DC fluctuation and offset component superimposed on a signal waveform is provided at a low cost with a simpler configuration.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiver-related means for limiting or suppressing noise or interference in transmission of pulse technology and electronic communication technology in basic electronic circuits, and in particular, to a small signal. The present invention relates to a compensating device for compensating for a DC fluctuation and an offset component superimposed on a signal waveform in a device for reading information by amplifying a signal with a differential amplifier.

[0002]

2. Description of the Related Art Conventionally, as a compensator for a DC fluctuation and an offset component superimposed on a signal waveform, US Pat.
No. 4398 (corresponding to Japanese Patent Publication No. 8-16964) is known.

FIG. 5 is a block diagram showing a configuration of a data signal disturbance reduction circuit described in Japanese Patent Publication No. 8-16964. In the figure, reference numeral 110 denotes data and an additive disturbance superimposed on the data. A positive envelope detector for detecting a positive envelope waveform from the input signal I including
120 is a negative envelope detector for detecting a negative envelope waveform from the input signal I, 130 is an adder for adding the outputs of the positive envelope detector 110 and the negative envelope detector 120, 140
Is a buffer connected between the positive envelope detector 110 and the negative envelope detector 120, 150 reduces the correlation residual value in the primary estimate of the additive disturbance from the output signal of the adder 130 160, an attenuator for outputting an estimated disturbance signal from the output signal of the adaptive filter 150, 170, a delay circuit for delaying the input signal I for a predetermined period and outputting the same, and 180, a delay by the delay circuit 170. This block adds / subtracts the estimated disturbance signal from the attenuator 160 with respect to the minute, and outputs an output signal O from which the additive disturbance has been removed.

The data signal disturbance reduction circuit detects the envelope waveform of the reproduced output (input signal I) by the envelope detectors 110 and 120, and calculates the center voltage by the adder 130 from the output envelope signal.
Thereafter, the center voltage waveform is smoothed by the non-linear adaptive filter 150, and the center voltage waveform obtained as described above is subtracted from the reproduced output (input signal I) by the delay circuit 170 by the addition block 180, thereby obtaining the output. It compensates for DC fluctuations and offset components in the signal O. However, the above adaptive filter 1
In the case of 50, a characteristic is provided in which smoothing is not performed on a change in the center voltage waveform due to a DC fluctuation.

[0005]

However, in the above conventional configuration, the envelope detectors (110, 12)
0), attenuator (160), adaptive filter (15)
0), signal inverter (140), delay element (17
0), adders (130, 180) and the like are required, and there are problems that the circuit components constituting the electric circuit are complicated, and that the cost of the apparatus is increased. SUMMARY OF THE INVENTION The present invention provides a compensator capable of compensating for a DC fluctuation and an offset component occurring in a differential output with a simpler circuit configuration.

[0006]

According to a first aspect of the present invention, there is provided a compensating apparatus comprising: a preamplifier for outputting a differential signal from a minute signal; and a differential amplifier for differentially amplifying the differential signal. A compensator that compensates for DC fluctuation and offset components of the differential signal output from the preamplifier, and removes high-frequency components from the positive-phase differential signal output from the preamplifier. A first low-pass filter for extracting a positive-phase DC fluctuation and offset component signal, and removing a high-frequency component from the negative-phase differential signal output from the preamplifier, thereby removing the negative-phase DC fluctuation and offset. A second low-pass filter for extracting a component signal; and a negative-phase DC fluctuation and offset component extracted by the second low-pass filter on the positive-phase differential signal output from the preamplifier. The first to add the signal
And a second adder for adding the positive-phase DC fluctuation and offset component signals extracted by the second low-pass filter to the negative-phase differential signal output from the preamplifier. It is characterized by having.

According to a second aspect of the present invention, there is provided a compensator according to the first aspect, further comprising a second compensator connected between the first low-pass filter and the second adder. 1 switch, a second switch connected between the second low-pass filter and the first adder, and a differential signal of the preamplifier or an output signal of the differential amplifier. And a control circuit for detecting a period during which the DC fluctuation is larger than the reference value and turning on the first and second switches only during the DC fluctuation detection period.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1 An embodiment of the present invention described in claim 1 of the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram illustrating a configuration of an information reading device including a compensating device according to Embodiment 1 of the present invention. The information reading apparatus shown in FIG. 1 includes a preamplifier 1 that outputs a minute signal containing predetermined information as a differential signal, and a differential signal from the preamplifier 1 is amplified by an internal differential amplifier 31. A compensator 2 according to the present embodiment, which is connected between the preamplifier 1 and the data channel 3 to generate a reproduced signal and read information.
This is a device for removing DC fluctuations and offset components of the differential signal output from the.

The preamplifier 1 receives a minute signal through an input terminal 11, outputs a positive-phase differential signal from a first output terminal 12a, and outputs a negative-phase differential signal from a second output terminal 12b. Outputs a motion signal. The data channel 3 is the first
The input terminal 32a receives the input of the positive-phase differential signal from the preamplifier 1, the second input terminal 32b receives the input of the negative-phase differential signal from the preamplifier 1, and the output terminal 22 Outputs a reproduced signal based on these differential signals. The compensator 2 has its signal input side connected to the first and second output terminals 12a and 12b of the preamplifier 1,
The signal output side is connected to the first and second input terminals 32a and 32b of the data channel 3.

The compensator 2 includes a first low-pass filter 21a,
It includes a second low-pass filter 21b, a first adder 22a, and a second adder 22b.

The first low-pass filter 21a includes a preamplifier 1
Receives the input of the RDX output signal a, which is a positive-phase differential signal, removes the information signal of the high-frequency component in the RDX output signal a and outputs the DC fluctuation and offset component signal c.

The second low-pass filter 21b includes the preamplifier 1
Receives the input of the RDY output signal b, which is a differential signal of the opposite phase, removes the information signal of the high frequency component in the RDY output signal b and outputs the DC fluctuation and offset component signal d.

The first adder 22a converts the DC fluctuation and offset component signal output from the second low-pass filter 21b into the RDX output signal a, which is a positive-phase differential signal from the preamplifier 1. d is added. Then, the first adder 22a outputs the positive-phase differential signal e in which the DC fluctuation and the offset component included in the RDX output signal a have been canceled to the first input terminal 32 of the data channel 3.
output to a.

The second adder 22b provides a DC fluctuation and offset component signal output from the first low-pass filter 21a to the RDY output signal b, which is a differential signal of the opposite phase from the preamplifier 1. c is added. Then, the second adder 22b outputs the negative-phase differential signal f in which the DC fluctuation and the offset component included in the RDY output signal b have been canceled to the second input terminal 32 of the data channel 3.
b.

Next, the operation of the compensator 2 having the above configuration will be described. 2A and 2B show signal waveforms of various parts in the information reading apparatus shown in FIG. 1. FIG. 2A shows the waveform of the RDX output signal a of the preamplifier 1, and FIG. The waveform of the RDY output signal b of the amplifier 1 is shown in FIG.
Is the waveform of the output signal c of the first low-pass filter 21a,
FIG. 4D shows the waveform of the output signal d of the second low-pass filter 21b, FIG. 4E shows the waveform of the output signal e of the first adder 22a, and FIG. The waveform of the output signal f of the second adder 22b is shown in FIG. 3 (g), and the waveform of the output signal g of the differential amplifier 5 provided in the data channel 3 is shown in FIG.

When a small signal containing information is input to the preamplifier 1 via the input terminal 11, the preamplifier 1 outputs positive- and negative-phase differential signals to the first and second output terminals 12a. ,
Output from 12b. In this case, the first output terminal 12a
Output signal a which is a positive-phase differential signal output from
Contains an abrupt DC fluctuation component a '(see FIG. 2).
(a)). Further, the RDY output signal b, which is a differential signal of the opposite phase output from the second output terminal 12b, also includes an abrupt DC fluctuation component b '(FIG. 2 (b)). Note that this RDX
The output signal “a” and the RDY output signal “b” have the same amplitude, but have opposite phases, DC fluctuations and offset components.

The RDX output signal a output from the first output terminal 12a is sent to the first adder 22a and also to the first low-pass filter 21a. The RDY output signal b output from the second output terminal 12b is sent to the second adder 22b,
To the low-pass filter 21b.

In the first low-pass filter 2a, when the RDX output signal a is input, the information signal of the high-frequency component is removed and the DC fluctuation of the RDX output signal a and the offset component signal c are extracted ( FIG. 2 (c)). Further, when the RDY output signal b is input, the second low-pass filter 2b removes the information signal of the high frequency component and extracts the DC fluctuation of the RDY output signal b and the offset component signal d (FIG. 2 (d)
). The DC fluctuation and offset component signal c and the DC fluctuation and offset component signal d have the same amplitude,
The phase, the DC fluctuation, and the offset are reverse signals.

The R extracted by the first low-pass filter 2a
DC fluctuation of DX output signal a and offset component signal c
Is input to the second adder 22b. The DC fluctuation and offset component signal d of the RDY output signal b extracted by the second low-pass filter 2b are input to the first adder 22a.

In the first adder 22a, the DC fluctuation and offset component signal d is added to the RDX output signal a which is a positive-phase differential signal output from the first output terminal 12a of the preamplifier 1. Is added. This DC fluctuation and offset component signal d is in phase with the RDX output signal a,
Since the DC fluctuation and the offset component are opposite, the output of the first adder 22a becomes the output signal e in which the DC fluctuation and the offset component included in the RDX output signal a are canceled (FIG. 2 (e)). ).

In the second adder 22b, the DC fluctuation and offset component signal c is applied to the RDY output signal b, which is a negative-phase differential signal output from the second output terminal 12b of the preamplifier 1. Is added. This DC fluctuation and offset component signal c is in phase with the RDY output signal b,
Since the DC fluctuation and the offset component are opposite, the output of the second adder 22b becomes the output signal f in which the DC fluctuation and the offset component included in the RDY output signal b have been canceled (FIG. 2 (f)). ).

Next, the output signal e of the first adder 22a
Is input to the first input terminal 32a of the data channel 3, and the output signal f of the second adder 22b is input to the second input terminal 32b of the data channel 3. The data channel 3 outputs a reproduced signal g corresponding to the amplification factor of the differential amplifier 31 provided therein (FIG. 2 (g)), and information is read from the reproduced signal g. Since the output signals e and f input to the data channel 3 do not include the DC fluctuation and the offset component, the reproduced signal g has the DC fluctuation and the offset component removed, and the detection error of the signal occurs. Can be difficult.

As described above, according to the compensator 2 according to the first embodiment, the low-pass filters 21a and 21b use the fact that the differential signals of the preamplifier 1 are inverted with respect to each other. The DC fluctuation and offset component c (d) are extracted from the differential signal RDX output signal a (RDY output signal b), and the DC fluctuation and offset component signal c (d) are subtracted by adders 22a and 22b. The DC fluctuation and the offset component are removed from the differential signal in addition to the dynamic signal RDY output signal b (RDX output signal a). Therefore, in the correction device 2 according to the first embodiment, utilizing the fact that the differential signals of the preamplifier 1 are opposite to each other,
With a simple circuit configuration including the low-pass filter and the adder, there is an effect that the DC fluctuation and the offset component superimposed on the signal waveform can be compensated.

Embodiment 2 Next, an embodiment of the invention described in claim 2 of the present invention will be described with reference to FIGS. FIG. 3 is a block diagram illustrating a configuration of an information reading device including a compensating device according to Embodiment 2 of the present invention. The same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

In the compensator 20 according to the second embodiment,
The difference from the first embodiment is that a comparator 24 for detecting a DC fluctuation of a signal waveform and a first analog switch 23a connected between a first low-pass filter 21a and a second adder 22b. And a second analog switch 23b connected between the second low-pass filter 21b and the first adder 22a.

The comparator 24 determines that the DC fluctuation of the output signal h of the differential amplifier 31 provided in the data channel 3 is larger than the reference voltage Vref of the comparator 24 by Tc.
Is detected.

The first analog switch 23a is turned on only during the period of Tc to output the output signal c of the first low-pass filter 21a to the second adder 22b. The switch 23b is also turned on only during the period of Tc to output the output signal d of the second low-pass filter 21b to the first adder 22a.

Next, the operation of the compensator having the above configuration will be described. FIG. 4 shows signal waveforms at various parts in the information reading apparatus shown in FIG. 3, and FIG. 4H shows an output signal h (including a DC fluctuation and an offset component) of the differential amplifier 31 in the data channel 3. (I) is a waveform of the output signal i of the comparator 24, and (j) of FIG.
FIG. 7 (k) shows the waveform of the output signal k of the second analog switch 23b, and FIG. 7 (l) shows the waveform of the output signal k of the first analog switch 23a. The waveform of the output signal 1 is shown in FIG.
4 (b) shows the waveform of the output signal m of the differential amplifier 5 in the data channel 3 (excluding the DC fluctuation and the offset component).

In the second embodiment, first, first and second
Are turned off, and the output signals c and d are not output from the first and second low-pass filters 21a and 21b to the first and second adders 22a and 22b. Therefore, RDX which is the differential signal of the preamplifier 1
The output signal “a” and the RDY output signal “b” pass through the first and second adders 22 a and 22 b and are directly input to the differential amplifier 31 of the data channel 3. At this time, since the RDX output signal a and the RDY output signal b include a DC fluctuation and an offset component, the output signal h of the differential amplifier 31
Contains the DC fluctuation h '(FIG. 4 (h)).

The output signal h is input to the comparator 24, and the comparator 24 detects a period Tc in which the DC fluctuation h 'of the output signal h is larger than the reference voltage Vref of the comparator 24. Then, the comparator 24 outputs an output signal i having a pulse waveform of High from the output terminal 34 for the period Tc (FIG. 4 (i)). The output signal i from the comparator 24 is the first and second signals
Are input to the analog switches 23a and 23b of the
The second analog switches 23a and 23b are turned on during the period Tc. Then, the first analog switch 2
3a, the DC fluctuation and offset component signal c extracted from the RDX output signal a by the first low-pass filter 21a output signal j for the period Tc (FIG. 4 (j)).
) Is sent to the second adder 22b. At the same time, the second low-pass filter 21 is output from the second analog switch 23b.
In the DC fluctuation and offset component signal d extracted from the RDY output signal b at b, the output signal k (FIG. 4 (k)) output for the period Tc is sent to the first adder 22a.

In the first adder 22a, the output signal k output for the period Tc in the DC fluctuation and offset component signal d is added to the RDX output signal a output from the preamplifier 1. Then, the first adder 22a calculates
In the RDX output signal a, an output signal 1 from which the DC fluctuation and the offset component have been removed for the period Tc is output (FIG. 4 (l)).

In the second adder 22b, the output signal j output from the preamplifier 1 for the period Tc in the DC fluctuation and offset component signal c is output from the RD output from the preamplifier 1.
It is added to the Y output signal b. Then, the second adder 22
b outputs an output signal m in which the DC fluctuation and the offset component have been removed from the RDY output signal b for the period Tc (FIG. 4 (m)).

The first and second adders 22a, 22a,
The output signals 1 and m output from 22b are input to the differential amplifier 31 of the data channel 3 via the first and second input terminals 32a and 32b, and the differential amplifier 31 outputs the output signals 1 and m in accordance with the amplification factor. The reproduction signal n is output (FIG. 4 (n)). The reproduced signal n is obtained by removing the DC fluctuation and the offset component during the period Tc in which the error occurs in the reproduced signal h. In this embodiment, since the comparator 24 is provided at the output of the input differential amplifier 31 of the data channel 3, the preamplifier 1 is provided with a signal delay element (not shown) in this case. The first and second adders 22a,
The combination at 22b is set to be synchronized.

As described above, according to the compensator according to the second embodiment, the DC fluctuation and the offset component are performed by the comparator 24 such that the reproduced signal h of the differential amplifier 31 provided in the data channel 3 causes an error. In response to the detection signal i, the first and second analog switches 23a and 23b provided at the subsequent stage of the first and second low-pass filters 21a and 21b are turned on, and the first and second analog switches 23a and 23b are turned on. The output signals c and d of the low-pass filters 21a and 21b are applied to first and second adders 22a and 22b. Therefore, in the correction device 20 according to the second embodiment, the differential signal a, b is compensated by operating the device only when the DC fluctuation and the offset component cause an error in the reproduction signal h. In this case, the device 20 is not operated, so that when it is not necessary to correct the differential signals a and b, the correction is not excessively performed and the reproduced signal waveform is not distorted. There is an effect that can be.

In the second embodiment, the description has been made of the configuration in which the comparator 24 for detecting the DC fluctuation is connected to the output of the differential amplifier 31 of the data channel 3. However, the first output terminal 12a of the preamplifier 1 is described. Alternatively, the present invention can be similarly carried out when connected to any output of the second output terminal 12b. In this case, it is not necessary to provide a signal delay element for synchronizing the signals synthesized by the first and second adders 22a and 22b as described above.

[0036]

As described above, the compensating device according to claim 1 of the present invention utilizes the fact that the differential signals of the preamplifier are inverted with respect to each other, and the first and second low-pass filtering are performed. The DC fluctuation and the offset component are extracted from one differential signal by the adder, the DC fluctuation and the offset component signal are added to the other differential signal by the first and second adders, and the DC fluctuation and the offset component are extracted from the differential signal. It is configured to remove the offset component. Therefore, this compensator utilizes the fact that the differential signals of the preamplifier are inverted with respect to each other, and has a simple circuit configuration including a low-pass filter and an adder, so that the DC fluctuation superimposed on the signal waveform is obtained. And the compensation of the offset component can be performed.

Further, in the compensator according to the second aspect of the present invention, the comparator detects a period in which the DC fluctuation and the offset component are performed so as to cause an error in the reproduced signal of the differential amplifier provided in the data channel. In response to the signal, the first and second analog switches provided at the subsequent stage of the first and second low-pass filters are turned on to output the output signals of the first and second low-pass filters to the first and second low-pass filters. Are added to the adder. Therefore, in this correction device, the device is operated only when the DC fluctuation and the offset component are performed so as to cause an error in the reproduced signal, and the differential signal is compensated.In other cases, the device is not operated, When the correction is not required, there is an effect that the correction is not excessively performed and the reproduced signal waveform is not distorted.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a data reading device including a compensation device according to Embodiment 1 of the present invention.

FIG. 2 is a signal waveform diagram of each part of the data reading device shown in FIG.

FIG. 3 is a block diagram illustrating a configuration of a data reading device including a compensation device according to a second embodiment of the present invention.

FIG. 4 is a signal waveform diagram of each part of the data reading device shown in FIG. 3;

FIG. 5 is a block diagram illustrating a configuration of a conventional compensation device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Preamplifier 11 Input terminal of a preamplifier 12a First output terminal 12b Second output terminal 2,20 Compensator 21a First low-pass filter 21b Second low-pass filter 22a First adder 22b Second adder 23a First analog switch 23b Second analog switch 24 Comparator 3 Data channel 31 Differential amplifier 32a First input terminal 32b Second input terminal 33 Output terminal 34 Comparator output terminal a RDX output signal b RDY output signal c DC fluctuation and offset component signal from which high frequency component of RDX output a is removed d DC fluctuation and offset component signal from which high frequency component of RDY output b is removed e Output signal f of first adder 3a after correction Output signal of second adder 3b after correction g Output signal of differential amplifier 31 h Differential amplification before correction 31 output signal i comparator output signal j output signal of first analog switch 23a k output signal of second analog switch 23b l output signal of adder 22a after correction m output signal of adder 22b after correction n Output signal of differential amplifier 31 after

 ──────────────────────────────────────────────────の Continued from the front page F term (reference) 5J066 AA01 AA12 AA22 AA51 CA12 CA13 CA92 FA08 FA09 FA18 HA40 KA02 KA17 KA26 KA42 MA08 MA11 MA20 ND05 PD01 SA01 TA01 TA06 5J091 AA01 AA12 AA22 AA51 CA12 CA13 CA92 FA08 FA09 KA26 KA42 MA11 MA20 SA01 TA01 TA06

Claims (2)

[Claims] 1. A pre-amplifier for outputting a differential signal from a small signal and a differential amplifier for differentially amplifying the differential signal, the DC of the differential signal output from the pre-amplifier being connected. A compensating device for compensating fluctuation and offset components, comprising: a first device for removing a high-frequency component from a positive-phase differential signal output from the preamplifier and extracting a positive-phase DC fluctuation and offset component signal. A low-pass filter, a second low-pass filter that removes a high-frequency component from the negative-phase differential signal output from the preamplifier and extracts a negative-phase DC fluctuation and offset component signal, A first adder for adding the negative-phase DC fluctuation and offset component signals extracted by the second low-pass filter to the positive-phase differential signal output from the preamplifier; The above-mentioned second differential signal is output Compensating apparatus characterized by comprising a second adder for adding the direct current variation and offset component signal of a positive phase extracted by the low pass filter. 2. The compensator according to claim 1, wherein: a first switch connected between the first low-pass filter and the second adder; and a second low-pass filter. A second switch connected between the adder and the first adder, and a period in which the DC fluctuation in the differential signal of the preamplifier or the output signal of the differential amplifier is larger than a reference value. And a control circuit for detecting and turning on the first and second switches only during the DC fluctuation detection period.