JP2000101060A - Solid-state image sensing element and control method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To raise the max. storing capacity of a photoelectric conversion element and prevent the smear. SOLUTION: This solid-state image sensing element comprises a substrate having a photoelectric conversion element 21 and a charge transfer line 22 and a power source Vod for applying a specified voltage to the substrate to remove the electric charge in the substrate and the control method thereof comprises step (a) of applying a first d-c bias voltage Vod1 to the substrate, converting a received light to an electric charge and storing the charge in the photoelectric conversion element, step (b) of reading the charge stored in the photoelectric conversion element onto the charge transfer line, and step (c) of applying a second d-c bias voltage Vod2 higher than the first d-c bias voltage to the substrate and transferring the charge on the charge transfer line.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device, and more particularly, to a technique for reading and transferring electric charges.

[0002]

2. Description of the Related Art FIG. 2 is a plan view of a solid-state imaging device.

The photoelectric conversion elements 21 are, for example, photodiodes, and are arranged in a large number in a two-dimensional matrix.
The photodiode 21 is, for example, 492 in the vertical direction.
And 660 in the horizontal direction. The photodiode matrix configured as described above forms an imaging surface.

[0004] The photodiode 21 converts received light into electric charge. The vertical charge transfer path (VCCD) 22 reads out charges from the photodiode 21 and transfers the charges in the vertical direction. Specifically, the charge is transferred from top to bottom in accordance with the drive pulse φV.

[0005] A horizontal charge transfer path (HCCD) 23 receives charges from the vertical charge transfer path 22 and transfers the charges in the horizontal direction. Specifically, according to the drive pulse φH,
Transfers charge from right to left.

The amplifier 24 receives charges from the horizontal charge transfer path 23 and outputs a voltage corresponding to the charge amount. An image signal is output from the amplifier 24. Each photodiode 21 arranged two-dimensionally corresponds to a pixel constituting an image.

[0007]

SUMMARY OF THE INVENTION Photodiode 21
Can receive light from outside. Vertical charge transfer path 2
2 and the horizontal charge transfer path 23 are covered with a light shielding film for shielding external light. When receiving light from outside,
Electric charges are generated only in the photodiode 21.

However, when receiving strong light, charges generated in the photodiode 21 may leak to the vertical charge transfer path 22. This phenomenon is called smear. When smear occurs, charges serving as noise leak to the vertical transfer path 22, thereby causing image deterioration.

It is an object of the present invention to provide a solid-state image pickup device capable of preventing image deterioration and a control method thereof.

[0010]

According to one aspect of the present invention, a substrate having a photoelectric conversion element and a charge transfer path, and a power supply for applying a predetermined voltage to the substrate to remove charges in the substrate are provided. A method for controlling a solid-state imaging device comprising:
(A) applying a first DC bias voltage to a substrate, converting received light into electric charges, and accumulating the electric charges in a photoelectric conversion element;
(B) reading the charge accumulated in the photoelectric conversion element to a charge transfer path; and (c) applying a second DC bias voltage higher than the first DC bias voltage to the substrate,
Transferring a charge on the charge transfer path.

A first or second DC bias voltage is applied to the substrate. The second DC bias voltage is higher than the first DC bias voltage. When accumulating charges in the photoelectric conversion element, a first DC bias voltage is applied to the substrate to increase the maximum possible storage capacity of the photoelectric conversion element. The charge stored in the photoelectric conversion element is read out on a charge transfer path. When transferring the charge on the charge transfer path, a second DC bias voltage is applied to the substrate to prevent charge leakage from the photoelectric conversion element to the charge transfer path. That is, smear can be prevented.

[0012]

FIG. 1 shows a solid-state imaging device according to an embodiment of the present invention, and is a cross-sectional view taken along line II of the solid-state imaging device shown in FIG.

A p-type well 2 is formed on the surface of an n-type silicon substrate 1. An n-type region 3 and a vertical charge transfer path 2 constituting a photodiode 21 are formed on the surface of the p-type well 2.
An n-type region 4 constituting 2 is formed. Between the n-type region 3 and the n-type region 4 to the left of the n-type region 3, ap ⁺ -type region 5 constituting a channel stop region is formed.

N-type region 4 constituting vertical charge transfer path 22
A shift gate electrode 7 is formed on the substrate with an insulating film 6 interposed therebetween. The shift gate electrode 7 has a shift gate signal S
G is supplied. When the positive potential shift gate signal SG is supplied, the electric charge accumulated in the photodiode 21 becomes
The data is read to the right vertical charge transfer path 22.

The n-type substrate 1 is connected to a positive variable power supply Vod. The p-type well 2 is connected to the ground.

The incident light 8 enters the photodiode 21. Charges accumulate in the n-type region 3 by light irradiation. If the charges are excessively accumulated in the n-type region 3, the electrons 9 overflow from the n-type region 3 to the n-type substrate 1. This structure is called an overflow drain structure.

The graph shown on the right side of FIG.
The potential corresponding to d is shown. The horizontal axis indicates the potential, and the vertical axis indicates the position in the depth direction (vertical direction) of the solid-state imaging device.

When the magnitude of the substrate voltage Vod is changed, the saturation charge of the photodiode 21 is changed. The case where the substrate voltage Vod is controlled to the low voltage Vod1 and the case where the substrate voltage Vod is controlled to the high voltage Vod2 are shown. Low substrate voltage Vod1
, The saturated charge amount Q1 is large, and at a high substrate voltage Vod2, the saturated charge amount Q2 is small.

The upper end of the p-type well 2 is at 0V. A peak of a potential barrier for electrons is formed near the center of the p-type well 2 in the depth direction. Low substrate voltage Vo
At a substrate voltage Vod2 higher than d1, the position of the potential barrier moves in the direction (upward) PV of the substrate surface.

When the substrate voltage Vod1 is low, it is difficult to discharge the charge accumulated in the photodiode 21 to the n-type substrate 1, but when the substrate voltage Vod2 is high, a part of the charge accumulated in the photodiode 21 is transferred to the n-type substrate 1. Can be swept to one.

By applying a high substrate voltage Vod2 to the n-type substrate 1, the charge accumulated in the photodiode 21 is swept to the n-type substrate 1 while leaving a predetermined amount, and the charge is transferred from the photodiode 21 to the vertical charge transfer path 22. Can be prevented from leaking. That is, smear can be prevented.

However, the necessary charges are transferred to the photodiode 2
1 is accumulated in the photodiode 1, it is desirable that the saturated charge amount of the photodiode 21 is large.
1 must be applied. That is, the substrate voltage Vod is changed according to the operation state of the solid-state imaging device. next,
The control method will be described.

FIG. 3 is a timing chart of signals for controlling the solid-state imaging device. The vertical charge transfer path drive pulse φV is a pulse for driving the vertical charge transfer path 22, as shown in FIG. The horizontal charge transfer path drive pulse φH is a pulse for driving the horizontal charge transfer path 23, as shown in FIG.

The shift gate pulse SG is a pulse supplied to the shift gate 7 shown in FIG. Substrate voltage Vo
d is a voltage applied to the n-type substrate 1 shown in FIG.
The bias voltage of the substrate voltage Vod is controlled to the low voltage Vod1 or the high voltage Vod2. The voltage obtained by adding the electronic shutter pulse SH to the bias voltage becomes the substrate voltage Vod.

The electronic shutter pulse SH is a pulse for generating a high substrate voltage Vod3, and has a role of sweeping all charges stored in the photodiode to the n-type substrate 1.

First, in the preparation period T1, the solid-state imaging device is initialized. Hereinafter, a specific operation will be described. The shift gate pulse SG is applied to the shift gate 7, and unnecessary charges stored in the photodiode 21 are read out to the vertical charge transfer path 22. The drive pulse φV is supplied to the vertical charge transfer path 22, and the vertical charge transfer path 22 transfers charges in the vertical direction. The drive pulse φH is supplied to the horizontal charge transfer path 23 (FIG. 2), and the horizontal charge transfer path 23 transfers the charge received from the vertical charge transfer path 22 in the horizontal direction and outputs the same to the outside. At this time, the substrate voltage Vod is the low voltage Vod1 (for example, 10 V).

Since unnecessary charges due to smear are removed in the subsequent period T2, even if smear is generated in the preparation period T1, the smear does not adversely affect. Therefore, the substrate voltage Vod in the preparation period T1 may be either the low voltage Vod1 or the high voltage Vod2.

Next, in the unnecessary charge removing period T2, unnecessary charges on the vertical and horizontal charge transfer paths 22 and 23 are removed.
Hereinafter, a specific operation will be described. The bias voltage of the substrate voltage Vod is changed to a high voltage Vod2 (for example, 14V). When a high substrate voltage Vod2 is applied, the potential barrier moves to the substrate surface side, and the photodiode 21
Can be prevented from leaking into the vertical charge transfer path 22. That is, smear can be prevented.

In FIG. 1, the photodiode 2
1, the depth of the n-type region 3 is about 3 to 4 μm,
The depth of the n-type region 4 constituting the vertical charge transfer path 22 is about 0.5 to 1 μm. Since the depth of the n-type region 4 is smaller than that of the n-type region 3, even if the substrate voltage Vod is changed, the vertical charge transfer path 22 is hardly affected.

In this period T2, the substrate voltage Vod
Is a voltage in which the electronic shutter pulse SH of a predetermined cycle is superimposed on the bias voltage Vod2. As a result, a pulse Vod3 of a predetermined cycle corresponding to the electronic shutter pulse SH appears in the substrate voltage Vod. The pulse voltage Vod3 is
For example, it is 20 to 30V.

When the pulse voltage Vod3 is applied, most of the electric charge stored in the photodiode 21 becomes n
It is swept out to the mold substrate 1 and the photodiode 21 is initialized.

The voltage Vod3 does not necessarily need to be composed of a plurality of pulses.
3 may be maintained. However, high voltage Vod
To apply 3 for a predetermined time, a large power supply is required.
On the other hand, the pulse Vod3 having a predetermined period can be easily realized by a small circuit by utilizing the charge / discharge characteristics of the capacitor.

Also in the unnecessary charge removing period T2, the driving pulses φV and φH are supplied, and the vertical and horizontal charge transfer paths 22 and 23 transfer unnecessary charges to the outside.

Next, in the charge accumulation period T3, the photodiode 21 performs photoelectric conversion by external light irradiation to generate and accumulate necessary charges. Charge accumulation period T3
Is the time from the last shutter pulse Vod3 of the plurality of shutter pulses Vod3 in the period T2 until the next shift gate pulse SG is supplied. The photodiode 21 is initialized by the last shutter pulse Vod3 and starts accumulating charges, and charges are read out to the vertical charge transfer path 22 by the next shift gate pulse SG to terminate the accumulation of charges.

In this period T3, the substrate voltage Vod is changed to the low voltage Vod1. By applying the low voltage Vod1 to the n-type substrate 1, the saturation charge of the photodiode 21 can be increased, and the dynamic range of the charge that can be stored can be widened.

The DC bias of the substrate voltage Vod is
Timing T5 for switching from od2 to low voltage Vod1
Is preferably after the last shutter pulse Vod3.

Next, in the charge reading period T4, the vertical charge transfer path 22 transfers the charge read from the photodiode 21. Specifically, drive pulses φV and φH are supplied, and the vertical and horizontal charge transfer paths 22 and 23 transfer charges. The amplifier 24 outputs a voltage corresponding to the amount of the transferred charges.

In this period T4, the bias voltage of the substrate voltage Vod is changed to a high voltage Vod2 (for example, 14V). By applying the high substrate voltage Vod2, it is possible to prevent the charge in the photodiode 21 from leaking to the vertical charge transfer path 22. That is, smear can be prevented.

The DC bias of the substrate voltage Vod is changed to the low voltage V
Timing T6 for Switching from od1 to High Voltage Vod2
Is not limited to after the shift gate pulse SG and may be before. The timing T6 is preferably immediately before or immediately after the shift gate pulse SG, and particularly preferably immediately after.

The substrate voltage Vod includes a pulse Vod3 (for example, 20 to 3) having a predetermined period in the bias voltage Vod2.
0V) appears. This pulse Vod3 initializes the photodiode 21 and prevents smear.

As described above, during the charge storage time T3, the charge storage capacity of the photodiode 21 is increased by setting the DC bias of the substrate voltage Vod to the low voltage Vod1. On the other hand, in the charge readout period T4, the DC bias of the substrate voltage Vod is set to the high voltage Vod2, thereby preventing the charge from leaking from the photodiode 21 to the vertical charge transfer path 22. That is, smear is prevented.

As a result, it is possible to increase the charge storage capacity of the photodiode 21 and prevent smear.

Further, it is desirable to set the DC bias of the substrate voltage Vod to the high voltage Vod2 also in the unnecessary charge removing period T2.

The timing T5 for switching the DC bias of the substrate voltage Vod from the high voltage Vod2 to the low voltage Vod1 may be before a plurality of shutter pulses Vod3 in the unnecessary charge removal period T2. That is, in the unnecessary charge removal period T2, the substrate voltage Vod is changed to the high voltage Vod2.
After removing unnecessary charges, the substrate voltage Vod is reduced to the low voltage Vod1. Thereafter, the shutter pulse Vod3 may be applied as the substrate voltage Vod in a state where the DC bias of the substrate voltage Vod is set to the low voltage Vod1.

Note that the DC bias voltage Vod2 in the unnecessary charge removal period T2 and the DC bias voltage Vod2 in the charge readout period T4 do not necessarily need to be the same. Both voltages may be voltages higher than the low bias voltage Vod1 in the charge accumulation period T2.

The solid-state imaging device according to this embodiment is suitable for capturing a still image. Although the present invention has been described with reference to the embodiments, the present invention is not limited to these embodiments. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0047]

As described above, according to the present invention,
When accumulating charges in the photoelectric conversion element, a first DC bias voltage is applied to the substrate to increase the maximum possible storage capacity of the photoelectric conversion element. The charge stored in the photoelectric conversion element is
It is read on the charge transfer path. When transferring the charge on the charge transfer path, a second DC bias voltage higher than the first DC bias voltage is applied to the substrate to prevent charge leakage from the photoelectric conversion element to the charge transfer path. That is, smear can be prevented.

[Brief description of the drawings]

FIG. 1 is a sectional view of a solid-state imaging device according to an embodiment of the present invention.

FIG. 2 is a plan view of the solid-state imaging device.

FIG. 3 is a timing chart illustrating an operation of the solid-state imaging device according to the embodiment.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 n-type substrate 2 p-type well 3, 4 n-type region 5 p ⁺ -type region 6 insulating film 7 shift gate electrode 8 light 9 electron 21 photoelectric conversion element 22 vertical charge transfer path 23 horizontal charge transfer path 24 output amplifier

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M118 AA05 BA13 CA03 DB13 FA06 FA13 FA26 FA35 5C024 AA01 CA04 FA01 FA11 GA44 GA45

Claims (10)

[Claims] 1. A method for controlling a solid-state imaging device, comprising: a substrate having a photoelectric conversion element and a charge transfer path; and a power supply for applying a predetermined voltage to the substrate to remove charges in the substrate. (A) applying a first DC bias voltage to a substrate, converting received light into electric charges, and accumulating the electric charges in a photoelectric conversion element; and (b) applying the electric charge accumulated in the photoelectric conversion element to a charge transfer path. A method for controlling a solid-state imaging device, comprising: a step of reading; and (c) a step of applying a second DC bias voltage higher than the first DC bias voltage to the substrate to transfer charges on the charge transfer path. 2. The method according to claim 1, wherein in the step (c), a voltage obtained by adding a pulse voltage to the second DC bias voltage is applied to the substrate. 3. The method according to claim 1, further comprising: (d) switching the voltage applied to the substrate from a first DC bias voltage to a second DC bias voltage before the step (b).
Or the control method of the solid-state imaging device according to 2. 4. The method according to claim 1, further comprising: (d) switching the voltage applied to the substrate from the first DC bias voltage to the second DC bias voltage after the step (b).
Or the control method of the solid-state imaging device according to 2. 5. Further, (e) before the step (a), applying a third DC bias voltage higher than the first DC bias voltage to the substrate to transfer unnecessary charges on the charge transfer path. The method for controlling a solid-state imaging device according to claim 1, further comprising the step of: 6. The method according to claim 5, wherein said second and third DC bias voltages are the same voltage. 7. The control of the solid-state imaging device according to claim 5, further comprising a step (f) of reading unnecessary charges accumulated in a photoelectric conversion element to the charge transfer path before the step (e). Method. 8. The method according to claim 5, further comprising: (g) switching the voltage applied to the substrate from the third DC bias voltage to the first DC bias voltage before the step (e).
8. The method for controlling a solid-state imaging device according to any one of claims 7 to 7. 9. The method according to claim 5, further comprising: (g) switching the voltage applied to the substrate from the third DC bias voltage to the first DC bias voltage after the step (e).
8. The method for controlling a solid-state imaging device according to any one of claims 7 to 7. 10. A photoelectric conversion element formed on a substrate and converting received light into charges and storing the charge, a charge transfer path formed on the substrate and transferring charges stored in the photoelectric conversion element, A shift gate for reading charges accumulated in the photoelectric conversion element into the charge transfer path; a power supply connected to the substrate for applying a predetermined voltage to the substrate to remove charges in the substrate; A first DC bias voltage is applied to the substrate during a period in which the charge is accumulated in the element, and the first DC bias voltage is applied to the substrate in a period in which the charge transfer path transfers the charge accumulated in the photoelectric conversion element. Control means for controlling the power supply so as to apply a large second DC bias voltage.