JP2000100957A - Timing adjusting method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To contrive adjustment of phase and timing between clock signals, by obtaining the time lag of another clock, on the basis of the clock of the maximum propagation average delay time among plural clock signals, and replacing the standard delay adjustment cell with a logical delay adjustment cell thereby minimizing the delay time lag. SOLUTION: A plurality of delay adjustment cells which are the same in cell size and pin position and are different in inner delay time and a delay adjustment cell list 12 of cell name information are prepared. In circuit design 2, a net list where standard delay adjustment cells are inserted into all clock lines to adjust the phase between plural clock signals is made. In circuit constitution, the list 6 of delay adjustment confirmation buses of information on the names of logic cells which operate with signals controlled with plural clocks and the names of clock signals is made in addition. It is completed with cell arrangement wiring 3. In timing examination 7, the circuit operation of the designated logical cell in the list 6 of the delay adjustment confirmation buses is examined, referring to an arrangement wiring delay information file 5 and a delay library 8, consequently if there is no necessity of phase adjustment in judgment 9, it is finished.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout design method and a timing adjustment method for a synchronous circuit of a semiconductor device, and a delay adjustment cell, and more particularly to a layout design method, a timing adjustment method, and a delay adjustment cell for correcting a clock shift for a synchronous circuit. About.

[0002]

2. Description of the Related Art Large-scale semiconductor integrated circuits, SOC (Sy
For the purpose of stem-on-chip, a plurality of systems are mounted on one chip, and the design of semiconductor integrated circuits having a plurality of clock signals is increasing.

A technique for reducing clock skew, which is a problem in designing a circuit when a clock signal is supplied to a plurality of logic cells at the same timing during automatic layout design of a synchronous circuit of a semiconductor integrated circuit, is known as clock tree synthesis. Alternatively, a method called a clock tree method is used.

Clock tree synthesis, as shown in FIG. 5, means that buffers 40 to 46 are arranged in a tree on a clock line for supplying a clock from a signal input terminal 39 for inputting a clock A to each of the logic blocks 47 to 50. And the wiring between the input signal terminal 39 and each of the buffers 40 to 46 has the same wiring length, thereby reducing the propagation delay difference (clock skew) of the clock signal to each of the logic blocks 47 to 50. . Similarly, the same applies to the signal input terminal 51, the buffers 52 to 54, and the logic blocks 55 to 56.

[0005]

However, as shown in FIG. 5, the number of buffers and the number of stages on the clock line differ depending on the number and arrangement of logic blocks connected to each signal input terminal. A propagation delay difference (clock skew between clock signals) occurs between the input terminal 39 and the logic blocks 47 to 50 and between the signal input terminal 51 and the logic blocks 55 to 56.

In clock tree synthesis, clock skew is reduced for each clock signal as shown in FIG. 5, and the delay value of each clock tree itself cannot be predicted until the placement and routing is completed. Due to the increase in the number of cells, the circuit may malfunction due to a malfunction of the timing adjustment after the completion of the cell arrangement and wiring.

The conventional solution to this problem is to empirically re-execute the cell placement and routing based on the delay information after the completion of the cell placement and routing, in order to change or reexamine the circuit or to improve the skew. It is necessary to start over until the clock skew between a plurality of clock signals is reduced.

Therefore, it is difficult to match the phases of a plurality of clock signals only by the conventional clock tree synthesis, so that there is a problem that the re-design is repeated many times after the completion of the cell arrangement and wiring. . In order to reduce clock skew between a plurality of clock signals, Japanese Patent Application Laid-Open No. 9-282444 discloses a semiconductor circuit that constitutes a frequency divider, a phase comparator, a loop filter, and a voltage controlled oscillator at a stage preceding each clock tree. A method for reducing clock skew between a plurality of clock signals has been proposed.

In Japanese Patent Application Laid-Open No. 7-56984,
After designing the placement and wiring, discloses that the clock driver basic cell column is inserted and placed, and that the clock skew is reduced.
Japanese Patent Application Laid-Open No. H8-130655 discloses that the overall clock skew value is reduced by adjusting a delay value after layout in a clock input unit or a clock buffer unit of each synchronous element. Discloses that the skew can be adjusted even after the skew is corrected, even if skew occurs due to the influence of parallel wiring due to wiring routing due to specification change or logic error.

However, according to the method proposed in the above publication, a phase comparator, a loop filter,
Many complicated circuits such as a voltage-controlled oscillator are required, which makes it difficult to design circuits and increases the degree of circuit integration.

The present invention has been made in view of the above, and after reducing clock skew in each clock by clock tree synthesis, adjusts the phase and timing between a plurality of clock signals by changing a circuit after cell placement and wiring is completed. An object of the present invention is to provide a technique which can be performed without re-arranging and wiring cells.

[0012]

According to the present invention, there is provided a synchronous circuit of a semiconductor device having a logic cell to which a signal changed by a plurality of clocks or a clock different from an operation clock is supplied. After forming a logic circuit for supplying to a plurality of logic cells, and completing cell placement and wiring including clock tree synthesis, calculating the average propagation delay time of all paths of the clock and the average propagation delay time difference between the clocks, The standard delay adjustment cell on the clock line is provided between the clock input terminal and the first logic cell.

According to another aspect of the present invention, there is provided a timing adjusting method for adjusting a phase between a plurality of clock-system signals. A time difference is obtained, and a standard delay adjustment cell on a clock line other than the clock having the maximum propagation average delay time is arranged before a plurality of logic cells on a clock path.

According to another aspect of the present invention, there is provided a timing adjusting method for adjusting a phase between a plurality of clock signals, wherein a plurality of clock input terminals, a plurality of logic cells for supplying a clock to a logic circuit to which the clock is supplied, Prepare a plurality of delay adjustment cells with the same cell size and pin position but different internal delay times, create a netlist with standard delay adjustment cells inserted in the clock line, and create a netlist that includes clock tree synthesis. Based on the delay information created after completion, consider whether there is a timing error in a logic cell that operates with a signal controlled by multiple clocks and determine whether timing adjustment is necessary. Features.

According to the present invention, there is provided a timing adjustment method for adjusting a phase between a plurality of clock signals, wherein a plurality of clock input terminals, a plurality of logic cells for supplying a clock to a logic circuit to which the clock is supplied, and Prepare a plurality of delay adjustment cells with the same cell size and pin position but different internal delay times, and if timing adjustment is required, the propagation average delay time of the entire tree of each clock,
Calculating a propagation average delay difference between the plurality of clock signals;
A delay adjustment block for reducing the calculated propagation average delay time difference is selected, and a standard delay adjustment cell on a clock line is replaced with the logic cell.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments according to the present invention will be described.
This will be described in detail with reference to the drawings.

[First Embodiment] (Structure of this Embodiment) FIG. 1 is a flowchart for explaining the processing of the present invention. First, a plurality of delay adjustment cells having the same cell size and pin position but different internal delay times and a delay adjustment cell list 12 which is information on the names of the cells are prepared. Here, the internal delay time may be a method of changing one of the length of the wiring, the capacitance value in the circuit, or the number of gate stages, or a method of combining a plurality thereof. As the delay adjustment cell, a logic cell such as AND or OR may be used as long as a buffer is mainly used and the logic is not inverted and a prescribed internal delay is satisfied.
It can be replaced by a two-stage inverter or the like.

Next, in circuit design 2, a netlist is created in which standard delay adjustment cells are inserted into all clock lines for performing phase adjustment between a plurality of clock signals. Here, the “standard delay” is a cell having a minimum internal delay time capable of driving the first buffer of the clock tree. In addition, a delay adjustment confirmation path list 6 which is information on the name of a logic cell operating with a signal controlled by a plurality of clocks on the circuit configuration and the name of the clock signal is also created.

Next, the cell placement and wiring is completed in the cell placement and wiring 3. The clock skew of each clock is reduced by using a conventional clock tree synthesis. Then, in the post-placement and wiring delay information generation 4, a netlist including the wiring capacitance and the resistance and the post-placement and wiring delay information file 5 are prepared.

Next, in the timing study 7, the logic cell specified in the delay adjustment confirmation path list 6 is referred to the post-placement and routing delay information file 5 and the delay library 8, and the circuit operation is performed by a circuit simulator or the like. Investigate whether there is any problem in the timing, and examine whether it is necessary to adjust the timing by adjusting the phase between a plurality of clock signals. In addition,
The delay library 8 contains information such as internal delay times and timing constraints of all logic cells and delay adjustment cells used in the circuit. Next, in the judgment 9 as to whether or not the timing adjustment is required, if the timing adjustment by the phase adjustment is not necessary, this flow is finished, but if necessary, the process proceeds to the next step.

Next, referring to the post-place and route delay information file 5 and the delay library 8, the propagation delay time of the entire tree path of each clock is calculated by a circuit simulator, a path calculation tool, etc. The tree total path delay time of each clock And the average time are calculated 10 to determine the propagation minimum delay time and the propagation maximum delay time in the tree of each clock, calculate the propagation average delay time therefrom, and in the clock signal for phase adjustment A calculation 11 of an average delay time difference between a plurality of clock signals for calculating an average propagation delay time difference with respect to a clock having a maximum propagation average delay time is executed.

Next, in the delay adjustment cell selection and replacement 13, a delay adjustment cell having an internal delay time that minimizes the average propagation delay time difference is selected from the delay adjustment cell list 12 with reference to the delay library 8. Automatically replaces the standard delay adjustment cell on the clock line with the smaller propagation average delay value with the selected cell. Further, the delay adjustment cell may be inserted between the buffers.

The delay information re-creation 14 after placement and routing reduces clock skew between a plurality of clock signals,
A new post-place and route delay information file for which timing adjustment has been completed can be created. Thus, each step of the layout design method for the synchronous circuit of the semiconductor device is completed.

(Operation of the Present Embodiment) Next, the method of FIG. 1 will be described with reference to FIGS. 2 and 3. FIG. 2 is a diagram showing a state where the cell arrangement wiring 3 of FIG. 1 is completed.
The clock signal input terminal 15 is connected to the standard delay adjustment cell 16 to the logic cells 24 to 27 and the buffers 17 to 23 in a tree shape.
Through the connection. Clock signal input terminal 29,
The standard delay adjustment cell 30, buffers 31 to 33, and logic cells 34 to 35 have the same configuration.

The internal delay time of the standard delay adjustment cells 16 and 30 is TDB (Time Delay of Block). In FIG. 2, the clock signal input from the clock signal input terminal 15 is CK1, and the clock input signal input from the clock signal input terminal 29 is CK2. P1 indicates a tree path from the clock signal input terminal 15 to the logic cell 24 via the standard delay adjustment cell 16 and the buffers 17, 18, and 20, and P2 indicates a tree path from the clock signal input terminal 15 to the standard delay adjustment cell 16, buffer 17 , 18 and 21 represent a tree path reaching the logic cell 25, and P3 represents a tree path reaching the logic cell 26 from the clock signal input terminal 15 via the standard delay adjustment cell 16 and the buffers 17, 19 and 22. P4 is a clock signal input terminal 15
From the standard delay adjustment cell 16, buffers 17, 19, and 23
Represents a tree path that reaches the logic cell 27 via the.

P5 represents a tree path from the clock signal input terminal 29 to the logic cell 34 via the standard delay adjustment cell 30, buffers 31 and 32, and P6 represents a tree path from the clock signal input terminal 29 to the standard delay adjustment cell 30. , The tree path reaching the logic cell 35 via the buffers 31 and 33.

The logic cell 34 has a clock signal CK.
This is a flip-flop expected to take in the output data signal of the logic circuit 28 which receives the output signals of the logic cells 24 to 27 changed at the rise of 1 at the fall of the clock signal CK2. It is assumed that the operation check study at the time of creation has been completed. FIG. 3 is a timing chart of the input signals of the logic cells 24 to 27 and 34 of FIG. 2C is the waveform of the clock signal CK1 input to the logic cells 24-27, and 34D is the logic cell 3
4 indicates the waveform of the data signal input to the logic cell 34, and 34C indicates the waveform of the clock signal CK2 input to the logic cell 34. FIG. 3A is a timing chart before the cell arrangement and wiring.

First, with respect to the logic cell 34 designated to perform the timing verification in the delay adjustment confirmation path list 6, the circuit operation is performed by a circuit simulator or the like with reference to the delay information after placement and routing created in step 4 and the delay library 8. The timing is examined to see if there is any problem, and whether timing adjustment by phase adjustment between a plurality of clock signals is necessary.

If there is no timing error in all the paths and no timing adjustment is required, this flow is terminated. In this case, in the timing after the completion of the cell arrangement and wiring shown in FIG. The logic block 34 differs from that before the layout design.
Needs to be adjusted in timing. Next, from the information of the delay adjustment confirmation path list 6, when the timing adjustment of the logic block 34 is necessary, the clock signal CK which is specified to require the phase adjustment among the plurality of clock-system signals.
For 1 and CK2, delay calculation for phase adjustment is performed.

The propagation delay time TP1 of the tree path P1, the propagation delay time TP2 of the tree path P2, the propagation delay time TP3 of the tree path P3, and the propagation delay time TP4 of the tree path P4 of the signal CK1 are calculated by using the post-place and route delay information and the delay. With reference to the library 8, it is obtained by a circuit simulator or the like. The resulting propagation delay times TP1, TP2, TP3, TP4
Are compared, and the maximum propagation delay time and the minimum propagation delay time are specified.

Here, it is assumed that TP1 is maximum and TP4 is minimum, and the average propagation delay time TA1 from the clock signal input terminal 15 to each of the logic circuits 24 to 27 is calculated as TA1 = (TP1 + TP4) ４2.

Similarly, with respect to the signal CK2, the propagation delay time TP5 of the tree path P5 and the propagation delay time TP6 of the tree path P6 are obtained. Here, it is assumed that TP5> TP6. ,
TA2 = (TP5 + TP6) ÷ 2 is calculated as the propagation average delay time TA2 up to 35.

Next, TA1 and TA2 are compared, and TA1>
In the case of TA2, the average propagation delay time difference ΔT12 = TA1-
TA2 is obtained, a delay adjustment cell having an internal delay time of ΔT12 + TDB is selected from the delay cell list, and a signal CK2
Of the standard delay adjustment cell 30 on the clock of ΔT1
2 is minimized, the clock skew between a plurality of clock signals of the signals CK1 and CK2 is reduced, and the logic cell 3
4 can be performed. FIG. 3C is a timing chart after completion of the timing adjustment (after replacement of the delay adjustment cell).

In this embodiment, the method of adjusting the phase and timing between two clock signals has been described. However, the number of clocks is not limited and three or more clock signals are required. In this case, the average propagation delay difference between the other clocks is calculated based on the clock with the maximum propagation average delay time between the clock signals. What is necessary is just to replace the delay adjustment cell with an appropriate delay adjustment cell.

[Second Embodiment] Next, a second embodiment of the present invention will be described with reference to the flowchart of FIG.

FIG. 4 changes the delay adjustment check path list 6 created in the circuit design 2 of FIG. 1 to an allowable clock delay time difference list 36, and performs a timing study 7 and a step 9 of checking whether timing adjustment is necessary. Omitted, calculation of average delay time difference 11 between a plurality of clock signals, selection of delay adjustment cell,
A step 37 of comparing the allowable delay time difference and the calculated delay time difference is added between the steps of the replacement 13.

The allowable clock delay time difference list 36 is
If the average delay time difference between specific clock signals is greater than or equal to the above, it is an information file indicating whether phase adjustment between a plurality of clock signals is necessary or specific numerical values and clock signal names. The comparison 37 between the allowable delay time difference and the calculated delay time difference is a step of comparing the numerical value of the allowable clock delay time difference list 36 with the actually calculated value. Compared to FIG. 1 according to the first embodiment, a step of comparing whether or not skew adjustment is required between a plurality of clock signals, which causes a timing error, with a specific numerical value is added, so that phase adjustment and timing It is easy to determine whether adjustment is necessary. This embodiment can shorten and simplify the processing time when the present method is used for a large-scale semiconductor integrated circuit or the like.

In FIG. 4, first, a plurality of delay adjustment cells having the same cell size and pin position but different internal delay times and a delay adjustment cell list 12 which is information on the cell names are prepared. Here, the internal delay time may be a method of changing one of the length of the wiring, the capacitance value in the circuit, or the number of gate stages, or a method of combining a plurality thereof.

Next, in circuit design 2, a netlist is created in which standard delay adjustment cells are inserted into all clock lines for performing phase adjustment between a plurality of clock signals. Here, the “standard delay” is defined as a cell having a minimum internal delay time capable of driving the first buffer of the clock tree. In addition, if the average delay time difference between specific clock-related signals is more than the circuit configuration, it is necessary to adjust the phase between multiple clock-related signals or an information file showing specific numerical values and clock signal names. Is created.

Next, the cell placement and wiring is completed in the cell placement and wiring 3. The clock skew of each clock is reduced by using a conventional clock tree synthesis. Then, in the post-placement and wiring delay information generation 4, a netlist including the wiring capacitance and the resistance and the post-placement and wiring delay information file 5 are prepared.

Next, in the judgment 9 as to whether or not the timing adjustment is required, if the timing adjustment by the phase adjustment is not necessary, this flow is finished, but if necessary, the process proceeds to the next step.

Next, referring to the post-place and route delay information file 5 and the delay library 8, the propagation delay time of the entire tree path of each clock is calculated by a circuit simulator, a path calculation tool or the like. And the average time are calculated 10 to determine the propagation minimum delay time and the propagation maximum delay time in the tree of each clock, calculate the propagation average delay time therefrom, and in the clock signal for phase adjustment A calculation 11 of an average delay time difference between a plurality of clock signals for calculating an average propagation delay time difference with respect to a clock having a maximum propagation average delay time is executed.

Next, the comparison 37 between the allowable delay time difference and the calculated delay time difference is a step of comparing the numerical value of the allowable clock delay time difference list 36 with the value of the calculated delay time difference actually calculated. Compared to FIG. 1 according to the first embodiment, a step 38 of comparing the calculated value with an allowable value for comparing whether a skew adjustment between a plurality of clock signals that causes a timing error is necessary or not with a specific numerical value. If the permissible value is larger than the calculated value, the process is terminated as permissible,
If the calculated value is larger than the allowable value, the process proceeds to delay adjustment cell selection / replacement 13 and refers to the delay library 8 to adjust delay having an internal delay time such that the average propagation delay time difference is minimized. A cell is selected from the delay adjustment cell list 12, and a standard delay adjustment cell on a clock line having a small propagation average delay value is automatically replaced with the selected cell.

Then, the delay information re-creation 14 after placement and routing reduces the clock skew between a plurality of clock signals,
A new post-place and route delay information file for which timing adjustment has been completed can be created.

[0045]

According to the present invention, by using a plurality of delay adjustment cells having the same cell size and pin position but different internal time delays, the phase adjustment between a plurality of clock signals can be performed after the completion of cell placement and wiring. Therefore, the phase adjustment and the timing adjustment between a plurality of clock signals can be performed based on the delay information after the completion of the cell arrangement and wiring.

Further, since the delay adjustment is performed at the time of layout design, it is only necessary to insert a standard delay adjustment cell on the clock line at the time of circuit design, so that the clock skew between clock signals and the timing adjustment can be simplified. Can be realized.

Further, according to the present invention, the clock skew value between a plurality of clock signals after the completion of the phase adjustment is determined. For example, when a clock signal having a clock skew of 5 ns, a clock having a clock skew of 3 ns, and a clock having a clock skew of 2 ns are phase-adjusted by the method of the present invention, the clock skew between the three clock signals becomes 5 ns. It is considered to be. That is,
The average value of the maximum propagation delay time and the minimum propagation delay time, not the average delay time of all paths in the tree, that is, the middle of the clock skew. This is because the maximum clock skew value becomes the final clock skew value between a plurality of clock signals.

Further, according to the present invention, it is not necessary to change the circuit for reducing the skew between a plurality of clock signals and adjusting the timing, so that the circuit and layout design time can be reduced.

According to the present invention, the size of the buffer to be replaced and the wiring path do not need to be changed, so that the degree of integration of the circuit does not need to be changed, and it is not necessary to redo the layout. Troubles such as wiring shortage and cell overlap can be avoided.

[Brief description of the drawings]

FIG. 1 is a flowchart of a layout design method according to the present invention.

FIG. 2 is a specific circuit diagram using a layout design method according to the present invention.

FIG. 3 is a timing chart using the layout design method according to the present invention.

FIG. 4 is a flowchart of a layout design method according to the present invention.

FIG. 5 is a circuit diagram according to a conventional layout arrangement.

[Explanation of symbols]

16, 30 Standard delay adjustment cell 17 to 23, 31 to 33, 40 to 46, 52 to 54 Buffer 24 to 27, 34, 35, 47 to 50, 55, 56 Logic cell 28 Logic circuit

[Procedure amendment]

[Submission date] August 27, 1999 (1999.8.2
7)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

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[Claims]

[Procedure amendment 2]

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[Correction target item name] 0041

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[Procedure amendment]

[Submission date] January 18, 2000 (2000.1.1)
8)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Name of invention

[Correction method] Change

[Correction contents]

[Title of the Invention] Timing adjustment method

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

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[Claims]

[Procedure amendment 3]

[Document name to be amended] Statement

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[Correction method] Change

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[0012]

According to the present invention, a plurality of input clocks are provided.
Logical times involving clock tree synthesis with locks
To adjust the phase between multiple clock signals for the
In the method for adjusting the timing, the plurality of clock signals
Between the clocks with the maximum propagation average delay time
The average propagation delay time difference between the other clocks
On a clock line other than a clock with a large propagation average delay time
The standard delay adjustment cell of
Replace with the cell's delay adjustment cell and calculate the average propagation delay time difference.
It is characterized by being minimized.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0013

[Correction method] Deleted

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Claims (6)

[Claims] In a synchronous circuit of a semiconductor device having a logic cell to which a signal changed by a plurality of clocks or an operation clock and another clock is supplied, a logic circuit for supplying a clock to the plurality of logic cells in accordance with an input clock After completion of the cell placement and routing including clock tree synthesis, the average propagation delay time of the entire tree of each clock and the average propagation delay time difference between them are calculated as follows.
A synchronous circuit for a semiconductor device, wherein a standard delay adjustment cell on a clock line of the clock is provided between a clock input terminal and the first logic cell. 2. A timing adjustment method for adjusting a phase between a plurality of clock-system signals, wherein an average propagation delay time difference of each of the other clocks is determined based on a clock having a maximum propagation average delay time among the plurality of clock-system signals. A timing adjustment method, wherein a standard delay adjustment cell on a clock line other than the clock having the maximum propagation average delay time is arranged before a plurality of logic cells on a clock path. 3. The timing adjustment method according to claim 2, wherein in a logic circuit including clock tree synthesis having a plurality of input clocks, a path having the maximum propagation average delay time and a path having another propagation delay time. The average delay time difference obtained by averaging the differences and comparing the average delay time difference with the average delay time difference of the path having another input clock, and inserting the standard delay adjustment cell. 4. A timing adjustment method for adjusting a phase between a plurality of clock signals, comprising: a plurality of clock input terminals; a plurality of logic cells for supplying a clock to a logic circuit to which the clock is supplied; Prepare a plurality of delay adjustment cells with the same pin positions and different internal delay times, create a netlist with standard delay adjustment cells inserted into the clock line, and create the netlist after cell placement and routing including clock tree synthesis is completed. A timing error of a logic cell operating with a signal controlled by a plurality of clocks based on the delayed information, and determining whether timing adjustment is necessary. Adjustment method. 5. A timing adjustment method for adjusting a phase between a plurality of clock signals, comprising: a plurality of clock input terminals; a plurality of logic cells for supplying a clock to a logic circuit to which the clock is supplied; When a plurality of delay adjustment cells having the same pin position and different internal delay times are prepared and timing adjustment is necessary, the propagation average delay time of the entire tree of each clock and the propagation Calculate the average delay difference, select a delay adjustment block to reduce the calculated propagation average delay time difference,
A timing adjustment method, wherein a standard delay adjustment cell on a clock line is replaced with the logic cell. 6. The timing adjustment method according to claim 4, wherein the delay adjustment cell is a logic cell having an internal delay time such that an average propagation delay time difference is minimized. A timing adjustment method comprising: creating a delay adjustment cell list; selecting a delay adjustment cell list from the delay adjustment cell list in accordance with the propagation average delay time of the entire tree path; and replacing a logic cell.