JP2013021452A - Control device and designing method for determining the number of arithmetic circuits - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a transmission interval control technique to control a semiconductor bus, which asynchronously transmits plural packets having a predetermined processing termination time, to execute a necessary access amount in a minimum period of time within the processing limit by appropriately adjusting the transmission interval of plural packets.SOLUTION: The control device includes: an allowable delay calculation section that calculates an allowable delay, which represents an allowable delay amount allowed for packets to be subsequently transmitted, and outputs the same as a piece of adjust range information at a timing determined depending on the transmission termination time of the predetermined number of packets; a transmission interval determination section that determines the transmission interval of the packets based on at least a piece of adjusting range information and permits or inhibits an initiator, which is connected adjacent thereto, to transmit the data according to the determined result; and a transmission/reception section that transmits at least one packet which is generated based on the data received from the initiator which is permitted to transmit the data.

Description

  The present invention relates to a technique for controlling a communication bus in a semiconductor chip having a networked communication bus.

  In recent years, network-on-chip (hereinafter “NoC”) has been used as a communication bus in the field of system on chip (hereinafter “SoC”) and multi-core processors. I came.

  FIG. 1 shows an example of a general connection configuration in which NoC is applied to the main bus between the initiators I1 to I4 and the targets T1 to T4. The initiator is, for example, a DSP (Digital Signal Processor), a CPU (Central Processing Unit), or a DMAC (Direct Memory Access Controller). The target is, for example, a memory controller connected to an external DRAM, an SRAM, or a buffer memory for input / output with the outside.

  The initiator and the target are connected to each other through a network bus composed of NoC routers R1 to R4 via NIC1 to NIC8, which are network interface controllers (NICs). . In NoC, all data exchange on the bus is performed in packet units. For this purpose, the NIC has a function of packetizing and depacketizing transaction data transmitted and received by the initiator and the target. Further, because of the NoC structure, the links L1 to L8 connecting the routers are shared when packets are transmitted from the plurality of initiators I1 to I4 to the targets T1 to T4.

  In the NoC configured as shown in FIG. 1, the communication band of each link is designed under two contradictory constraints. In other words, by improving the link bandwidth, the first restriction of ensuring the transmission quality such as latency and throughput required by each initiator, and by reducing the link bandwidth, avoiding high frequency design of the circuit and reducing power consumption. The second restriction is to reduce.

  Since the bandwidth required by each initiator generally varies with time, the average bandwidth required per unit time does not match the maximum bandwidth. If multiple initiators that share the same link and asynchronously transmit packets access the maximum bandwidth to the target almost simultaneously, the link on the path can accommodate all accesses. Therefore, an increase in latency and a decrease in throughput occur. In particular, when there is an initiator that performs burst-type access, the link on the transmission path is overloaded during a series of accesses (burst access). Reduce the real-time nature of the process.

  “Burst-type access” or “burst access” here means, for example, an access in which a fixed number of accesses are continuously performed and then calculation processing is performed internally, and a fixed number of accesses are continuously performed again. It is. FIG. 2 shows an example of burst access to the memory. The horizontal axis represents time, and the vertical axis represents the amount of data read from the memory (memory access amount). It is understood that after a series of accesses continuing for a certain period occurs, the access is temporarily stopped, and thereafter, a series of accesses continuing for a certain period again occurs.

  Patent Document 1 discloses a technique for avoiding packet transmission contention when a communication bus is shared among a plurality of initiators operating asynchronously. The initiator monitors the communication bus to detect a transmission conflict, sets a random waiting time for each initiator, waits, and performs a transmission operation again after the waiting time has elapsed. With this operation, each initiator can share the communication bus while autonomously avoiding contention of transmission packets.

  Non-Patent Document 1 discloses a method for calculating a standby time. According to Non-Patent Document 1, it is possible to efficiently prevent contention for transmission requests by increasing the standby time as the time for detecting contention with other initiators is longer.

JP-A-61-230444 Japanese Patent No. 1373810

IEEE Std 802.3 Standard (Section 4.2.3.2.5)

  However, the DSP is usually mounted on the assumption that processing of signals such as video signals and audio signals is performed in real time. Therefore, there is a need to complete a necessary amount of data access by a predetermined processing time limit. In the prior art, the real time property of the process could not be secured. The reason for this is that when the conflict repeatedly occurs, the prior art randomly extends the waiting time while raising the upper limit of the waiting time.

  If real-time performance cannot be ensured, the user will be affected, for example, in the form of dropping frames, skipping sound, and increasing service wait time. Therefore, delay should not be tolerated.

  Note that Non-Patent Document 1 described above relates to a transmission protocol technique in a general network. General network communication is best-effort communication and delay is allowed. Therefore, it is difficult to apply general network technology uniformly to NoC.

  FIG. 3 shows an example in which all accesses are not completed before the processing deadline when the conventional technique is applied. Assume that both initiator 1 and initiator 2 shown in FIG. 3 are initiators that perform burst access. Under a situation where a plurality of initiators performing burst access compete, as shown in FIG. 3, the upper limit of the waiting time is raised due to repeated occurrence of the competition.

  Now, it is assumed that both initiator 1 and initiator 2 simultaneously start access requests at time t0. That is, the first access conflict occurs at time t0. At this time, each of the initiator 1 and the initiator 2 performs a conflict avoidance by setting a random waiting time with an upper limit of L. When the standby time of the initiator 1 is shorter than the standby time of the initiator 2, the initiator 1 restarts the burst access before the initiator 2. When the standby state of the initiator 2 is released at time t1, a conflict occurs again. At this time, since the initiator 2 has detected two consecutive conflicts, the upper limit of the waiting time is rounded up by a factor of two. As a result, the waiting time upper limit of the initiator 1 becomes shorter than that of the initiator 2 again. Furthermore, when the standby state of the initiator 2 is canceled at time t2, a conflict occurs again with the initiator 1 that has previously resumed access, and the initiator 2 has detected three conflicts. Is rounded up to 4 times.

  According to the conventional technique, the initiator 2 that has waited for a long time in the initial competition becomes disadvantageous in the subsequent re-competition, and the time when the initiator 2 starts to access again is time t3. At time t3, all accesses of initiator 1 are completed, so burst access of initiator 2 is resumed. However, due to repeated waiting times, there is no longer enough time to complete all accesses by the process deadline. As described above, in the conventional technique, all accesses cannot be completed within the processing time limit, and the processing of the signal processing is lost. In addition, the real time property of the process could not be secured.

  In a semiconductor bus that asynchronously communicates multiple packets having the same processing completion time, the necessary access amount can be executed in the shortest time while adhering to the processing deadline by appropriately adjusting the transmission interval of the multiple packets. A possible transmission interval control method is considered. Each initiator needs to ensure real-time processing by completing Np data accesses during the processing completion time limit Tb (cycle).

The interval between adjacent data accesses is G cycles, the adjustment unit adjusted by the control of one communication interval is K, the number of cycles remaining until the process completion deadline is Rc, and the number of remaining data accesses is Rp Assuming that the number of cycles required to transfer one packet is Nf, the communication interval G for each data access is given by equation (1).

  According to Equation 1, it is necessary to calculate the upper limit of the communication interval adjustment range in order to appropriately control the communication interval G while ensuring the real-time property based on the current time t and the process completion time limit Tb. Therefore, it is necessary to divide the remaining cycle number Rc by the remaining access number Rp.

  In general, division processing increases the computational cost of hardware. That is, the division process requires a larger number of cycles than addition and subtraction.

  For this reason, the minimum interval at which the communication interval G can be controlled is limited by the number of cycles spent for division execution, and there is a first problem that the communication interval G cannot be updated at an optimal timing according to the actual packet size. . Also, in order to reduce the number of cycles required for division execution, it is necessary to execute a complex high-speed division algorithm and to hold a large-scale division result data table as described in Patent Document 2, which is very large. There was a second problem of requiring a hardware circuit having the number of gates. Furthermore, since the timing at which each data access is processed fluctuates depending on the bus and target congestion, it is difficult to predict the value of the remaining data access Rp at the time of controlling the communication interval G, and division is executed predictively. There was a third problem that it was not possible to speed up by doing.

  The present invention has been made in view of the above problems, and an object thereof is to appropriately adjust a transmission interval of a plurality of packets in a semiconductor bus that asynchronously communicates a plurality of packets having a predetermined processing completion time. Accordingly, it is an object of the present invention to provide a transmission interval control method capable of executing a necessary access amount in the shortest time while keeping the processing deadline.

  A control device according to the present invention is a control device for controlling a transmission timing of each packet and transmitting each packet to the bus in a semiconductor circuit having a networked bus through which a plurality of packets are transmitted. An allowable delay calculation unit that calculates an allowable delay indicating an allowable transmission delay amount of a packet to be transmitted later and is output as adjustment range information at a timing determined according to the transmission completion time of a plurality of packets, and at least the adjustment The transmission interval of each packet is determined based on the range information, and a transmission interval determination unit that permits or prohibits data transmission by an adjacently connected initiator according to the determination result, and transmission of the data is permitted Transmitting / receiving unit for transmitting to the bus at least one packet generated based on the received data from the initiator It is equipped with a.

  The allowable delay calculation unit includes N calculation execution units in parallel, each of which requires time n to execute a predetermined calculation, a minimum size a of a packet transmitted to the bus, and a parallel of the calculation execution units. A control interval determining unit that calculates a control interval p based on the number N and the time n, and the predetermined number may be determined by the control interval p.

The control interval determination unit may determine the control interval p according to the following equation.

  The transmission interval determination unit may determine the transmission interval of each packet based on the information on the load L of the bus in addition to the adjustment range information.

  When the load L is larger than a predetermined value, the transmission interval determination unit expands the transmission interval of each packet, and when the load L is equal to or less than the predetermined value, the transmission interval determination unit The transmission interval of each packet may be reduced.

  Another initiator or target is connected to the bus, and the transmission interval control unit calculates a latency that is a time from when an access request is transmitted to the other initiator or the target until a response is returned. The transmission / reception unit may be used and used as a load on the bus.

The method according to the present invention is provided in parallel to a control device for controlling the transmission timing of each packet and transmitting each packet to the bus in a semiconductor circuit having a networked bus through which a plurality of packets are transmitted. A design method for determining the number N of arithmetic circuits, wherein the control device determines an allowable transmission delay amount of a packet to be transmitted thereafter at a timing determined according to a transmission completion time of a predetermined number of packets. An allowable delay calculation unit that calculates the allowable delay shown and outputs it as adjustment range information, determines a transmission interval of each packet based on at least the adjustment range information, and depends on the determination result by an initiator connected adjacently Data received from the transmission interval determination unit that permits or prohibits data transmission, and the initiator that is permitted to transmit the data A transmission / reception unit that transmits at least one packet generated based on the bus to the bus, and the allowable delay calculation unit includes N operations in parallel, each of which requires time n to execute a predetermined calculation. A circuit and a control interval determination unit that calculates the control interval p, which is the predetermined number, based on the minimum size a of packets transmitted to the bus, the parallel number N of the arithmetic circuits, and the time n The method includes the step of inputting a value of a predetermined control interval p, a step of acquiring a predetermined value of the minimum size a and the value of the time n, and the calculation by the following formula: Determining the parallel number N of the circuit.

  According to the present invention, in a semiconductor bus that asynchronously communicates a plurality of packets having the same processing completion time, interference between flows is suppressed by appropriately adjusting a transmission interval of the plurality of packets, and the entire system is Throughput and latency can be improved. At the same time, since the required access amount can be executed in the shortest time while keeping the processing completion time, it is possible to ensure real-time performance of applications such as media processing. In addition, since automatic adjustment of the transmission interval according to the network status works, the cost of design evaluation of transmission timing using complicated use cases in the design phase can be reduced.

It is a figure which shows the example of the general connection structure which applied NoC to the main bus between initiator I1-I4 and target T1-T4. It is a figure which shows an example of the burst access to a memory. FIG. 10 is a diagram illustrating an example in which all accesses are not completed by the processing deadline when the conventional technique is applied. It is a figure which shows the structural example of SoC100 which has a NoC bus | bath. It is a figure which shows the example of the data structure of the request transaction 10 which DMAC produced | generated. It is a figure which shows request transaction 12 packetized by adding packet header PH by NIC1. It is a figure which shows an example of the data structure of the reply transaction 14 which NIC5 received from MEM1. It is a figure which shows an example of the data structure of the reply transactions 16 and 18 packetized. It is a figure which shows the typical burst access example. It is a figure which shows the example of an access delay of DMAC when DMAC, ENC, and DEC simultaneously request access to MEM1. It is a figure which shows the example of access delay of DMAC when DMAC, ENC, and DEC make an access request to MEM1 while adjusting the transmission interval. 2 is a diagram illustrating a basic configuration of a NIC 120 on an initiator side. FIG. 3 is a diagram illustrating a basic configuration of a transmission interval control unit 125. FIG. It is a flowchart which shows the procedure of the process of NIC120 by the side of an initiator. 3 is a diagram illustrating a basic configuration of an allowable delay calculation unit 131. FIG. It is a flowchart which shows the procedure of the process of the control interval determination part 144. It is a figure which shows the example of the register group for recording the parameter which the transmission space | interval control part 125 manages. 7 is a flowchart illustrating a processing procedure of a transmission interval control unit 125. It is a figure which shows the kind of burst access. It is a timing chart when the minimum packet size of data access from the initiator is 9 flits. FIG. 6 is a timing diagram when a new data access with a packet size of 7 flits occurs from an initiator. FIG. 10 is a timing chart when an arithmetic circuit is parallelized using two circuits A and B so that an adjustment range can be calculated within a time limit. FIG. 6 is a timing chart when the number of parallel N = 3, the minimum packet size a = 2, and the number of cycles n = 9 required for the operation of the divider circuit. FIG. 24 is a timing chart when the minimum packet size transmitted by the initiator is changed from 2 flits (a = 2) to 4 flits (a = 4) during operation under the conditions shown in FIG. It is a figure which shows the result of the latency of the packet when not performing transmission interval control. It is a figure which shows the result of the latency of the packet at the time of performing transmission interval control by embodiment of this invention.

  Hereinafter, embodiments of a transmission interval control device according to the present invention will be described with reference to the accompanying drawings. In the following embodiments, a transmission interval control device will be described by taking an example in which NoC is used as a main bus of SoC incorporated in a mobile phone or an AV device.

(Embodiment 1)
First, the configuration of the circuit network will be described. FIG. 4 shows a configuration example of the SoC 100 having a NoC bus. The SoC 100 is incorporated into, for example, a mobile phone or an AV device. In FIG. 4, data is transmitted from the initiator described at the top to the target described at the bottom. Alternatively, data is transmitted from the target to the initiator in response to a read request from the initiator.

  FIG. 4 shows an example of a bus initiator and target. That is, as a bus initiator, a DMAC (Direct Memory Access Controller) that performs display processing on a screen, an ENC (Encoder) that performs MPEG (Motion Picture Expert Group) encoding of a video signal, and a DEC (MPEG) that decodes a video signal. Decoder), a CPU (Central Processing Unit) that performs web browser, user interface processing, and the like. Targets include memory controllers MEM1 (Memory Controller 1) to MEM4 (Memory Controller 4) connected to external DRAM1 to DRAM4 (not shown).

  Each initiator and each target are connected to a network interface controller NICn (n: an integer from 1 to 8). A plurality of network interface controllers are connected by a router Rk (k: integer of 1 to 4). Thereby, each initiator and each target are connected so that they can communicate with each other.

  In the following, basic processing of data and data flow in the SoC 100 will be outlined.

  The initiator first generates a request transaction which is an access request to the target, and outputs it to NICx (x: an integer of 1 to 4) connected to itself.

  Upon receiving the request transaction from the initiator, NICx packetizes the received request transaction and sends it to the network bus configured by the connection between the routers R1 to R4.

  The NIC (y + 4) connected to the memory controller MEMy (y: an integer from 1 to 4) receives a packet transmitted from the initiator side via the routers R1 to R4 and configures a request transaction of the initiator from the packet. To do. Then, the NIC (y + 4) transfers the obtained request transaction to the memory controller MEMy connected to itself. The memory controller MEMy writes data to the DRAMy (data write) or reads data stored in the DRAMy (data read) according to the requested transaction. The result is passed from the memory controller MEMy to NIC (y + 4).

  The NIC (y + 4) connected to the memory controller MEMy packetizes a return transaction obtained by the memory controller MEMy reading or writing to the DRAMy, and is configured by a router Rk (k: an integer of 1 to 4). Sent to the network bus.

  The NICx connected to the initiator receives the reply packet sent from the target, depackets it, forms a reply transaction, and notifies the initiator as an access result.

  Next, specific examples of the above request transaction and reply transaction will be described. Here, an example will be described in which the DMAC transmits the request transaction 10 and reads the data stored in the MEM1.

  FIG. 5 shows an example of the data structure of the request transaction 10 generated by the DMAC. The request transaction 10 has an R / W field, an ADDR field, and a SIZE field. In FIG. 5, “R / W”, “ADDR”, and “SIZE” are shown, respectively. The same applies to FIGS. 6 to 8 below.

  In the R / W field, an instruction indicating a read operation from the memory is described. In the ADDR field, the address of a DRAM from which data is read is described. The size of data to be read is specified in the SIZE field.

  FIG. 6 shows the request transaction 12 packetized by the NIC 1 with the packet header PH added. The packet header PH stores the node ID of the NIC 1 as the request source (the initiator that transmitted the request). The packet header PH stores the ID of the node of the NIC 5 as the request destination. The NIC 5 performs processing (depacketization processing) for removing the packet header from the packetized request transaction 12 to reconfigure the request transaction 10 shown in FIG. 5, and transfers the request transaction 10 to the MEM 1.

  The MEM 1 specifies the read operation based on the R / W field described in the request transaction 10. Further, the MEM 1 reads the ADDR field and the SIZE field, and reads data of the size specified in the SIZE field from the address on the DRAM specified in the ADDR field. Thereafter, the MEM 1 outputs the data obtained as a result of the reading to the NIC 5.

  FIG. 7 shows an example of the data structure of the reply transaction 14 received by the NIC 5 from the MEM 1. The NIC 5 packetizes the reply transaction and transfers it to the network bus.

  FIG. 8 shows an example of the data structure of the packetized reply transactions 16 and 18. The reply transaction 16 is generated by attaching the packet header PH to the acquired data. If the size of the data to be returned is large, it may be returned in a plurality of packets. After receiving one reply packet 16 or a plurality of reply packets 18, the NIC 1 deconstructs the reply packet 16 or 18 to reconstruct the reply transaction 14 shown in FIG. NIC1 completes the DMAC memory access by transferring the data to DMAC.

  Next, the operation of the SoC 100 according to the present embodiment will be described.

  In the following, it is assumed that the DMAC as the initiator performs a process of displaying a video (not shown). However, it is assumed that not only the DMAC operates on the SoC 100 but also that the ENC, the DEC, and the CPU operate in parallel and exchange data.

  In this embodiment, since the DMAC performs display processing on the screen, in order not to reduce the user value of the product due to frame dropping or freezing on the display screen, the demand for latency during memory access is severe, and real-time performance is required. Is important.

  On the other hand, ENC and DEC that execute video and audio encoding and decoding algorithms typified by MPEG generate bursty access in the process of signal processing. FIG. 9 is an example showing a typical burst access. “Tb” in FIG. 9 is a cycle in which a burst occurs. For a codec that performs signal processing in units of MPEG macroblocks, Tb is represented by the number of cycles corresponding to one macroblock time. “Np” is the number of accesses that occur in one burst. Np is determined by the codec processing algorithm prior to the start of burst access.

  The CPU is also used for user interaction processing, Internet browsing processing, and the like. Although it is difficult to estimate the timing at which access occurs and the amount of access in advance, compared to other initiators, the demand for real-time processing is not strict regarding CPU processing.

  The router configuring the network bus determines the output port according to the destination stored in the packet header, and transfers the packet. The number of cycles Tp required to transfer one packet differs depending on the internal hardware configuration and the packet size.

  FIG. 10 shows how DMAC access is delayed when DMAC, ENC, and DEC simultaneously request access to MEM1. From the top of the drawing, ENC, DEC, DMAC, R1 and R3 output packets, and the time (cycle) at which the packets are output. In the figure, the numbers assigned to the packets are numbers for distinguishing the packets, and are merely added for convenience of explanation.

  In the example of FIG. 10, ENC and DEC transmit data of packet 1 and packet 2 at the same timing, transmit packet 3 and packet 4 in the subsequent cycle, and transmit packet 5 and packet 6 in the subsequent cycle. . The DMAC transmits the packet 7 at the same timing as when the packets 5 and 6 are output.

  In the following description, it is assumed that the routers R1 and R3 require one cycle to transfer one packet unless interference waiting with a transmission packet from ENC and DEC occurs. That is, assume that the packet 7 output from the DMAC arrives at MEM1 after two cycles.

  The packet transmitted by the ENC and DMAC is received by the router R1 after one cycle and relayed to the subsequent router R3. On the other hand, the packet 7 transmitted from the DMAC simultaneously with the transmission of the packet 5 from the ENC cannot pass through the router R1 simultaneously with the packet 5 from the ENC. Thus, for example, the packet 7 is relayed after the packet 5. At this time, a delay of one cycle occurs in the packet 7.

  On the other hand, the DEC transmits packet 2, packet 4, and packet 6 in order at the same timing as the transmission start timing of ENC. Packets 2, 4, and 6 are transmitted to router R3 via router R2. Router R3 relays packets 2, 4, and 6 together with the relay packet of router R1. Router R3 alternately outputs packets from router R1 and packets from DEC.

  According to the packet output timing of the router R3 in FIG. 10, the packet 7 that is relayed by the router R3 and arrives at MEM1 has a delay of 4 cycles based on the two cycles that reach the MEM1 at the fastest speed. I understand that. This delay is due to packet contention on the router network. Therefore, as the number of stages of the network bus increases, the delay further increases and a situation occurs in which the latency of DMAC memory access exceeds the allowable time.

  On the other hand, FIG. 11 shows how DMAC access is delayed when DMAC, ENC, and DEC make an access request to MEM1 while adjusting the transmission interval. As shown in FIG. 11, when DMAC, ENC, and DEC adjust the transmission interval, the latency of DMAC is significantly shortened. ENC and DEC transmit packets 1 to 6 with a transmission packet interval. On the other hand, the DMAC transmits the packet 7 at a timing when no packet is transmitted from the ENC and the DEC. The packet 7 transmitted by the DMAC arrives at the MEM 1 in two cycles, which is the shortest latency, using the empty cycle between the transmission packets from the ENC and the DEC.

  In this embodiment, ENC and DEC dynamically determine the packet transmission interval using the state of access load and the degree of progress of access. The timing of determination is determined by the number of cycles required for calculation of the transmission interval, the minimum number of packet transfer cycles defined by the operation hardware resources and the access flow in operation.

  FIG. 12 shows a basic configuration of the NIC 120 on the initiator side. The NIC 120 is, for example, the NICs 1 to 4 in FIG. In view of the functions described below, the NIC 120 may be referred to as a “transmission interval control device”.

  The NIC 120 includes a packetization unit 121, a depacketization unit 122, a packet buffer 123, a packet transmission / reception unit 124, and a transmission interval control unit 125.

  The packetizing unit 121 receives data transmitted from the initiator, adds a packet header to the data, and packetizes the data. For example, the packetizing unit 121 receives the request transaction 10 (FIG. 5) transmitted from the initiator, and generates a packetized request transaction 12 (FIG. 6) by adding a packet header PH. This processing is also called packetization processing.

  The depacketizing unit 122 performs processing reverse to the processing of the packetizing unit 121. That is, the depacketizer 122 removes the packet header from the packet received from the router. This process is also called a depacketization process.

  The packet buffer 123 is a buffer provided for temporarily storing packets.

  The packet transmitting / receiving unit 124 performs processing related to packet transmission / reception. At the time of packet transmission, the packet transmitting / receiving unit 124 reads the packet data stored in the packet buffer 123 for each transmission data bus width, and performs packet transmission processing. When receiving a packet, the packet transmitting / receiving unit 124 reconstructs the packet by storing the data received for each received data bus width in the packet buffer 123.

  Details of the transmission interval control unit 125 will be described later in detail with reference to FIG.

  The packetization unit 121, the depacketization unit 122, the packet buffer 123, and the packet transmission / reception unit 124 are functions existing in a general NIC. The processing of the NIC 120 based on these components will be outlined.

  Processing at the time of packet transmission is as follows. The packetization unit 121 receives data from the initiator, adds a packet header to the data, and performs packetization processing. The packet buffer 123 temporarily stores the packet. The packet transmission / reception unit 124 reads the packet data held in the packet buffer 123 for each transmission data bus width, and performs packet transmission processing.

  Processing at the time of packet reception is as follows. The packet transmitting / receiving unit 124 receives data for each received data bus width and stores the data in the packet buffer 123, whereby the packet is reconstructed. The depacketizer 122 removes the packet header from the obtained packet, and outputs the remaining data to the initiator.

  Next, the transmission interval control unit 125 will be described.

  The transmission interval control unit 125 is a functional element unique to the NIC 120 according to the present embodiment.

  FIG. 13 shows a basic configuration of the transmission interval control unit 125. The transmission interval control unit 125 includes an allowable delay calculation unit 131, an adjustment method selection unit 132, and a transmission interval determination unit 133.

  The allowable delay calculation unit 131 calculates a communication interval adjustment range (allowable delay amount) that can ensure real-time performance based on the progress information of burst access. The progress information is information held by the allowable delay calculation unit 131. Specifically, the progress information is the remaining number of burst accesses (access remaining number). In the following description, the term “remaining access number” will be mainly used.

  The adjustment method selection unit 132 selects a communication interval adjustment method based on the load information, and generates interval control information.

  The transmission interval determination unit 133 determines a communication interval based on the adjustment range information and the interval control information, and generates data transmission permission information.

  Here, an overview of processing of the NIC 120 on the initiator side including the transmission interval control unit 125 will be described.

  FIG. 14 is a flowchart showing a processing procedure of the NIC 120 on the initiator side.

  In step S100, the transmission interval control unit 125 acquires information indicating the minimum packet size a. The minimum packet size refers to the minimum size of a packet transmitted to the target for data access. The minimum packet size a may vary depending on the type of data access and the target.

  In step S102, the allowable delay calculation unit 131 sets the control interval p based on the minimum packet size a, the parallel number N of the division circuits provided in the allowable delay calculation unit 131, and the number of cycles n required for each division circuit to calculate. Calculate. Note that the parallel number N and the cycle number n are held in the allowable delay calculation unit 131 as described later with reference to FIG.

  In step S104, the allowable delay calculation unit 131 obtains the allowable delay I at a timing based on the control interval p. The “timing based on the control interval p” means that every time p packets are transmitted. The obtained allowable delay I is used as adjustment range information indicating how much packet transmission delay can be tolerated.

  When the adjustment range information is obtained, the transmission interval determination unit 133 executes the process of step S106. In step S106, the transmission interval determining unit 133 receives the adjustment range information and the network bus load (latency) information. Then, the packet transmission interval is adjusted according to the adjustment range and the load (latency). If it matches the packet transmission interval, the transmission interval determination unit 133 determines whether to permit or prohibit transmission of data (request transaction corresponding to the access request) from the initiator, and provides information indicating the result. Output.

  In step S108, the packetizing unit 121 receives data from the initiator permitted to transmit data and packetizes it.

  In step S110, the packet transmitting / receiving unit 124 transmits the generated packet.

  The process from step S104 to S110 will be specifically described as follows.

  For example, it is assumed that the allowable delay I obtained at the timing based on the control interval p is negative. This means that no delay is allowed. At this time, every time a packet transfer cycle is completed, the transmission interval determination unit 133 permits transmission of data from the initiator (step S108), and the packet transmission / reception unit 124 transmits the next data (packet) without delay ( Step S110).

  On the other hand, when the allowable delay I is 0 or more, the adjustment method selection unit 132 determines the packet communication interval according to the load (latency) of the network bus at that time. If the load is relatively large, the network bus is congested, so the packet transmission interval is expanded. On the other hand, if the load is relatively small, the network bus is not congested, so the packet transmission interval is reduced. In accordance with the determined communication interval, the transmission interval determination unit 133 outputs information that permits or prohibits data transmission to the initiator.

  As can be understood from the above description, the control interval p indicates the timing at which the allowable delay I is recalculated. When the allowable delay I is obtained, processing for adjusting the packet transmission interval is performed. Therefore, it can be said that the control interval p is a parameter for adjusting the packet transmission interval.

  FIG. 15 shows a basic configuration of the allowable delay calculation unit 131. The allowable delay calculation unit 131 includes a calculation execution unit 141, a calculation result storage unit 142, an allowable delay calculation unit 143, and a control interval determination unit 144.

  The operation execution unit 141 performs predictive parallel processing of division execution that requires the number of cycles. In the present embodiment, it is assumed that the calculation execution unit 141 is provided in parallel. The number of operation execution units 141 provided in parallel is later represented by a symbol “N”.

  The calculation result storage unit 142 stores the calculation result until the transmission interval is calculated.

  The allowable delay calculation unit 143 calculates transmission interval adjustment range information.

  The control interval determination unit 144 determines an optimal control interval from the minimum packet size accessed from the initiator, the number of processing cycles consumed for the calculation of the calculation execution unit, and the number of hardware parallel processes.

  Hereinafter, the processing of the control interval determination unit 144 will be described with reference to FIG.

  FIG. 16 is a flowchart illustrating a processing procedure of the control interval determination unit 144.

  In step S200, the control interval determination unit 144 determines whether to update the control interval p. When the minimum packet size a is changed, the control interval determination unit 144 determines to update the control interval p. If it is not determined to update, the control interval determination unit 144 does not proceed to the next process.

  Information indicating the minimum packet size a is held in a register (not shown) on the NIC 120. Whether or not the minimum packet size a has been changed may be detected by the control interval determination unit 144 monitoring the register.

  In step S202, the control interval determination unit 144 obtains the control interval p using a ceiling function shown in Equation 8 described later.

  In step S204, the control interval determination unit 144 holds the obtained control interval p in an internal memory or a register (not shown).

  FIG. 17 shows an example of a register group for recording parameters managed by the transmission interval control unit 125. Hereinafter, the meaning of the parameters set in each register will be described.

  Tb is a cycle in which burst access occurs, and Tp is the number of cycles required for transaction transfer. For example, if a 128-byte transaction is transmitted on a 64-bit bus, the number of cycles is 128/64 * 8 = 16 cycles.

  Np is the number of accesses generated within a single burst period. Sb is a register for storing the number of cycles at the start time of the burst period, and Rp is the remaining number of accesses obtained by subtracting the number of accesses already generated from the number of accesses Np to be generated within the burst period. Rc is the number of remaining cycles until Rp access is completed. G is a transmission interval until the next access, and L is the latest latency.

  Parameters Tb, Tp, and Np determine the memory access characteristics required from the initiator. These are initialized on each register by the initiator prior to the start of access to the memory. The parameters Sb, Rp, Rc, G, and L are used to record internal parameters managed by the transmission interval control unit 125. Cleared to zero on each register when the chip is powered on or reset. Tc appearing in the following description is the current value of the cycle counter and represents the current time on the system. The cycle counter may be an n-bit counter that is cleared to zero when the chip is powered on or reset and incremented every clock cycle.

  Hereinafter, the operation of the transmission interval control unit 125 will be described.

  FIG. 18 is a flowchart illustrating a processing procedure of the transmission interval control unit 125. This process is repeated for each access request in the burst access period.

  First, when a transmission request from the initiator to the target is generated and the transmission interval control unit 133 detects that the NIC 120 has received a transaction, the processing is started. For example, the transmission interval control unit 133 monitors the packet buffer 123 (FIG. 12). The transmission interval control unit 133 detects the reception of the above-described access request and transaction by detecting the presence of transaction data. Alternatively, the above-described detection may be performed when the transmission interval control unit 133 receives a notification from the packet transmitting / receiving unit 124 or the packetizing unit 121.

  As described above, when an access request is detected, processing is started.

  In step S2, the transmission interval control unit 133 reads the remaining access number register Rp. If the remaining access number register Rp is Rp = 0, the process proceeds to step S4. If Rp = 1, the process proceeds to step S8. If the value of Rp is other than those, the process proceeds to step S6. The reason why the process is changed according to the value of the remaining access number register Rp is to perform an appropriate process according to the type of burst access.

  FIG. 19 shows the types of burst access. As shown in FIG. 19, when Rp = 0, it means that the head access is within the burst period. Further, when Rp = 1, it means that it is the last (final) access within the burst period. When the value of Rp is other than those, it means that the access is in a burst (intermediate access). In this embodiment, the contents of processing performed by each unit are different in each case so that an appropriate operation is performed.

Refer to FIG. 17 again. Step S4 is processing in the case of head access. The permissible delay calculation unit 131 performs the related parameter initialization processing according to Equations 2 to 5.

  Tb ′ in Equation 4 is a value obtained by subtracting a margin amount to be secured as a time margin from the burst period Tb. The initiator needs a time margin for performing data processing after completing all accesses within the burst period. The main factor that determines the time margin to be secured is the maximum number of cycles required for the processing. In a program in which a memory area for data storage and a memory area for data processing are separated, Tb 'and Tb can be set to the same value.

  When the process of step S4 is completed, the process proceeds to step S32.

  Next, the process of step S6 will be described. Step S6 is processing in the case of intermediate access.

In step S <b> 6, the allowable delay calculation unit 131 updates the remaining cycle number Rc according to Equation 6.

In step S10, the allowable delay calculation unit 131 calculates the allowable delay (or adjustment range) I according to Equation 7.

  The allowable delay calculation unit 131 notifies the value of the allowable delay I to the adjustment method selection unit 132 and the transmission interval determination unit 133 as adjustment range information.

  The calculation of the value of the allowable delay I can be roughly divided into two phases. The first phase is a phase for calculating 1 / Rp, and the second phase is a phase for calculating an allowable delay I by a product-sum operation. Needless to say, the calculation cost is higher in the first phase including division. In the present embodiment, the number of cycles required for the first phase is 9 cycles, and the number of cycles required for the second phase is 2 cycles. The first phase is executed by the calculation execution unit 141, and the second phase is executed by the allowable delay calculation unit 143.

  Subsequently, reference will be made to FIGS. In connection with the description of these drawings, the concept of “frit” is used below. "1 flit" is a data transmission unit that can be transferred every bus clock. The size of one flit is equal to or smaller than the size of one packet. In the present embodiment, it is assumed that one packet is divided into a plurality of flits and transmitted.

  The packet size is proportional to the number of cycles required to transfer one packet. If the number of cycles is determined, the packet size can be obtained from the product of the data size of 1 flit and the number of cycles.

  FIG. 20 is a timing chart when the minimum packet size for data access from the initiator is 9 flits. The uppermost rectangular waveform indicates the state of the bus clock. A symbol t written at the top indicates an elapsed time when one bus clock (one cycle) is a unit time.

  Each rectangle in the second row indicates a frit. In each rectangle, symbols using P and F such as “P0” and “F0” are shown. In this specification, P and F in one frit are represented by connecting them with a hyphen as “PF” for convenience. For example, the first frit is expressed as “P0-F0”.

  P0-F0 indicates the 0th flit constituting the 0th packet (packet 0) (header flit of packet 0), and P0-F8 indicates the 9th flit of the 0th packet (trailer flit of packet 0). . It can be seen that the timing for starting transmission of the next packet 1 (P1) is t = 10 at the shortest. Therefore, it is necessary that the allowable delay I has been updated at the time t = 10.

  The lowest level is a time (cycle) required for processing such as calculation. The division operation, which is the first phase, is started predictively at time t = −1 so that it is completed at timing t = 8. Thereafter, the product-sum operation is executed in the second phase, and the allowable delay I is calculated. Completion of the product-sum operation as the second phase means completion of calculation (update) of the allowable delay I. The calculation of the allowable delay I is completed at t = 10. Therefore, the adjustment range for determining the transmission interval of the subsequent packet 1 (P1) can be calculated within the time limit.

  Calculation for determining the transmission interval of the subsequent packet 2 (P2) is started. The timing at which the packet 2 is transmitted is t = 19 at the shortest. The first phase division is performed during the cycle period from t = 8 to t = 17. After consuming 2 cycles in the second phase, the allowable delay I is updated at t = 19. If such a calculation cycle can be secured, it is possible to calculate an allowable delay (adjustment range) for determining the transmission interval of the subsequent packet 3 within the time limit.

  FIG. 21 is a timing chart when a new data access with a packet size of 7 flits occurs from the initiator. The first calculation phase for packet 2 (P2) is completed at the timing t = 8, and the second phase is completed at t = 10. Therefore, it can be said that the adjustment range I for determining the transmission interval of the subsequent packet 2 (P2) can be calculated within the time limit.

  However, since the packet size is 7 flits, the transmission timing of packet 3 (P3) is t = 17 at the shortest. The first calculation phase is completed at t = 17, but it takes two more cycles to complete the second phase, resulting in a processing delay. Therefore, the value of the allowable delay I cannot be calculated by the shortest timing at which transmission of the packet 3 is started, and real-time performance cannot be ensured. According to this example, it can be seen that whether or not the adjustment range I can be calculated within the time limit depends on the packet size.

  FIG. 22 shows a timing diagram when the adjustment range can be calculated within the time limit by parallelizing the arithmetic circuit using two circuits A and B. The packet size is 7 flits as in the example of FIG. This configuration example corresponds to the configuration when the number of parallel executions of the arithmetic execution unit 141 in FIG.

  While the circuit A performs 1 / Rp prediction calculation until t = 8, and the adjustment range I is updated at t = 10, the parallelized circuit B is 1 / Rp between t = 6 and t = 17. A prediction calculation is performed, and the adjustment range I is updated. Thus, by parallelizing the division circuit that executes the first calculation phase, the calculation timing of the allowable delay I is not delayed, and real-time performance can be ensured. According to this example, it can be seen that whether the adjustment range I can be calculated within the time limit depends on whether the arithmetic circuits are parallelized.

  Here, a case is considered where data access is newly generated from an initiator in which one packet is composed of 4 flits. In this case, even if two parallel arithmetic circuits as shown in FIG. 22 are provided, the real-time property cannot be maintained.

  If such data access can occur, further division of the division circuit that executes the first operation phase is required. This results in an increase in circuit area. However, depending on the specifications of the product on which NoC is mounted, there may be a case where further parallelization of the arithmetic circuit is allowed.

  Therefore, in this embodiment, the update interval p of the adjustment range I is set to the minimum packet size transmitted by the initiator in accordance with the parallel number N of the division circuits that execute the first phase, which is implemented while receiving circuit area restrictions. The structure controlled according to a is shown. This makes it possible to ensure real time performance. The number of cycles required for each division circuit operation is n.

FIG. 23 shows a timing chart when the parallel number N = 3, the minimum packet size a = 2, and the number of cycles n required for the operation of the dividing circuit n = 9. At this time, the control interval determination unit 144 determines the control interval p by the following expression using a ceiling function.

  The ceiling function is a function that gives a minimum integer greater than or equal to x for a real number x. Under the above-mentioned conditions, since n / Na is 1.5, the control interval p is calculated as 2. At this time, the transmission interval control unit 125 monitors the packet buffer 123 and updates the transmission interval every time two packets are transmitted. In FIG. 23, the prediction calculation is started when the first flit of the two flits constituting the second packet is transmitted. In this way, the allowable delay I is updated every time a certain number of packets are transmitted, and the expansion and reduction of the transmission interval are controlled using the allowable delay I (FIG. 18). As a result, the remaining access number Rp decreases monotonously and 1 / Rp can be calculated predictively.

  FIG. 24 shows a timing chart when the minimum packet size transmitted by the initiator is changed from 2 flits (a = 2) to 4 flits (a = 4) during operation under the conditions shown in FIG.

  In general, the values of N, a, and n are stored in a register or the like on the NIC. The initiator updates the register when the minimum packet size changes. As a result, the transmission interval control unit 144 can receive a notification regarding the change of the above-described condition from the initiator or the NIC.

  When the transmission interval control unit 144 detects that the register storing the value of a has been changed or receives a notification that it has been changed, the transmission interval control unit 144 recalculates the control interval p again according to (Equation 8). Update. At this time, since p = 1, the transmission interval is recalculated for each packet, and the followability to the busy state of the bus is improved. By dynamically calculating the control interval with the best follow-up performance using the arithmetic circuit with the maximum number of parallel processings, which is the upper limit of mounting in this way, efficient control can be realized in securing real-time performance. .

  Refer to FIG. 17 again. In step S12, the adjustment method selection unit 132 determines whether the value I of the adjustment range information is non-negative or negative. If it is non-negative, the process proceeds to step S14. If negative, the process proceeds to step S16.

  In step S14, the allowable delay calculation unit 131 acquires load information in order to estimate the current load state of the network bus. As information used for grasping the load, the latency value L required for the latest transaction processing can be used. Latency is the time from when a request is made until a response is returned.

  An example of a specific method for obtaining the latency value L is as follows. First, the packet transmitting / receiving unit 124 records the value of the cycle counter Tc at the time of sending the requested transaction to the network bus in the packet header. When the target NIC sends a reply transaction, it records the cycle counter value recorded in the packet header of the previously received packet in the packet header of the reply transaction packet to be sent ( make a copy. Then, the allowable delay calculation unit 131 calculates the value of the cycle counter at the time when the reply transaction packet arrives at the NIC on the initiator side from the value of the copied cycle counter (= the value of the cycle counter at the time of sending the request transaction). It may be obtained by subtracting.

  In the above description, the time point when the initiator-side NIC 120 sends the requested transaction to the network bus is used as the starting point, and the elapsed time from the starting point is measured as the latency. However, for example, the time from when a request transaction is received from an initiator as a starting point until the response is returned after the initiator issues a request may be measured as latency.

  It can also be assumed that a plurality of initiators communicate directly with each other. In that case, the time from when the request transaction is received from the initiator to the other initiator as a starting point and the response from the initiator to the other initiator may be measured as the latency.

  In the next step S18, the adjustment method selection unit 132 compares the calculated latency value L with preset threshold values L1 and L2 (L1 <L2), and selects an adjustment method. When L> L2, the load is large, that is, the number of transmitted packets is large. Therefore, it is necessary to increase the transmission interval and decrease the packet density. On the other hand, when L ≦ L1, the load is small, that is, the number of transmitted packets is small. At this time, it is possible to reduce the transmission interval and increase the packet density. When L2> L ≧ L1, the load is medium.

  When L2> L ≧ L1, the process proceeds to step S20, and the transmission interval determination unit 133 performs adjustment to increase the transmission interval stepwise. The transmission interval G is obtained by G + K1.

K1 is a step adjustment range, and is defined as in Equation 9.

  According to this definition, the adjustment width of the transmission interval can be increased as the initiator has a smaller ratio of cycles in which data transmission is performed within the burst period. Note that k is an adjustment parameter, and is a constant determined by simulation or the like.

  Equation 8 will be described in more detail. (Np · Tp) included in Equation 8 is the product of the number of times of access Np generated within a single burst period and the number of cycles Tp required to transfer one packet. The number of cycles required. Therefore, when the burst period Tb is divided by (Np · Tp), the time length per cycle during the burst access period can be obtained. In the present specification, the value thus obtained is referred to as “burst access density”. K1 in Equation 8 is a value obtained by multiplying the density of burst access by the adjustment parameter k, and is a value corresponding to the density of burst access.

  When L ≦ L1, the process proceeds to step S22, and the transmission interval determination unit 133 performs adjustment to reduce the transmission interval step by step. The transmission interval G is obtained by G-K2.

  K2 is a step adjustment width, and may be K2 = 1, or may be defined in the same manner as K1 with K1 in Equation 8 as K2.

  If L> L2, the process proceeds to step S24, and the adjustment method selection unit 132 performs adjustment to increase the transmission interval in a non-step manner.

In step S24, the transmission interval determination unit 133 updates the transmission interval G according to Equation 9.

  Note that a = 0 in step S24 of FIG.

  Although non-stepwise adjustment is not essential, there is a possibility that it is possible to quickly escape from an overload state in which latency is not improved by stepwise adjustment. a is the lower limit of the random number generation interval, and may be a = I / 2 or a = K1. The random probability distribution may be a uniform distribution.

  The adjustment method selection unit 132 notifies the transmission interval determination unit 133 of the determined adjustment method as interval control information. Thereafter, the process proceeds to steps S26 and S28.

  In step S <b> 26, the transmission interval determination unit 133 compares the transmission interval G with the allowable delay I. When the transmission interval G is smaller than the allowable delay I, the process proceeds to step S30, and the transmission interval G is recorded. When the transmission interval G is equal to or greater than the allowable delay I, the process proceeds to step S28, where the allowable delay I is set as the transmission interval G. In step S30, the transmission interval G is recorded.

  In this example, two threshold values L1 and L2 are provided, but this is an example. The threshold may be only L1. At this time, when L> L1, adjustment to increase the transmission interval stepwise may be performed, and when L ≦ L1, adjustment to decrease the transmission interval stepwise may be performed.

  At this time, the transmission interval G can be obtained by the following process.

First, when the transmission interval is increased stepwise (L> L1), the transmission interval determination unit 133 updates the transmission interval G according to Equation 10.

  K1 is as shown in Equation 9 above.

When the transmission interval is reduced stepwise (L ≦ L1), the transmission interval determination unit 133 updates the transmission interval G according to Equation 12.

  K2 may be set to 1 or may be defined as in Equation 9.

  It should be noted that “min” in Equations 11 and 12 includes the processing of Steps S26 and S28 in FIG.

  The transmission interval determination unit 133 has a decrement counter inside, and asserts a transmission permission signal (Assert) only when the value held by the decrement counter is zero so that the initiator can issue a request transaction. When a value other than zero is written to the decrement counter, the transmission permission signal is negated, and the initiator waits for memory access until a new request transaction can be issued. The value of the decrement counter gradually approaches zero by being decremented each time the cycle counter is incremented.

  In step S32 executed in the case of the head access, the remaining access number Rp is decremented (Rp = Rp-1), and Tp + G is written in the decrement counter in step S34. In step S38, the transmission interval determination unit 133 sets the transmission permission signal to “DISABLE”. This prohibits the issue of a request transaction from the initiator within the Tp + G cycle.

  In step S16 executed in the case of intermediate access, when the transmission interval determination unit 133 detects that the value of the allowable delay I is negative based on the adjustment range information, the transmission interval determination unit 133 ensures the real-time property of the processing performed by the initiator. Therefore, the transmission interval G is updated to G = 0. Thereafter, the process proceeds to step S30, and the value of the transmission interval G is recorded. In the next step S32, the remaining access number Rp is decremented (Rp = Rp−1), and Tp + G is written in the decrement counter in step S34. In step S38, the transmission interval determination unit 133 sets the transmission permission signal to “DISABLE”. This prohibits the issue of a request transaction from the initiator within the Tp + G cycle.

  In step S8 executed in the case of the last access, the transmission interval determination unit 133 clears the remaining access number Rp to zero, and writes Sb + Tb to the decrement counter in step S36. In step S38, the transmission interval determination unit 133 sets the transmission permission signal to “DISABLE”. This prohibits the issue of a request transaction from the initiator within the Tp + Sb cycle.

  Thereafter, when it is detected in step S40 that the counter has been reset, in step S42, the transmission interval determination unit 133 sets the transmission permission signal to “ENABLE”. Thereby, the issuing of the request transaction from the initiator is permitted.

  By reducing not only the transmission interval but also the Np number of accesses, it is possible to complete Np accesses at an early stage and accommodate the access of other initiators that will occur later in the bus bandwidth as much as possible. For example, since the CPU in FIG. 4 is used for user interaction, Internet browsing, and the like, it is difficult to predict in advance the amount of memory access that occurs to execute the process specified by the user. Even in such a case, if each initiator completes all memory accesses at an early stage by reducing the transmission interval, the CPU processing access activated by the user can be accommodated in the bus band. The utilization efficiency of is improved.

As described above, when the transmission interval control unit 125 operates, it is possible to ensure real-time performance on the network bus sharing the link between the initiators, and it is possible to improve the utilization efficiency of the bus bandwidth. FIGS. 25 and 26 are modeled on the access of ENC, DEC, and DMAC, and the magnitude of latency is compared and evaluated by a software simulator. The horizontal axis represents time (cycle clock value), and the vertical axis represents latency value (unit: cycle). The access models for the three types of initiators used were set as follows.
ENC: Tb = 4000, Np = 250, Tp = 4 (gray)
DEC: Tb = 4000, Np = 250, Tp = 4 (gray)
DMAC: Tb = 400, Np = 4, Tp = 4 (black)

  FIG. 25 shows packet latency results when transmission interval control is not performed. It can be seen that when burst access of ENC and DEC is started from the 0th cycle, the latency increases with a constant slope and increases to about 850 cycles. The latency of DMAC memory access performed while the bus is overloaded by burst access is similarly increased due to the effect of burst access.

  On the other hand, FIG. 26 shows packet latency results when transmission interval control according to the present embodiment is performed. In the burst access of ENC and DEC started from the 0th cycle, the transmission interval is controlled as the latency increases, and the latency is suppressed to about 50 cycles. For this reason, it can be seen that the DMAC access is completed with a low latency due to the empty cycle created because the transmission interval is controlled. Since the transmission interval is controlled to be reduced, it is understood that all 4000 accesses of ENC and DEC to be executed between 0 and 4000 cycles are completed within 2000 cycles. . As described above, it can be confirmed by simulation that the real-time property is secured for each initiator and the utilization efficiency of the bus bandwidth is improved.

  In the present embodiment, the transmission interval control unit has been described as a part of the NIC on the initiator side, but may be located outside the NIC functional block. Further, although the fly network is assumed as the topology of the network bus connecting the initiator and the target, other topologies such as a mesh network and a torus network may be used. In this embodiment, the case where there are a plurality of targets is described, but a single target may be used.

(Embodiment 2)
In the present embodiment, the number of operation cycles n required to execute the first operation phase described in the first embodiment, the minimum packet size a transmitted by the initiator, and the control interval p indicating the required control granularity are set in the circuit. It is defined as a required specification at the time of design. Thereby, the required parallel number of arithmetic circuits can be determined from the relational expression shown in (Equation 13).

  Since the circuit mounting scale and mounting area are determined by N, it can be used for estimating the circuit scale at the time of designing, and can also be used as a design technique or a design tool.

  For example, it is considered that a designer is strongly required to control the transmission interval for each transmission of one packet. In that case, the control interval p may be fixed to 1. In this way, it is possible to design a transmission interval control device having an optimal number of parallel arithmetic circuits even under conditions where the value of p does not change.

  The present invention is not only implemented as a NIC or transmission interval control device mounted on a chip (NoC), but also as a simulation program that performs design and verification for mounting on a chip. Such a simulation program is executed by a computer. In the present embodiment, each component shown in FIGS. 12, 13, and 15 is implemented as an object class on the simulation program. Each class implements an operation corresponding to each component of the above-described embodiment on a computer by reading a predetermined simulation scenario. In other words, the operation corresponding to each component is executed in series or in parallel as a processing step of the computer.

  For example, in order to obtain the optimum parallel number N of the parallel arithmetic circuit, the user inputs the value of the predetermined control interval p to the above-mentioned computer, and is assumed to be the smallest packet transmitted by the initiator. What is necessary is just to input the size a and the processing time n required for execution of the parallel arithmetic circuit. The computer can determine the optimum number N of parallel arithmetic circuits by substituting them into the above-described equation 13.

  The present invention is applicable to a packet communication type bus on a semiconductor LSI that performs real-time processing on various embedded devices such as AV home appliances such as TVs and recorders and mobile devices such as mobile phones. For example, the present invention can be used as a transmission interval control device, a control method, and a control program for efficiently communicating a plurality of initiators sharing a bus by controlling the packet transmission interval.

121 packetization unit 122 depacketization unit 123 packet buffer unit 124 packet transmission / reception unit 125 transmission interval control unit 131 allowable delay calculation unit 132 adjustment method selection unit 133 transmission interval control unit 141 calculation execution unit 142 calculation result storage unit 143 allowable delay calculation Unit 144 Control interval determination unit

Claims (7)

In a semiconductor circuit having a networked bus through which a plurality of packets are transmitted, a control device that controls the transmission timing of each packet and transmits each packet to the bus,
An allowable delay calculation unit that calculates an allowable delay indicating an allowable transmission delay amount of a packet to be transmitted afterwards at a timing determined according to a transmission completion time of a predetermined number of packets, and outputs as an adjustment range information;
A transmission interval determination unit that determines a transmission interval of each packet based on at least the adjustment range information, and permits or prohibits transmission of data by an adjacently connected initiator according to the determination result;
A control device for controlling a transmission interval, comprising: a transmission / reception unit configured to transmit, to a bus, at least one packet generated based on data received from the initiator permitted to transmit the data. The allowable delay calculation unit includes:
N operation execution units in parallel, each of which takes time n to execute a predetermined operation;
A control interval determining unit that calculates a control interval p based on a minimum size a of packets transmitted to the bus, a parallel number N of the operation execution units, and the time n, and the predetermined number is the control The control device according to claim 1, defined by the interval p. The control device according to claim 2, wherein the control interval determination unit determines the control interval p according to an expression shown in the following formula 1.

  The control device according to claim 1, wherein the transmission interval determination unit determines a transmission interval of each packet based on information on the load L of the bus in addition to the adjustment range information. When the load L is greater than a predetermined value, the transmission interval determination unit expands the transmission interval of each packet,
The control device according to claim 4, wherein when the load L is equal to or less than the predetermined value, the transmission interval determination unit reduces the transmission interval of each packet. Other initiators or targets are connected to the bus,
The transmission interval control unit obtains a latency, which is a time from when an access request is transmitted to the other initiator or the target until a response is returned, using the transmission / reception unit, and uses it as a load on the bus The control device according to claim 4. In a semiconductor circuit having a networked bus through which a plurality of packets are transmitted, the number N of arithmetic circuits provided in parallel in a control device that controls the transmission timing of each packet and transmits each packet to the bus A design method for determining,
The controller is
An allowable delay calculation unit that calculates an allowable delay indicating an allowable transmission delay amount of a packet to be transmitted afterwards at a timing determined according to a transmission completion time of a predetermined number of packets, and outputs as an adjustment range information;
A transmission interval determination unit that determines a transmission interval of each packet based on at least the adjustment range information, and permits or prohibits transmission of data by an adjacently connected initiator according to the determination result;
A transmission / reception unit for transmitting to the bus at least one packet generated based on the data received from the initiator permitted to transmit the data;
The allowable delay calculation unit is
N arithmetic circuits in parallel, each of which takes time n to execute a predetermined operation;
A control interval determining unit that calculates the control interval p, which is the predetermined number, based on the minimum size a of packets transmitted to the bus, the parallel number N of the arithmetic circuits, and the time n,
Inputting a value of a predetermined control interval p;
Obtaining a predetermined minimum value of size a and the value of time n;
A step of determining a parallel number N of the arithmetic circuits by an expression shown in the following equation (2):

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