KR101382606B1 - Apparatus and method for task mapping of hybrid optical networks on chip and hybrid optical networks on chip system using the same - Google Patents

Abstract

When task-mapping a hybrid optical network-on-chip which comprises a plurality of processing elements (PEs), a plurality of routers matched by PE, and optical links and electrical links forming paths between the routers, a method of the present invention comprises modeling a task characteristic graph by defining a relation between a plurality of tasks and the data sizes of the tasks; modeling a PE characteristic graph by defining the arrangement of the PEs and connection states between the PEs; performing mapping modeling by temporarily mapping the task characteristic graph on the PE characteristic graph repeatedly; and mapping a task by PE according to a mapping modeling result which has the minimum value of path overlap of optical links between tasks among the mapping modeling results. [Reference numerals] (100) Processing element; (200) Router; (300) Optical link; (400) Electrical link; (500) Task-mapping device

Description

Task mapping device and method of hybrid optical network on chip, and hybrid optical network on chip system using same

The present invention relates to an apparatus and method for mapping a task to a processing element (PE) in a hybrid optical network-on-chip (HONoC) environment, and a HONoC system using the same.

Due to the limitation of power efficiency versus performance of single core processors, a multi-processor system-on-chip (MPSoC) using multiple cores has been developed. In such a multi-processor system-on-chip, if the existing bus structure is applied, bottlenecks may occur and overall system performance improvement may be reduced. As a result, Network-on-Chip (NoC), which applies the concept of On-chip Network (OCN) to an advanced SoC structure that integrates hundreds of cores and IP (Intellectual Property), Appeared. For example, realistic multimedia and user interface / user experience (UI / UX) have become important in recent years, and the application of NoC is greatly considered as the demand for high parallelism increases in the UHD-class next-generation TV which requires ultra high resolution. .

On the other hand, since NoC is a structural change in terms of topology and protocol, an approach that takes into account the physical connection medium is required to cope with the limitations of the existing semiconductor process / device technology. Accordingly, a hybrid optical network-on-chip (hereinafter, referred to as " hybrid optical < RTI ID = 0.0 > NoC ") & HONoC).

For example, a method of transmitting large payload data through OI in a mesh topology and transmitting control packets and routing packets through EI has been proposed. In addition, a method of improving transmission efficiency by using OI for long path communication and EI for short path communication has been proposed. The chip is composed of two layers using TSV (Through-Silicon-Vias), which transmits payload data through the optical network at one layer and control packet transmission and optical routing at the other layer. The method has been proposed. In addition, a method of configuring a cluster in units of four cores and transmitting data by OI between clusters to the EI within the cluster has also been proposed.

In the HONoC, when the optical signal is routed through the packet switching method, each router must convert the optical signal into an electrical signal and determine the destination through the routing process. Therefore, the latency is rather higher than that of the EI based NoC The circuit switching network is configured to set the path of the OI through the EI.

Therefore, simultaneous transmission is impossible when some of the independent transmission paths of a plurality of data overlap each other, causing a problem that other transmissions must wait until one transmission is completed. In other words, as circuit switching is used in HONoC, as network traffic and network size increase, the probability of path collisions increases more rapidly, and if the path collisions are not properly controlled, overall system performance decreases drastically. In addition, latency unfairness is aggravated when collisions occur with large data transmission paths.

In the existing NoC, various mapping algorithms for assigning a task to a processing element (PE) have been studied for optimization of performance and power consumption. For example, how to address and solve communication bandwidth constraints as a linear problem, how to know the energy needs of each task and the performance requirements for communication, and how to map them using branch-and-bound, to perform the actual task Slack-budgeting task mapping method considering time constraints and mapping using ILP (Integer Linear Programming) to minimize energy consumption in heterogeneous multiprocessor NoC.

In this regard, Korean Patent Registration No. 714073 (entitled "On-chip Network Automatic Generation Method Without Contention of Communication Resources"), in the SoC design, a traffic graph and a communication schedule for the traffic volume between the modules constituting the on- And automatically generates an optimal on-chip network without contention between communication requests.

However, these existing studies do not properly reflect the environment of the HONoC structure that requires the use of circuit switching through the application of optical interconnection (OI), there was a limit to the path collision control in the HONoC structure as described above.

In order to solve the above-mentioned problems of the prior art, an embodiment of the present invention is a task mapping apparatus and method for mapping a task to a PE by optimizing the latency cost caused by the optical path collision in the HONoC structure, To provide a HONoC system using this.

It should be understood, however, that the technical scope of the present invention is not limited to the above-described technical problems, and other technical problems may exist.

According to an aspect of the present invention for achieving the above technical problem, a plurality of processing elements (PE), a plurality of routers matched for each PE and an optical link and an electrical link forming a path between the routers The task mapping apparatus of the configured hybrid optical network-on-chip (HONoC) may include a task modeling unit configured to model a task characteristic graph by defining a relationship between a plurality of tasks and data sizes of the plurality of tasks; A processing element modeling unit configured to model PE characteristic graphs by defining the arrangement of the plurality of PEs and a connection state between PEs; And mapping modeling mapping the task characteristic graph onto the PE characteristic graph a plurality of times, wherein mapping of the optical link between the plurality of tasks among the plurality of mapping modeling has a minimum value according to a result of mapping modeling. It includes a task mapping unit for mapping the task for each PE.

In addition, a hybrid optical network on chip including a plurality of processing elements (PEs), a plurality of routers matched for each PE, and optical links and electrical links forming a path between the routers according to another aspect of the present invention. A task mapping method through a task mapping apparatus of an optical network-on-chip includes: modeling a task characteristic graph by defining a relationship between a plurality of tasks and data sizes of the plurality of tasks; Modeling a PE characteristic graph by defining a batch of the plurality of PEs and a connection state between the PEs; Performing mapping modeling for temporarily mapping the task characteristic graph onto the PE characteristic graph a plurality of times; And mapping the tasks for each PE according to a mapping modeling result in which path overlap of the optical link has a minimum value among the plurality of tasks in the mapping modeling.

In addition, according to another aspect of the present invention, a hybrid optical network-on-chip system includes a plurality of processing elements (PEs); A plurality of routers matched for each PE and configured to process circuit switching for transmission of data between the PEs through an optical link and to process packet switching for routing between PEs through an electrical link; And mapping modeling which temporarily maps a plurality of tasks to the plurality of PEs a plurality of times, and in accordance with a result of mapping modeling in which path overlap of the optical link has a minimum value among the plurality of tasks among the plurality of mapping modelings. It includes a task mapping device for mapping the task for each PE.

According to any one of the above-described problem solving means of the present invention, in the circuit switching-based HONoC environment, the path collision frequency is reduced without increasing the routing complexity of the optical path, and in the worst case even during the path collision. This has the effect of ensuring path latency to a minimum value.

1 is a view for explaining a hybrid optical network on a chip system according to an embodiment of the present invention.
2 is a block diagram illustrating a configuration of a task mapping apparatus for a hybrid optical network on chip according to an embodiment of the present invention.
3 is a diagram illustrating an example of a task characteristic graph according to an exemplary embodiment of the present invention.
4 is a block diagram illustrating a configuration of a task mapping unit according to an embodiment of the present invention.
5 is a pseudo code of a mapping algorithm for delay time optimization in a hybrid optical network on chip environment according to an embodiment of the present invention.
6 is a pseudo code of a variable initialization part of a mapping algorithm according to an embodiment of the present invention.
7 is a flowchart illustrating a task mapping method of a hybrid optical network on chip according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, which will be readily apparent to those skilled in the art. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly illustrate the present invention, parts not related to the description are omitted, and similar parts are denoted by like reference characters throughout the specification.

Throughout the specification, when a part is referred to as being "connected" to another part, it includes not only "directly connected" but also "electrically connected" with another part in between . Also, when an element is referred to as "comprising ", it means that it can include other elements as well, without departing from the other elements unless specifically stated otherwise.

1 is a view for explaining a hybrid optical network on a chip system according to an embodiment of the present invention.

2 is a block diagram illustrating a configuration of a task mapping apparatus for a hybrid optical network on chip according to an embodiment of the present invention.

First, as shown in FIG. 1, the hybrid optical network on chip (HONoC) system 10 according to an embodiment of the present invention includes a plurality of processing elements (PEs) 100, HONoC consisting of a plurality of routers 200 matched with each PE 100, an optical link 300 forming an optical path between each router 200, and an electrical link 400 forming an electrical path between each router. It includes. In addition, the HONoC system 10 is configured to include a task mapping device 500 for mapping a task to a plurality of PE 100 on the HONoC, respectively.

In this case, FIG. 1 shows that the HONoC system 10 according to the embodiment of the present invention is configured as a HONoC in the form of a mesh topology. The topology type of the HONoC according to the embodiment of the present invention may be variously set.

On the other hand, in an embodiment of the present invention, the optical link 300 is an optical interconnect (OI), and a large payload packet may be communicated as an optical signal between the routers 200 having an optical path. Is a link. In addition, the electrical link 400 is an electrical interconnect (EI), which is capable of communicating a routing packet for establishing an optical path between a source router and a destination router among the plurality of routers 200 as an electrical signal. Link

Specifically, the HONoC system 10 according to an embodiment of the present invention performs data communication between the PE 100 through the following operation.

First, the originating router transmits a routing packet to the destination router through the electrical link 400. Then, the router receiving the routing packet checks the routing packet and routes it to the next preset router on the HONoC, or, if it is the final destination, routes to the PE 100 that is matched with itself and simultaneously pays the payout. Set optical path for load packet transmission.

At this time, when the routing packet arrives at the final destination router, the destination router transmits a response packet (ie, Ack) to the source router through the electrical link 400. Then, the source router receiving the response packet Ack causes the desired data (ie, payload packet) to be transmitted over the established optical link 300. That is, data communication through the optical link 300 is performed between the PE 100 matched with the source router and the PE 100 matched with the destination router.

Finally, when data transmission from the source router is completed, the source router transmits the path release packet through the electrical link 400 to release the path on the optical link 300 that has been established to the destination router.

As described above, the routing operation for performing data communication between the PEs 100 may be based on a routing algorithm preset for each router 200. In an embodiment of the present invention, the task mapping apparatus 500 to be described below may control a routing operation for data communication of each router 200.

On the other hand, in the HONoC system 10 according to an embodiment of the present invention, prior to performing the data communication operation of the HONoC described above, the task mapping apparatus 500 performs a plurality of tasks according to the application Mapping process to the PE (100).

The task mapping apparatus 500 according to an embodiment of the present invention maps a task for each PE 100 according to a result of mapping modeling in which the path overlap of the optical link 300 has a minimum value among a plurality of tasks.

At this time, the task mapping apparatus 500 is based on the maximum data size of a plurality of tasks, and the bandwidth of the optical link 300 connected through the router 200 for each of the plurality of PE (100), the path delay according to the mapping modeling Calculate the cost. The task mapping apparatus 500 maps the plurality of tasks to the plurality of PEs 100 according to the mapping modeling result of which the path delay cost is the minimum value.

In detail, as illustrated in FIG. 2, the task mapping apparatus 500 according to the exemplary embodiment may include a task modeling unit 510, a processing element modeling unit 520, a task mapping unit 530, and data communication. It is configured to include a control unit 540.

The task modeling unit 510 models a task characteristic graph by defining relationships and data sizes between tasks of the plurality of tasks.

Specifically, FIG. 3 is a diagram illustrating an example of a task characteristic graph according to an embodiment of the present invention.

In FIG. 3, a communication pattern between a plurality of tasks included in an application and a size of data to be processed in each task are modeled using a directed acyclic graph (DAG).

At this time, it can be expressed as G = <V, E> by DAG notation. Here, V may be expressed as v _i ∈V as a task, and E may be expressed as e _{i , j} ∈E, in which v _i transmits data to v _j as data communication between tasks.

As illustrated in FIG. 3, e _{i , j} may have two values _, BW (e _{i , j} ) and CV (e _{i , j} ). BW (e _{i, j} ) is the bandwidth of communication when v _i sends data to v _j , and CV (e _{i , j} ) is the maximum data processed in one communication when v _i sends data to v _j Amount (ie data size).

As such, the communication pattern and the characteristics of the task may be modeled as a task characteristic graph to perform mapping between the task and the PE 100 based on the characteristics of the plurality of tasks.

2, the processing element modeling unit 520 models the PE characteristic graph by defining the arrangement of the plurality of PEs 100 and the connection state between the PEs 100.

In detail, as in the case of modeling the task characteristic graph, the PE characteristic graph may be modeled by defining an arrangement state and a connection state of the PE 100.

In this case, the PE characteristic graph may be expressed as P = <U, F> by DAG notation. Here, U may be expressed as u _j ∈U as PE 100, and F may mean a connection between PE 100, and a connection between u _i and u _j may be expressed as f _{i , j} ∈F.

The task mapping unit 530 maps the task characteristic graph modeled through the task modeling unit 510 onto the PE characteristic graph modeled through the processing element modeling unit 520.

In this case, the task mapping unit 530 performs mapping modeling for temporarily allocating a plurality of tasks to the plurality of PEs 100, and minimizes path overlap of the optical link 300 among the plurality of tasks among the plurality of mapping modelings. According to the result of mapping modeling having a value, the task is finally mapped for each PE 100.

For reference, an operation of mapping the task and the PE 100 by the task mapping unit 530 will be described in detail with reference to FIGS. 4 to 6.

The data communication controller 540 controls data communication between the PEs 100 according to execution of an application including a plurality of tasks.

In detail, the data communication controller 540 controls at least one of the plurality of routers 200 to process packet switching for routing with a destination router set by any one task through the electrical link 400. In addition, the data communication controller 540 controls the circuit switching for the communication of the payload packet with the destination router through the optical link 300.

Hereinafter, the configuration and task mapping scheme of the task mapping unit 530 according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 4 to 6.

4 is a block diagram illustrating a configuration of a task mapping unit according to an embodiment of the present invention.

As shown in FIG. 4, the task mapping unit 530 according to an embodiment of the present invention includes a mapping modeling module 531, a path delay cost calculation module 532, and a mapping processing module 533. .

The mapping modeling module 531 processes mapping modeling for temporarily allocating a plurality of tasks to the plurality of PEs 100 a plurality of times. In this case, the mapping modeling module 540 temporarily assigns a plurality of tasks to the plurality of PEs 100 by applying a different mapping model for each of the plurality of mapping modelings.

In detail, the mapping modeling module 531 maps the task characteristic graph to the PE characteristic graph through a preset mapping function.

For example, use the preset mapping function 'map ()' to map the task characteristic graph G = <V, E> to the PE characteristic graph P = <U, F>, which maps each task to PE (100). After mapping to) can be expressed by the following equation (1).

&Quot; (1) &quot;

In this case, when | V | ≤ | U |, the mapping is defined.

In one embodiment of the present invention, the calculation of the path delay cost through the path delay cost calculation module 532 to be described below is performed in parallel for each mapping modeling through the mapping modeling module 531.

The path delay cost calculating module 532 may map the path delay for each mapping modeling based on the maximum data size for each task and the bandwidth size of the optical link 300 connected through the router 200 for each of the plurality of PEs 100. Calculate the cost.

In detail, in the mapping modeling of each round, the path delay cost calculating module 532 performs the path delay cost of the corresponding task (that is, the temporarily allocated task) whenever a plurality of tasks are sequentially temporarily assigned. Path delay cost ').

Here, the first path delay cost is a value required to process data communication of the task after data communication of at least one other task pre-allocated in the mapping modeling of the turn is completed. That is, when a path overlap on the optical link 300 occurs between the task and another preassigned task, the first path delay cost of the task has a value of zero or more.

At this time, the path delay cost calculation module 532 accumulates the first path delay cost until the temporary allocation of the plurality of tasks is completed, and calculates the path delay cost for the corresponding mapping modeling as a result of accumulating the first path delay costs. (Hereinafter referred to as 'second path delay cost').

The path delay cost calculation module 532 matches and stores the optimal mapping model and the minimum path delay cost according to the result of mapping modeling having the minimum value among the path delay costs (ie, the second path delay cost).

At this time, the path delay cost calculation module 532 stops mapping modeling currently being performed when a path delay cost greater than a previously stored minimum path delay cost is generated during mapping modeling through the mapping modeling module 531. That is, when the second path delay cost of the mapping modeling already performed is stored as the minimum path delay cost, when the cumulative value of the first path delay cost of the mapping model currently being performed exceeds the previously stored minimum path delay cost. Stop mapping modeling in progress to prevent unnecessary mapping modeling.

In addition, the path delay cost calculation module 532 optimizes the mapping model and the path delay cost according to the result of the mapping modeling when the path delay cost when the mapping modeling is completed is smaller than the previously stored minimum path delay cost. Updates and stores the mapping model and the minimum path delay cost.

The mapping processing module 533 maps the plurality of tasks to the plurality of PEs 100 according to the mapping modeling result in which the path delay cost (ie, the second path delay cost) is the minimum value.

At this time, the mapping processing module 533 determines the optimal mapping model according to the mapping modeling result of the path delay cost having the minimum value among the mapping modelings, and maps the task for each PE 100 according to the determined optimal mapping model.

In FIG. 4, the task mapping unit 530 according to an embodiment of the present invention sets an optimal mapping model having a minimum latency cost through mapping modeling to map a plurality of tasks to a plurality of PEs 100. The way of doing this was explained.

The task mapping method of the task mapping unit 530 as described above will be described in detail through the algorithm shown in FIGS. 5 and 6.

5 is a pseudo code of a mapping algorithm for delay time optimization in a hybrid optical network on chip environment according to an embodiment of the present invention.

6 is a pseudo code of a variable initialization part of a mapping algorithm according to an embodiment of the present invention.

First, as shown in FIG. 5, in one embodiment of the present invention, the task mapping unit 530 may process a task mapping by performing a mapping algorithm implemented as an objective function.

In FIG. 5, a mapping algorithm implemented as a recursive function is performed, and this recursive function finds an optimal solution while attempting to sequentially map a task to the PE 100.

In this case, the 'allocation_calculation_path ()' function reflects the cost (i.e. latency cost) growth rate calculation and communication newly applied to each optical connection when the task is mapped to the PE 100, and is reflected in the 'returning_path ()' function. Restore communication to its previous state. If the cost after task mapping is completed is less than the minimum cost of the candidate solutions found so far, update it and the algorithm will be updated if the minimum cost becomes zero or all candidate solutions (ie mapping modeling) are considered. It ends. For reference, all variables of the mapping algorithm shown in FIG. 5 are initialized according to the initialization algorithm shown in FIG. 6. In this case, 'total_task' refers to the total number of tasks to be mapped and 'total_pe' refers to the number of PEs 100 present in the HONoC's network.

Such a mapping algorithm processes the mapping according to mapping modeling having a path delay cost of the minimum value among the path delay costs for each mapping modeling in order to reduce the overall delay time. That is, mapping is processed to minimize collision (ie, overlap) of communication paths for a plurality of tasks. In addition, as HONoc's network complexity and communication data increases, it is difficult to arrange (i.e., map) independently in consideration of all collision communication paths. Therefore, in the case of optical paths where a large amount of data is transmitted, transmission path overlap is eliminated first. Minimize and map inevitable collision paths to occur in small data transfers. As such, it can be written on a branch-and-bound basis to speed up operations by eliminating unnecessary considerations.

Specifically, according to the mapping algorithm shown in FIG. 5, in order to process the mapping according to an optimal condition when mapping a plurality of tasks to a plurality of PEs 100, a routing path is mapped (that is, tasks are mapped to PEs). And the problem of delay minimization that can minimize delay in optical link 300 for a plurality of tasks.

To this end, in one embodiment of the present invention, in order to define the problem of minimizing such a path delay cost, a problem with a delay time cost is defined based on a deterministic algorithm. In this case, a subset of the connection F used for communication from the task v _i to v _j mapped by the deterministic algorithm may be defined as L (e _{i , j} ).

In detail, while mapping modeling is performed through the mapping modeling module 531, after a plurality of tasks are temporarily allocated to the PE 100, e _{i , j} and a routing path (that is, the optical link 300) are established. All shared e _{i ' , j'} ∈E are defined as S _{i , j} . Accordingly, when L (e _{i , j} ) ∩ L (e _{i ', j'} ) ≠ φ, it is e _{i ' , j'} ∈S _{i , j} .

Based on the above definition, the delay time due to the path overlap of the optical link 300 may be defined as in Equation 2 below.

&Quot; (2) &quot;

In Equation 2, OptBW means the bandwidth of the optical connection, WLat (e _{i , j} ) is the transmission of their own data after the completion of the transmission of all other overlapped data when the path overlap (that is, collision) is completed When used, it refers to the delay time of the 'worst case'.

Through this, delay equalization and minimization problems can be defined as in Algorithm 1 below.

Algorithm 1

In Algorithm 1, Link_BW (f _{i , j} ) means the amount of optical bandwidth, which can be expressed by Equation 3 below.

&Quot; (3) &quot;

For reference, when the optical bandwidth requirement LinkBW (f _{i , j} ) performs a mapping exceeding the usable bandwidth OptBW, not only the task execution time is increased but also the network delay time of the HONoC itself is greatly increased. . For example, if Task1 transmits data occurring at 60Gbps to Task2, and the transmittable bandwidth is 40Gbps, the processing time of Task1 generating data is delayed, and the delay is further delayed as data is also accumulated. In other words, in order to optimize the optical delay time, it is necessary to reduce the time between transmissions sharing the path while the bandwidth requirement in each optical path does not exceed the actual optical bandwidth.

Accordingly, the mapping algorithm is set to give the cost to an infinite value if one f _{i , j} (ie, optical connection) exceeds the allowable bandwidth. This is to prevent this because exceeding the bandwidth can have a fatal effect on the delay time.

Meanwhile, the delay time cost for communication f _{i , j} may be calculated after v _i and v _j are mapped. At this time, the initial value of the latency cost is set to zero, and whenever the communication associated with the task (that is, the overlapping optical path) is accumulated as the latency cost after the task is mapped in mapping modeling, Is updated through 4.

&Quot; (4) &quot;

In Equation 4, cost is a previously accumulated first delay cost and cost 'is a first delay cost accumulated by additional communication. N is the number of communications with which a path is collided with an additional communication.

Through Equation 4, not only the delay time of the newly added communication but also the delay time increased by the newly added communication can be reflected.

In addition, in the mapping algorithm, in order to reduce the optimal solution search time, the smallest cost value (that is, the minimum latency cost) among candidate solutions found through each mapping modeling is stored. If the candidate solution currently being mapped already exceeds the stored cost (minimum delay time cost), it is determined that this mapping cannot be the optimal solution and does not search for other solutions derived from the candidate solution. This can reduce unnecessary mapping attempts. For reference, when all the tasks are mapped to the PE 100, the cumulative cost is an optimal solution if it is zero. This means that there is no communication with path collisions and bandwidth overruns, which in turn can be directly adopted as the optimal solution for the defined problem, eliminating the need for further mapping modeling.

Hereinafter, a method of performing task mapping in the HONoC system 10 according to an embodiment of the present invention will be described in detail with reference to FIG. 7.

7 is a flowchart illustrating a task mapping method of a hybrid optical network on chip according to an embodiment of the present invention.

First, a task characteristic graph is modeled by defining relationships and data sizes between tasks of a plurality of tasks (S710).

In addition, the PE characteristic graph is modeled by defining the arrangement of the plurality of PEs on the HONoC and the connection state between the PEs (S720).

At this time, the modeling step (S710, S720) may be changed in order, it may be performed at the same time. That is, in one embodiment of the present invention, it is not influenced by the relationship between the modeling of the task characteristic graph and the modeling of the PE characteristic graph.

Then, mapping modeling for temporarily mapping the plurality of tasks to the plurality of PEs is repeatedly performed based on the task characteristic graph and the PE characteristic graph (S730).

That is, mapping modeling for temporarily mapping a task characteristic graph onto the PE characteristic graph is performed a plurality of times, and the plurality of tasks are sequentially temporarily assigned to a plurality of PEs according to a different mapping model for each of the plurality of mapping modelings.

During the repetition of the mapping modeling, an optimal mapping model having a minimum value of the path overlap of the optical link on the HONoC between the plurality of tasks is detected (S740).

Specifically, the path delay cost is calculated based on the maximum data size for each task and the bandwidth size of the optical link connected through the router for each PE. At this time, whenever a plurality of tasks are temporarily temporarily assigned to a plurality of PEs, a first path delay of the corresponding task when a path overlap on the optical link occurs between the temporarily allocated task and at least one other task that is previously allocated The cost is calculated, and the second path delay cost for the mapping modeling is calculated by accumulating the first path delay costs for the plurality of tasks.

In addition, the optimal mapping model and the minimum path delay cost are matched and stored according to the result of the mapping modeling having the minimum path delay cost among the multiple mapping modeling. Select an optimal mapping model according to

 Specifically, if a path delay cost of a value greater than the previously stored minimum path delay cost is generated during the execution of any mapping modeling, the mapping mapping being performed is stopped, and the path delay in a state in which the mapping modeling is completed. If the cost is less than the previously stored minimum path delay cost, the mapping model and path delay cost according to the result of the mapping modeling are updated and stored with the optimal mapping model and the minimum path delay cost.

Thereafter, tasks are mapped for each PE 100 according to the optimal mapping model (S750).

That is, the tasks are mapped for each PE according to the mapping modeling result in which the path overlap of the optical link has a minimum value among the plurality of tasks in the mapping modeling.

On the other hand, in an embodiment of the present invention, after mapping the task for each PE, the method may further include controlling data communication between PEs according to execution of an application including a plurality of tasks. The step of controlling data communication between PEs may include controlling at least one of the plurality of routers to handle packet switching for routing with a destination router set by the task through the electrical link, And control the circuit switching for communication of the payload packet with the destination router via the optical link established.

The foregoing description of the present invention is intended for illustration, and it will be understood by those skilled in the art that the present invention may be easily modified in other specific forms without changing the technical spirit or essential features of the present invention. will be. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. For example, each component described as a single entity may be distributed and implemented, and components described as being distributed may also be implemented in a combined form.

The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

10: Hybrid optical network on-chip system
100: processing element
200: router
300: Optical path
400: electrical path
500: task mapping device

Claims (17)

Hybrid Optical Network-on-Chip (HONoC) configured with a plurality of processing elements (PEs), a plurality of routers matched for each PE, and optical and electrical links forming a path between the routers In the task mapping apparatus of
A task modeling unit configured to model a task characteristic graph by defining a relationship between a plurality of tasks and data sizes of the plurality of tasks;
A processing element modeling unit configured to model PE characteristic graphs by defining the arrangement of the plurality of PEs and a connection state between PEs; And
Mapping of the task characteristic graph onto the PE characteristic graph is performed a plurality of times of mapping modeling, and according to a result of mapping modeling in which the path overlap of the optical link has a minimum value among the plurality of tasks among the plurality of mapping modeling. Task mapping apparatus of a hybrid optical network on a chip comprising a task mapping unit for mapping the task for each PE. The method according to claim 1,
The task mapping unit,
A mapping modeling module configured to process the mapping modeling for temporarily allocating the plurality of tasks to the plurality of PEs a plurality of times;
A path delay cost calculation module configured to calculate a path delay cost for each mapping modeling based on the maximum data size for each of the plurality of tasks and the bandwidth size of the optical link connected through the router for each of the plurality of PEs; And
And a mapping processing module for mapping the plurality of tasks to the plurality of PEs according to the mapping modeling result of the path delay cost being the minimum value. 3. The method of claim 2,
The mapping modeling module,
And a task mapping apparatus for temporarily assigning the task according to a different mapping model for each of the plurality of mapping modelings. 3. The method of claim 2,
The path delay cost calculation module,
In the mapping modeling of each round, the temporary allocation for the case where a path overlap on the optical link occurs between the temporary allocated task and at least one other task that is pre-allocated whenever the plurality of tasks are sequentially temporarily allocated. Calculate a first path delay cost for the scheduled task,
The second path delay cost for the mapping modeling is calculated by accumulating the first path delay cost until the temporary allocation of the plurality of tasks is completed.
The first path delay cost is
And a value necessary to process data communication of the temporarily allocated task after data communication of the at least one other task is completed. 3. The method of claim 2,
The path delay cost calculation module,
According to the result of the mapping modeling having the minimum value of the path delay cost, the optimal mapping model and the minimum path delay cost are matched and stored,
During the mapping modeling through the mapping modeling module, if a path delay cost of a value greater than the previously stored minimum path delay cost is generated, the mapping modeling being performed is stopped,
When the path delay cost in the state where the mapping modeling is completed is smaller than the previously stored minimum path delay cost, the mapping model and the path delay cost according to the result of the mapping modeling are determined by the optimal mapping model and the minimum path delay cost. Task mapping device for a hybrid optical network on a chip to be updated and stored. The method according to claim 1,
Further comprising a data communication control unit for controlling the data communication between the PE in accordance with the execution of the application including the plurality of tasks,
The data communication control unit,
Control at least one of the plurality of routers to handle packet switching for routing with a destination router set by the task over the electrical link, and communicate payload packets with the destination router via the optical link. A task mapping device for a hybrid optical network on chip that controls to handle circuit switching for a circuit. Hybrid Optical Network-on-Chip task consisting of a plurality of processing elements (PEs), a plurality of routers matched for each PE, and optical and electrical links forming a path between the routers In the task mapping method through the mapping device,
Modeling a task characteristic graph by defining relationships between a plurality of tasks and data sizes of the plurality of tasks;
Modeling a PE characteristic graph by defining a batch of the plurality of PEs and a connection state between the PEs;
Performing mapping modeling for temporarily mapping the task characteristic graph onto the PE characteristic graph a plurality of times; And
And mapping the tasks for each PE according to a result of mapping modeling in which the path overlap of the optical link has a minimum value among the plurality of tasks during the mapping modeling. The method of claim 7, wherein
Performing the mapping modeling a plurality of times,
And sequentially assigning the plurality of tasks to the plurality of PEs sequentially according to a different mapping model for each of the plurality of mapping modelings. The method of claim 8,
The step of mapping the task for each PE,
Calculating a path delay cost based on the maximum data size for each of the plurality of tasks and the bandwidth size of the optical link connected through the router for each of the plurality of PEs;
Determining an optimal mapping model according to a result of mapping modeling of which the path delay cost is the minimum among the mapping modeling times; And
And mapping the task to each PE according to the optimal mapping model. The method of claim 9,
Computing the path delay cost,
The first path delay cost of the temporarily allocated task for the case where a path overlap on the optical link occurs between the temporary allocated task and at least one other task that is pre-allocated whenever the plurality of tasks are sequentially temporarily assigned. Calculating; And
Computing the first path delay cost for each of the plurality of tasks to calculate a second path delay cost for the mapping modeling,
The first path delay cost is
And a value required to process data communication of the temporarily allocated task after data communication of the at least one other task is completed. The method of claim 9,
Prior to determining the optimal mapping model,
Matching and storing an optimal mapping model and a minimum path delay cost according to a result of mapping modeling having a minimum path delay cost among the plurality of mapping modeling operations,
Computing the path delay cost,
During the execution of any one of the mapping modeling, if a path delay cost of a value greater than the previously stored minimum path delay cost is generated, the mapping modeling being performed is stopped,
If the path delay cost when the one of the mapping modeling is completed is less than the previously stored minimum path delay cost, the mapping model and the path delay cost according to the result of the one mapping modeling are determined as the optimal mapping model. And updating and storing the minimum path delay cost in a hybrid optical network on chip system. The method of claim 7, wherein
After mapping the task for each PE,
Controlling data communication between the PEs according to execution of an application including the plurality of tasks;
Controlling data communication between the PE,
At least one of the plurality of routers controls to handle packet switching for routing with a destination router set by the task through the electrical link, or with the destination router through the optical link set by the routing. A task mapping method of a hybrid optical network on chip system for controlling to handle circuit switching for communication of payload packets. In a hybrid optical network-on-chip system,
A plurality of processing elements (PE);
A plurality of routers matched for each PE and configured to process circuit switching for transmission of data between the PEs through an optical link and to process packet switching for routing between PEs through an electrical link; And
The mapping model for temporarily mapping a plurality of tasks to the plurality of PEs is performed a plurality of times, and the PE according to a result of mapping modeling in which the path overlap of the optical link has a minimum value among the plurality of tasks among the plurality of mapping modelings. Hybrid optical network on a chip system comprising a task mapping device for mapping the task for each. 14. The method of claim 13,
The task mapping device,
Calculating the path delay cost for each mapping modeling based on the maximum data size for each of the plurality of tasks and the bandwidth size of the optical link connected through the router for each of the plurality of PEs,
And mapping the plurality of tasks to the plurality of PEs according to a mapping modeling result of the path delay cost being the minimum value. 15. The method of claim 14,
The task mapping device,
In the mapping modeling of each round, the plurality of tasks are temporarily temporarily assigned to the PE,
Calculating a path delay cost for a case where a path overlap on the optical link occurs between the temporarily allocated task and at least one other task previously allocated,
And calculating the path delay cost for the mapping modeling by accumulating the calculated path delay cost until the temporary allocation of the plurality of tasks is completed. 16. The method of claim 15,
The task mapping device,
And performing the mapping modeling and performing the next mapping modeling when the accumulated path delay cost is greater than a minimum value of the calculated path delay cost during the mapping modeling. 14. The method of claim 13,
The task mapping device,
And hybridly map a plurality of tasks to the plurality of PEs according to different mapping models for each of the plurality of mapping modelings.

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