JP2000099313A - Multiplier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a repetitive multiplier which can increase its operation speed with a small-scale configuration. SOLUTION: When an 8-bit multiplicand X is multiplied by an 8-bit multiplier Y with addition of a code, the 2-bit code expansion is carried out. Meanwhile, the 2-bit 0 expansion is carried out with addition of no code. Thus, this multiplier M1 performs alternatively the multiplication with a code and the multiplication with no code. In such a constitution, a partial product generation circuit 22 generates a 1st partial product B0 corresponding to the least significant bit of the multiplier Y in a 1st cycle of operation. A partial product generation circuit 20 successively generates the partial products B1, B2... excluding the product B0 in each cycle and in the order of lower ranks. Then the partial product that is generated by the circuit 20 in the current cycle is added to the intermediate sum that is held in the preceding cycle, so that the partial products are cumulatively added together at the circuit parts (24 to 30). An augend selection circuit 32 supplies the product B0 received from the circuit 22 to each of said circuit parts in the 1st cycle only. As a result, the cumulative addition of partial products is possible in and after the 1st cycle and the number of cycles is decreased by one.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention divides a multiplication into a plurality of operation cycles, generates a partial product in each operation cycle, and accumulates the partial products, thereby obtaining a sum of all the partial products. The present invention relates to an iterative multiplier (iterative multiplier) for obtaining a multiplication result that is a sum.

[0002]

2. Description of the Related Art Conventionally, as a configuration of a multiplier used in a digital signal processing apparatus, for example, "Digital Signal Processing Handbook: pages 243 to 243" edited by the Institute of Electronics, Information and Communication Engineers.
Page 244 "or the like, a carry-save adder type parallel multiplier, a parallel multiplier using a secondary Booth's algorithm for generating partial products, or a wary tree (for adding partial products). Wallace Tree).

However, these parallel multipliers require a large number of partial product generation circuits and a large number of addition circuits. Therefore, when hardware is realized on an IC chip (ie, an IC chip).
Occupied area becomes large. Therefore, when it is desired to reduce the occupied area on the IC chip, a repetitive multiplier (iterative multiplier) that divides and executes multiplication in a plurality of operation cycles is used.

Here, a description will be given of a conventional iterative multiplier using a secondary Booth algorithm for generating a partial product. In this specification, “sign extension” means that the same bit as the most significant bit is added to the most significant bit of data, and “0 extension” means that the most significant bit of data is This means that a “0” bit is added. Then, both “sign extension” and “0 extension” are collectively referred to as “extension”.

First, Booth's algorithm is characterized in that two's complement multiplication (ie, a two's complement binary multiplication and signed multiplication) can be executed without correction. Above all, the second-order Booth algorithm is frequently used in this type of multiplier because the number of partial products can be halved.

The second-order Booth algorithm generates a partial product using the rule shown in the truth table of FIG. 7 when the multiplicand is X and the multiplier is Y. That is, bits forming the multiplier Y are represented by Y [i + 1], Y [i], Y [i-1].
(I = 0, 2, 4,...) And divided into groups of three consecutive bits in which one bit before and after is overlapped (see FIG. 9), and according to the bit sequence of each group,
"0", "+ X", "-X", "+ 2X", "-2X"
Is a partial product. However, []
The values in parentheses indicate the bit positions when the least significant bit in the data is the 0th bit. Thus, for example, Y
[7] represents the eighth bit of the bits constituting the multiplier Y, counting from the least significant bit Y [0] (in other words, when the least significant bit Y [0] is the first bit). It will be. Y [-1] is a dummy bit that does not actually exist and is regarded as "0".

In the multiplication using the secondary Booth's algorithm, the multiplicand and the multiplier are calculated by shifting each of the partial products generated according to the truth table of FIG. To get the product. As an example, FIG. 8 shows an example of multiplication of 8 bits × 8 bits in a two's complement display format. In this example, the bits forming the multiplier Y are divided into four groups G0 to G3 as shown in FIG. 9, and four partial products B0 to B3 are generated corresponding to the groups G0 to G3. Then, the four partial products B0 to B3 are shifted by 2 bits at a time as shown in FIG. 8 and cumulatively added, so that 15-bit data of 2's complement notation representing the product of the multiplicand X and the multiplier Y is obtained. Is obtained.

In FIG. 8, each bit of the partial products B0 to B3 is indicated by "O" and "●". 8 indicate sign extension bits necessary for digit alignment during addition. That is, in the second order Booth algorithm, the partial product is “−2X” or “2X” as shown in FIG.
X, the minimum required partial product to be generated is 9 (= 8 + 1) bits on the right side of the bit indicated by the mark “●” in FIG. In order to make the bit positions of the most significant bits of the partial products B0 to B3 coincide with each other, a sign extension bit indicated by the above-mentioned "□" is added.

Next, FIG. 10 is a block diagram showing the configuration of a conventional repetitive multiplier J1 for performing multiplication of 8 bits × 8 bits in a two's complement display format using a secondary Booth algorithm. FIG. 11 is a schematic diagram showing the multiplication operation of the repetitive multiplier J1. As shown in FIG. 10, an 8-bit multiplicand X and a multiplier Y are input to the repetitive multiplier J1, and the first cycle (first operation cycle), the second cycle (second operation cycle), An operation cycle signal indicating the number of operation cycles, such as a third cycle (third operation cycle) and a fourth cycle (fourth operation cycle), is input via the control line L.

The repetitive multiplier J1 changes the 8-bit multiplicand X input from the outside at the timing when the operation cycle signal from the control line L becomes a value indicating the first cycle (or the timing immediately before that). ) And the 8-bit multiplier Y input from the outside at the timing (or immediately preceding timing) at which the operation cycle signal from the control line L reaches the value indicating the first cycle. Each of the groups G0 to G3 shown in FIG. 9 of the multiplier holding circuit 102 to be held and the bits constituting the multiplier Y held in the multiplier holding circuit 102 in synchronization with the change of the operation cycle signal from the control line L. And a multiplier bit selection circuit 104 for selecting and outputting any one of the three bits in order from the lower one.

When the operation cycle signal reaches the value indicating the first cycle, the multiplier bit selection circuit 104 outputs three bits (Y [1], Y [1], Y [1], Y [1]) of the lowest group G0 shown in FIG.
[0], Y [-1]: However, Y [-1] is a dummy bit and outputs "0". When the operation cycle signal becomes a value indicating the second cycle, the second group G1 shown in FIG. 3 bits (Y [3]
, Y [2], Y [1]) and the operation cycle signal is 3
When the value indicates the cycle, three bits (Y [5], Y [4], Y [3]) of the third group G2 shown in FIG.
When the operation cycle signal reaches a value indicating the fourth cycle, the three bits (Y [7], Y [6]) of the fourth group G3 shown in FIG.
, Y [5]).

Further, this repetitive multiplier J1
The 3-bit output from the multiplier bit selection circuit 104 and the 8-bit multiplicand X held in the multiplicand holding circuit 100
A partial product generation circuit 106 for generating and outputting a 9-bit partial product based on the secondary Booth algorithm;
Sign extender 10 that performs 2-bit sign extension on input 7-bit data (that is, adds 2 bits the same as the most significant bit to the most significant bit side of the data) and outputs it
8, an adder 110 that adds 9-bit data from the sign extender 108 and a 9-bit partial product from the partial product generation circuit 106, and calculates the upper 7 bits of the 9-bit data output from the adder 110 An intermediate sum holding circuit 112 that holds the 7-bit data held by itself and supplies it to the sign extender 108 while holding the data in synchronization with the change of the cycle signal.
And a shift register 114 that holds the lower 2 bits of the 9-bit data output from the adder 110 in synchronization with a change in the operation cycle signal.

For example, the value of the operation cycle signal sequentially changes at a predetermined clock rising timing, and the clock of the intermediate sum holding circuit 112 and the shift register 114 falls after the value of the operation cycle signal changes. The data holding operation is performed at a timing (that is, a timing shifted by a half cycle of the clock with respect to the change of the operation cycle signal). Further, the intermediate sum holding circuit 112 and the shift register 114 are initialized immediately before the operation cycle signal becomes a value indicating the first cycle, and the held contents (that is, the bits of the held data) are all set to “0”. Become.

The repetitive multiplier J1 constructed as described above
Works as follows. First, in the first cycle of the operation (that is, when the operation cycle signal has a value indicating the first cycle), the multiplier bit selection circuit 104 outputs the bits constituting the multiplier Y held in the multiplier holding circuit 102. 10 are output as a part of the first group G0 shown in FIG. 9 (Y [1], Y [0], Y [-1]). As shown, a 9-bit first partial product B is obtained from the 3 bits of the first group G0 and the multiplicand X held in the multiplicand holding circuit 100.
0 is generated and output. Then, from the top of FIG.
As shown in the fifth to fifth stages, the initial value of the intermediate sum holding circuit 112 (that is, 7-bit data in which all bits are “0”) is 2-bit sign-extended by the sign extender 108 to “0”. 9-bit data and the 9-bit first partial product B0 from the partial product generation circuit 106 are added by the adder 110, and the higher-order 9-bit data of the addition result of the adder 110 is added. Seven bits are held in the intermediate sum holding circuit 112. Also, the lower 2 bits (2 bits indicated by “◎” in the “intermediate sum 1” stage in FIG. 11) of the 9-bit data that is the addition result of the adder 110 are Will be retained.

Next, in the second cycle of the operation (that is, when the operation cycle signal becomes a value indicating the second cycle), the multiplier bit selection circuit 104
As a part of the bits forming the multiplier Y held in 2, the three bits (Y [3], Y [3],
Y [2], Y [1]) are output, and the partial product generation circuit 1
In step 06, as shown in FIG. 10, a 9-bit second partial product B1 is generated and output from the 3 bits of the second group G1 and the multiplicand X held in the multiplicand holding circuit 100. Then, as shown in the fifth to seventh stages from the top in FIG. 11, the sign extender 108 converts the 7-bit data held in the intermediate sum holding circuit 112 into two bits (FIG. 1).
The two 9-bit sign-extended 9-bit data of the "intermediate sum 1" stage in FIG. 1 and the 9-bit second partial product B1 from the partial product generating circuit 106 are added by the adder 110. Further, the upper 7 bits of the 9-bit data as the addition result of the adder 110 are updated and held in the intermediate sum holding circuit 112. Further, the shift register 114 is shifted to the lower 2 bits by 2 bits (right shift), and the lower 2 bits of the 9-bit data that is the addition result of the adder 110 ("◎" in the "intermediate sum 2" stage in FIG. 11). The upper 2 bits of the 4 bits marked with “” are held in the upper 2 bit positions of the shift register 114. As a result, the “◎” mark 4 in the “intermediate sum 2” stage in FIG.
The bit will be held in the shift register 114.

Then, as shown in the seventh to ninth stages and the ninth to eleventh stages from the top in FIG. 11, the third and fourth cycles of the operation are similarly executed, and as a result, the multiplicand X
Of the 15-bit data representing the product of
The bit is held in the intermediate sum holding circuit 112, and the lower 8 bits (8 bits indicated by “◎” in the “product” stage in FIG. 11)
Is held in the shift register 114, and the multiplication ends.

On the other hand, since the multiplication using the Booth algorithm is based on multiplication in signed two's complement notation (signed multiplication), unsigned multiplication (that is, absolute value notation) is performed as it is. Binary multiplication) cannot be performed. Therefore, in order to selectively perform signed multiplication and unsigned multiplication using common hardware using the second-order Booth algorithm, input multiplicand X and multiplier Y will be described below. Is extended by at least one bit. Here, a case of performing multiplication of 8 bits × 8 bits will be described as an example.

First, when performing unsigned multiplication, the most significant bits X [7] and Y [7] of the 8-bit multiplicand X and the multiplier Y
Is not a sign bit, and at least one bit of positive “0” is added above the most significant bits X [7] and Y [7] of each of the multiplicand X and the multiplier Y ( That is, each of the multiplicand X and the multiplier Y is extended by at least one bit 0), and the multiplicand X and the multiplier Y are treated as signed numbers. When signed multiplication is performed, the most significant bits X [7] and Y [7] of the multiplicand X and the multiplier Y are originally sign bits, but the most significant bits X [7] and Y [7]. , And at least one bit having the same value as the most significant bits X [7] and Y [7] is added (ie, the multiplicand X
And each of the multipliers Y is sign-extended by at least one bit with the most significant bit). This is because signed multiplication and unsigned multiplication are performed by common hardware.

Then, the multiplicand X and the multiplier Y extended by at least one bit as described above may be multiplied in the same procedure as in FIG. As an example, FIG.
An execution example in the case of switching between 8-bit signed multiplication and unsigned multiplication will be described. In the case of this example, as shown by the “△” mark, when performing signed multiplication, each of the multiplicand X and the multiplier Y is one-bit sign-extended with the most significant bit, and when performing unsigned multiplication, Each of the multiplicand X and the multiplier Y is extended by one bit 0. And 9 which is extended by 1 bit
The bits forming the multiplier Y of the bits are divided into five groups as in the state shown in FIG. 9, and five partial products B0 to B4 are generated corresponding to each group. Further, the five partial products B0 to B4 are shifted by 2 bits and cumulatively added, thereby obtaining 16-bit data representing the product of the multiplicand X and the multiplier Y.

However, in this case, the fifth partial product B4 corresponding to the group of the most significant bit (fifth group) among the bits constituting the multiplier Y extended by 1 bit is an unsigned multiplication. And the most significant bit Y [7] of the original multiplier Y
Is "+ X" only when is "1", otherwise it is "0".

That is, first, in the case of unsigned multiplication, 1
Although the most significant bit (Y [8]) of the bit-expanded multiplier Y becomes “0”, the higher bit (Y [9]) can be regarded as “0”, so that the bit-expanded multiplier 1 Among the groups of three bits of Y, the fifth group G4, which is one level higher than the fourth group G3 in FIG.
The bit arrangement of (Y [9], Y [8], Y [7]) is "0,
0,0 "or" 0,0,1 ". Therefore, the fifth partial product B4 becomes "+ X" when the most significant bit Y [7] of the original multiplier Y is "1", and when the most significant bit Y [7] is "0". Becomes "0" (see FIG. 7). Also,
In the case of signed multiplication, the upper two bits (Y [8], Y [7]) of the multiplier Y extended by 1 bit have the same value as the most significant bit Y [7] of the original multiplier Y, The higher-order bits (Y [9]) can be regarded as having the same value as the most significant bit Y [7] of the original multiplier Y. Therefore, the fifth group G4 (Y [9], Y [8], Y [7]) of the multiplier Y extended by 1 bit
) Is "0,0,0" or "1,1,
1 ", and the fifth partial product B4 is always" 0 "(FIG. 7).
reference). Therefore, the fifth partial product B4 becomes "+ X" only in the case of unsigned multiplication and when the most significant bit Y [7] of the original multiplier Y is "1", and in other cases, it becomes "0". It becomes.

In FIG. 12, similarly to FIG. 8, each bit of the partial products B0 to B4 is indicated by "O" and "●".
Also, “□” indicates sign extension bits required for digit alignment at the time of addition. In other words, regarding the first partial product B0 to the fourth partial product B3, in FIG.
The 10 bits (= 9 + 1) indicated by the mark are essential, and the sign extension bits indicated by the "□" mark are added in order to match the bit positions of the most significant bits of the partial products B0 to B3 during addition. . In the case of this example, for the fifth partial product B4, 8 bits indicated only by the mark "O" are indispensable.

In view of the above, for example, an iterative multiplier (hereinafter, referred to as a “signature multiplier”) that alternatively executes a signed multiplication and an unsigned multiplication of 8 bits × 8 bits using a second-order Booth algorithm. The "multiplier with / without" is configured as shown in FIG. 13, and the multiplication operation is as shown in FIG.

That is, as shown in FIG. 13, an 8-bit multiplicand X and a multiplier Y are input to the signed / unsigned repetition multiplier J2, and the first cycle of the operation is performed.
In the second cycle,..., An operation cycle signal indicating the number of operation cycles is input via the first control line L1. Further, a switching signal for setting the type of multiplication performed by the multiplier J2 to either signed multiplication or unsigned multiplication is input via the second control line L2.

The signed / unsigned repetitive multiplier J2 converts an 8-bit multiplicand X input from the outside into
The multiplicand holding circuit 200 which holds the operation cycle signal from the first control line L1 at the timing (or the immediately preceding timing) at which the value indicates the first cycle, and the switching signal from the second control line L2 are signed When the execution of the multiplication is indicated, the multiplicand X held in the multiplicand holding circuit 200 is sign-extended by 1 bit and output, and when the switching signal indicates the execution of the unsigned multiplication, the multiplicand holding circuit 200 is output.
And a bit extender 202 that extends the multiplicand X stored in the bit line by one bit 0 and outputs the result. When the switching signal from the second control line L2 indicates the execution of signed multiplication, an externally input 8-bit The multiplier Y is sign-extended by 1 bit and output,
Conversely, if the switching signal indicates the execution of unsigned multiplication, the externally input 8-bit multiplier Y is set to 1 bit 0
A bit extender 204 that expands and outputs, and a 9-bit multiplier Y (multiplier Y after 1-bit expansion) output from the bit expander 204 are converted into a first cycle by an operation cycle signal from the first control line L1. Is held by the multiplier holding circuit 206 at the timing (or the immediately preceding timing) at which the value indicates the value, and the multiplier holding circuit 206 synchronizes with the change of the operation cycle signal from the first control line L1. 9
A multiplier bit selection circuit 208 for selecting and outputting one of the three bits of each of the groups G0 to G3 shown in FIG. It should be noted that the multiplier bit selection circuit 208 corresponds to FIG.
The operation is the same as that of the multiplier bit selection circuit 104.

Further, the signed / unsigned repetitive multiplier J2 includes a 3-bit output from the multiplier bit selection circuit 208 and a 9-bit multiplicand X (one-bit expanded multiplicand X) output from the bit expander 202. ), A partial product generating circuit 210 for generating and outputting a 10-bit partial product based on the secondary Booth algorithm, and a second control line L
2 indicates the execution of unsigned multiplication, and the 9-bit multiplier Y held in the multiplier holding circuit 206 is the eighth bit counted from the least significant bit (ie, the original multiplier input from the outside). When the most significant bit Y [7] of Y is "1", the multiplicand holding circuit 200 holds the operation cycle signal at the timing when the operation cycle signal from the first control line L1 becomes a value indicating the fourth cycle. A final partial product generation circuit 212 which outputs the 8-bit multiplicand X as the fifth partial product B4, and otherwise outputs 8-bit data in which all bits are "0" as the fifth partial product B4. It has.

Further, the signed / unsigned repetitive multiplier J2 is provided with a sign extender 214 for extending the input 8-bit data by 2-bit sign extension and outputting, and a sign extender 2
An adder 216 for adding the 10-bit data from 14 and the 10-bit partial product from the partial product generation circuit 210;
Top 8 of 10-bit data output from adder 216
An intermediate sum holding circuit 218 that holds the bits in synchronization with the change of the operation cycle signal and supplies the 8-bit data held by itself to the sign extender 214;
6, a shift register 220 for holding the lower 2 bits of the 10-bit data output from the adder 216 in synchronization with the change of the operation cycle signal, and the upper 8 bits of the 10-bit data output from the adder 216 , And a product upper bit register 224 that holds 8-bit data output from the adder 222 in synchronization with a change in the operation cycle signal.

The signed / unsigned repetition multiplier J
Also in 2, for example, the value of the operation cycle signal changes sequentially at a predetermined clock rising timing, and the intermediate sum holding circuit 218, the shift register 220, and the product upper bit register 224 change the value of the operation cycle signal after the change. The data holding operation is performed at the timing when the clock falls. Further, the intermediate sum holding circuit 218, the shift register 220, and the product upper bit register 224 are initialized immediately before the operation cycle signal becomes a value indicating the first cycle, and all the bits of the held data are set to “0”. Become. On the other hand, the product upper bit register 224 may perform the data holding operation only when the operation cycle signal becomes a value indicating the fourth cycle.

The signed / unsigned repetitive multiplier J2 configured as described above operates as follows. First, in the case of signed operation (that is, when the switching signal indicates the execution of signed multiplication), the 9-bit multiplicand X obtained by sign-extending the 8-bit multiplicand X by 1 bit is output from the bit extender 202. At the same time, a 9-bit multiplier Y obtained by sign-extending the 8-bit multiplier Y by 1 bit is output from the multiplier holding circuit 206. Conversely, in the case of unsigned operation (that is, when the switching signal indicates the execution of unsigned multiplication), the 9-bit multiplicand X obtained by extending the 8-bit multiplicand X by 1 bit 0 is output from the bit expander 202. At the same time, a 9-bit multiplier Y obtained by extending the 8-bit multiplier Y by 1 bit 0 is output from the multiplier holding circuit 206.

Then, in the first cycle of the operation (that is, when the operation cycle signal has a value indicating the first cycle), the multiplier bit selection circuit 208 sends the multiplier holding circuit 20
As a part of the bits constituting the 9-bit multiplier Y held in 6, three bits (Y [1], Y [0], Y [-1]) of the first group G0 shown in FIG. 9 are output. Further, as shown in FIG. 13, the partial product generation circuit 210 calculates the 10-bit first multiplicand X from the 3 bits of the first group G0 and the 9-bit multiplicand X output from the bit expander 202.
A partial product B0 is generated and output. And further, FIG.
As shown in the third to fifth stages from the top of FIG. 4, the initial value of the intermediate sum holding circuit 218 (that is, 8-bit data in which all bits are “0”) is 2-bit sign-extended by the sign extender 214. The adder 216 adds the 10-bit data in which all the bits are “0” and the 10-bit first partial product B0 from the partial product generation circuit 210, and further adds the 10-bit result of the adder 216. The upper 8 bits of the data are held in the intermediate sum holding circuit 218. Adder 2
Lower 2 bits of 10-bit data that is the result of adding 16
The bits (two bits marked with “◎” at the stage of “intermediate sum 1” in FIG. 14) are held in the upper two bit positions of the shift register 220.

Next, in the second cycle of the operation (that is, when the operation cycle signal has a value indicating the second cycle), the multiplier bit selection circuit 208 sends the multiplier holding circuit 20
As a part of the bits constituting the 9-bit multiplier Y held in 6, three bits (Y [3], Y [2], Y [1]) of the second group G1 shown in FIG. 9 are output. Further, as shown in FIG. 13, the 10-bit second multiplicand X output from the bit expander 202 is calculated by the partial product generation circuit 210 from the 3 bits of the second group G1.
A partial product B1 is generated and output. Then, as shown in the fifth to seventh stages from the top in FIG.
The eight-bit data held in the code extender 21
The 10-bit data sign-extended by 2 bits at 4 (the 2 bits marked with “□” at the “intermediate sum 1” stage in FIG. 14) and the 10-bit second partial product B 1 from the partial product generation circuit 210 are , And the upper 8 bits of the 10-bit data as the addition result of the adder 216 are updated and held in the intermediate sum holding circuit 218. Also, the shift register 220 is shifted to the lower 2 bits by 2 bits (to the right), and the lower 2 bits of the 10-bit data that is the addition result of the adder 216 (“◎ in the“ intermediate sum 2 ”stage in FIG. 14). The upper two bits of the four bits marked with “” are held in the upper two bit positions of the shift register 220. As a result, four bits marked with “◎” at the stage of “intermediate sum 2” in FIG. 14 are held in the shift register 220.

Then, as shown in the seventh to ninth stages and the ninth to eleventh stages from the top in FIG. 14, the third and fourth cycles of the operation are executed in the same manner. 8 are stored in the shift register 220 in the “intermediate sum 4” stage, and especially in the fourth cycle of the operation, the eleventh to thirteenth stages from the top in FIG. As shown in FIG. 14, the upper 8 bits (8 bits marked with “○” in the “intermediate sum 4” stage in FIG. 14) of the 10-bit data as the addition result of the adder 216 and the final partial product generation circuit 212 The output 8-bit fifth partial product B4 is added by the adder 222, and the adder 222
Is stored in the product upper bit register 224.

Therefore, when the fourth cycle of the operation is completed, the upper 8 bits of the 16-bit data representing the product of the multiplicand X and the multiplier Y are held in the product upper bit register 224, and the lower 8 bits are stored. Shift register 22
This means that the multiplication is completed.

On the other hand, FIG. 15 is a block diagram showing another conventional configuration of an 8-bit × 8-bit signed / unsigned repetition multiplier using the second-order Booth algorithm, and FIG. It is a schematic diagram showing the multiplication operation | movement of the signed / unsigned repetition multiplier J3.

As shown in FIG. 15, the signed / unsigned repetitive multiplier J3 converts an 8-bit multiplicand X input from the outside into a value indicating that the operation cycle signal from the first control line L1 indicates the first cycle. Multiplicand holding circuit 300 holding at the timing (or timing immediately before)
And when the switching signal from the second control line L2 indicates the execution of signed multiplication, the multiplicand X held in the multiplicand holding circuit 300 is sign-extended by 2 bits and output. In the case of indicating the execution of the null multiplication, the bit extender 302 that extends the multiplicand X held in the multiplicand holding circuit 300 by two bits 0 and outputs the result, and the second control line L2
When the switching signal from the indicates execution of signed multiplication, the externally input 8-bit multiplier Y is sign-extended by 2 bits and output, and conversely, when the switching signal indicates execution of unsigned multiplication, Is a bit extender 304 that extends an 8-bit multiplier Y input from the outside by two bits 0 and outputs the same, and a 10-bit multiplier Y output from the bit expander 304 (multiplier Y after 2-bit expansion) At the timing when the operation cycle signal from the first control line L1 reaches the value indicating the first cycle (or the timing immediately before), and a multiplier holding circuit 306.

Further, the signed / unsigned repetitive multiplier J3 forms the 10-bit multiplier Y held in the multiplier holding circuit 306 in synchronization with the change of the operation cycle signal from the first control line L1. FIG.
, A multiplier bit selection circuit 308 for selecting and outputting any three bits of each of the groups G0 to G4 in order from the lower one, a 3-bit output from the multiplier bit selection circuit 308 and a bit extender 302. From the output 10-bit multiplicand X (multiplicand X after 2-bit expansion), 2
A partial product generation circuit 310 that generates and outputs a 10-bit partial product based on the next Booth's algorithm, a sign extender 214, an adder 216, and an intermediate A sign extender 314, similar to the sum holding circuit 218 and the shift register 220,
An adder 316, an intermediate sum holding circuit 318, and a shift register 320 are provided. Note that the shift register 320
Is capable of storing 10-bit data.

Here, the two bits marked with “△” in FIG. 17 are the upper two bits (Y [9], Y [8]) of the multiplier Y extended by the bit extender 304. And
When the operation cycle signal reaches a value indicating the first cycle, the multiplier bit selection circuit 308 outputs three bits (Y [1], Y [0], Y [-1) of the first group G0 on the lowermost side shown in FIG. ]:
However, Y [-1] is a dummy bit and outputs "0", and when the operation cycle signal becomes a value indicating the second cycle, the three bits (Y [3], Y [3]) of the second group G1 shown in FIG. 2], Y
[1]), and when the operation cycle signal reaches a value indicating the third cycle, the three bits (Y [5], Y [4], Y [3]) of the third group G2 shown in FIG. 17 are output. When the operation cycle signal reaches a value indicating the fourth cycle, the three bits (Y [7], Y [6], Y [5]) of the fourth group G3 shown in FIG.
When the operation cycle signal reaches a value indicating the fifth cycle, three bits (Y
[9], Y [8], Y [7]).

The signed / unsigned repetitive multiplier J3 thus configured operates as follows. First, in the case of signed operation (that is, when the switching signal indicates execution of signed multiplication), a 10-bit multiplicand X obtained by sign-extending an 8-bit multiplicand X by 2 bits is output from the bit extender 302. At the same time, a 10-bit multiplier Y obtained by extending the 8-bit multiplier Y by 2 bits is output from the multiplier holding circuit 306. Conversely, in the case of unsigned operation (ie, when the switching signal indicates the execution of unsigned multiplication), the 10-bit multiplicand X obtained by extending the 8-bit multiplicand X by 2 bits 0 is output from the bit extender 302. At the same time, a 10-bit multiplier Y obtained by extending the 8-bit multiplier Y by 2 bits 0 is output from the multiplier holding circuit 306.

Then, in the first cycle of the operation (that is, when the operation cycle signal becomes a value indicating the first cycle), the multiplier bit selection circuit 308 sends the multiplier holding circuit 30
As a part of the bits forming the 10-bit multiplier Y held in 6, three bits (Y [1], Y [0], Y [-1]) of the first group G0 shown in FIG. Further, as shown in FIG. 15, the 10-bit first partial product is generated by the partial product generation circuit 310 from the 3 bits of the first group G0 and the 10-bit multiplicand X output from the bit expander 302. B0 is generated and output. Further, as shown in the third to fifth stages from the top in FIG. 16, the initial value of the intermediate sum holding circuit 318 (that is, 8-bit data in which all bits are “0”) is The adder 316 adds the 10-bit data in which all the bits subjected to the bit sign extension are "0" and the 10-bit first partial product B0 from the partial product generation circuit 310, and further adds the addition result of the adder 316. The upper 8 bits of the 10-bit data are held in the intermediate sum holding circuit 318. Also,
The lower 2 bits (2 bits indicated by “◎” in the “intermediate sum 1” stage in FIG. 16) of the 10-bit data that is the addition result of the adder 316 are held in the upper 2 bits of the shift register 320. You.

Next, in the second cycle of the operation (that is, when the operation cycle signal has a value indicating the second cycle), the multiplier bit selection circuit 308 sends the multiplier holding circuit 30
As a part of the bits forming the 10-bit multiplier Y held in 6, three bits (Y [3], Y [2], Y [1]) of the second group G1 shown in FIG. 17 are output. Further, as shown in FIG. 15, the 10-bit second partial product B1 is obtained from the 3 bits of the second group G1 and the 10-bit multiplicand X output from the bit expander 302, as shown in FIG. Is generated and output. Then, as shown in the fifth to seventh stages from the top in FIG. 16, the 8-bit data held in the intermediate sum holding circuit 318 is converted into two bits by the sign extender 314 (“intermediate sum 1” in FIG. 16). The 2 bit sign-extended (2 bits) sign-extended 10-bit data and the 10-bit second partial product B1 from the partial product generation circuit 310 are added by the adder 316.
The upper 8 bits of the 10-bit data as the addition result of the adder 316 are updated and held in the intermediate sum holding circuit 318. Also, the shift register 320 is shifted to the lower 2 bits (to the right), and the lower 2 bits of the 10-bit data that is the addition result of the adder 316 (“「 in the “intermediate sum 2” stage in FIG. 16). The upper 2 bits of the 4 bits marked with “” are held in the upper 2 bit positions of the shift register 320. As a result, the four bits marked with “◎” in the “intermediate sum 2” stage in FIG. 16 are held in the shift register 320.

Then, from the top in FIG.
As shown in the ninth to eleventh stages and the eleventh to thirteenth stages, the third, fourth, and fifth cycles of the operation are similarly executed. As a result, the multiplicand X, the multiplier Y, Of the 16-bit data representing the product of, the upper 6 bits (6 bits marked with “○” in the “product” stage in FIG. 16) are held in the lower 6 bits of the intermediate sum holding circuit 318, and the lower 10 bits ( 1 of “◎” mark of the “product” stage in FIG. 16
0 bit) is held in the shift register 320, and the multiplication ends.

[0042]

The conventional iterative multipliers J1, J2, and J3 shown in FIGS. 10, 13, and 15, respectively, have three lines from the top in FIG. 11, FIG. 14, and FIG. As shown in the stages from the fifth stage to the fifth stage, in the first cycle of the operation, the adders 110, 216, 316 initialize the intermediate sum holding circuits 112, 218, 318 with initial values (data in which all bits are “0”). Is added to the first partial product B0. For this reason, in the first cycle of the operation, the cumulative addition of the partial products is not substantially performed, resulting in waste.

In particular, in a configuration in which signed multiplication and unsigned multiplication are selectively performed by common hardware, as described above, the input multiplicand X and multiplier Y are extended by at least one bit (code (Extended or 0-extended), and accordingly, one extra partial product is generated as compared with the configuration in which only signed multiplication is performed. Therefore,
As can be seen from a comparison between FIG. 11 and FIG. 16, an operation cycle (fifth cycle in FIG. 16) for adding a partial product (fifth partial product B4) generated by one extra is added by one cycle. This is very disadvantageous in that the speed of calculation required to obtain the product decreases.

Further, an adder 222 for adding only one extra partial product (fifth partial product B4) is additionally provided as in the signed / unsigned repetitive multiplier J2 shown in FIG. If this is the case, the operation cycle can be reduced by one cycle, and furthermore, the operation speed equivalent to that of the configuration in which only signed multiplication is performed can be achieved. However, since the adder has a relatively large circuit scale, It is disadvantageous in terms of chip size when it is made into an IC.

The present invention has been made in view of such a problem, and has as its object to provide a repetitive multiplier (iterative multiplier) that can improve the operation speed with a relatively small circuit configuration. I have.

[0046]

In the multiplier according to the present invention which has been made to achieve the above object, the multiplicand holding means holds the multiplicand, and the multiplier holding means holds the multiplier.

Then, the first partial product generating circuit synchronizes with the change of the operation cycle signal indicating the number of operation cycles,
Among the bits constituting the multiplier held in the multiplier holding means, some of the bits other than some of the least significant bits are selected in order from the lower one, and the selected A partial product is generated from the bit and the multiplicand held in the multiplicand holding means.

When the operation cycle signal indicates the first operation cycle, the second partial product generation circuit outputs the least significant part of the bits constituting the multiplier held in the multiplier holding means. A partial product is generated from the bit and the multiplicand held in the multiplicand holding means.

In the partial product accumulative addition circuit having the addition means and the addition result holding means for holding the addition result of the addition means, the addition means adds the first partial product to the value held in the addition result holding means. The partial product generated by the first partial product generation circuit is added by adding the partial products generated by the generation circuit, and the addition result holding means updates and holds the addition result of the addition means in synchronization with the change of the operation cycle signal. Is cumulatively added, particularly in the present invention,
When the operation cycle signal indicates the first operation cycle, the augend selection circuit adds the partial product generated by the second partial generation circuit, instead of the value held in the addition result holding means. It is supplied to the means as an augend (ie, a number that is added to the partial product generated by the first partial product generation circuit).

In such a multiplier according to the present invention, in the first cycle in which the operation cycle signal indicates the first operation cycle, the addition means of the partial product accumulative addition circuit uses the initial value of the addition result holding means at that time. Instead, the partial product generated by the second partial product generation circuit (ie, the first partial product corresponding to some of the least significant bits of the multiplier) is added to the partial product generated by the first partial product generation circuit. The products (that is, partial products corresponding to some bits higher than some least significant bits of the multiplier) are added.

Then, in the second and subsequent cycles in which the operation cycle signal indicates the second and subsequent operation cycles, the addition means of the partial product accumulative addition circuit performs the addition result holding means in the previous operation cycle similarly to the conventional multiplier. To the value held in
The partial products generated this time by the partial product generating circuit are added.

Therefore, according to the iterative multiplier of the present invention, from the first cycle of the operation, the first partial product corresponding to some least significant bits of the multiplier and the higher partial product are calculated. Addition can eliminate waste in the first cycle as in a conventional multiplier, and as a result, improve the operation speed until a product is obtained without adding an adder having a relatively large circuit size. Can be.

By the way, as described in claim 2, the first
If the partial product generation circuit and the second partial product generation circuit are configured to generate a partial product based on a secondary Booth algorithm, the partial product is generated corresponding to each bit of the multiplier. Compared with the case, the number of partial products required for multiplication can be reduced by half, which is very advantageous for improving the calculation speed until obtaining the product.

On the other hand, in the multiplier according to the third aspect, the multiplier according to the second aspect uses a second-order Booth's algorithm, and the multiplicand holding means determines whether the type of multiplication performed by the multiplier is signed. When the switching signal for setting to any of the multiplication and the unsigned multiplication indicates execution of signed multiplication, the multiplicand input from the outside is sign-extended by the most significant bit by two bits and held, If the switching signal indicates that unsigned multiplication is to be performed, the multiplicand input from the outside is held by extending the most significant bit side by two bits 0. Similarly, when the switching signal indicates execution of signed multiplication, the multiplier holding means also holds the multiplier input from the outside by sign-extending the most significant bit by two bits, and the switching signal is When the execution of the unsigned multiplication is indicated, the multiplier input from the outside is held by extending the most significant bit side by 2 bits 0.

According to the multiplier of the third aspect, signed multiplication and unsigned multiplication are selectively performed by common hardware using a second-order Booth algorithm. Will be able to In the case of this multiplier, the input multiplicand and multiplier are extended by 2 bits (sign extension or 0 extension) and processed.
One extra partial product is generated as compared with the configuration in which only signed multiplication is performed. However, since the partial product can be cumulatively added from the first cycle of the operation as described above,
An operation speed equivalent to that of a conventional multiplier that performs only signed multiplication can be achieved without any additional adder. That is, according to the multiplier of the third aspect, signed multiplication and unsigned multiplication can be switched and executed without lowering the operation speed and with a relatively small circuit configuration.

[0056]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. First, FIG. 1 shows a repetition multiplier (signed / unsigned repetition multiplier) M1 of the first embodiment that inputs an 8-bit multiplicand X and a multiplier Y and selectively performs signed multiplication and unsigned multiplication. FIG. 2 is a block diagram illustrating a configuration, and FIG. 2 is a schematic diagram illustrating a multiplication operation of the repetitive multiplier M1. In the repetitive multiplier M1 of the first embodiment, an operation cycle signal indicating the number of operation cycles, such as the first cycle, the second cycle,... Of the operation, is input via the first control line L1. In addition, a switching signal for setting the type of multiplication performed by the multiplier M1 to either signed multiplication or unsigned multiplication is input via the second control line L2.

As shown in FIG. 1, the iterative multiplier M1 of the first embodiment has the same structure as the multiplier J3 shown in FIG.
A multiplicand holding circuit 10 for holding an 8-bit multiplicand X input from the outside at a timing when the operation cycle signal from the first control line L1 has a value indicating the first cycle (or a timing immediately before the same); When the switching signal from the second control line L2 indicates execution of signed multiplication, the multiplicand X held in the multiplicand holding circuit 10 is sign-extended by two bits and output. Is performed, the multiplicand X held in the multiplicand holding circuit 10 is extended by two bits 0 and output.
2 and when the switching signal from the second control line L2 indicates execution of signed multiplication, the 8-bit multiplier Y input from the outside is sign-extended by 2 bits and output. In the case of indicating the execution of the null multiplication, an 8-bit multiplier Y input from the outside is extended by 2 bits by 0 and output, and a 10-bit multiplier Y output from the bit expander 14 ( And a multiplier holding circuit 16 for holding the multiplier Y) after the 2-bit expansion at a timing when the operation cycle signal from the first control line L1 becomes a value indicating the first cycle (or a timing immediately before that). I have.

The repetition multiplier M of the first embodiment
1 is a 4-bit Y from the least significant bit Y [0] to the fourth bit Y [3] among bits constituting the 10-bit multiplier Y held in the multiplier holding circuit 16 as shown in FIG.
A first output composed of [3: 0], a second output composed of four bits Y [5: 2] from a third bit Y [2] to a sixth bit Y [5], and a fifth bit Y [4] To the eighth bit Y [7], the third output consisting of four bits Y [7: 4], and the fourth bit Y [9: 6] from the seventh bit Y [6] to the tenth bit Y [9]. And a multiplier bit selection circuit 18 which outputs the fourth output from the first control line L1 in order from the lower one in synchronization with the change of the operation cycle signal from the first control line L1.

Note that the two bits marked with “△” in FIG.
The upper 2 bits (Y [9], Y [8]) of the multiplier Y extended by the bit extender 14. When the operation cycle signal reaches a value indicating the first cycle, the multiplier bit selection circuit 18 outputs the first output (Y [3: 0]) shown in FIG. 3, and the operation cycle signal indicates the second cycle. When the value reaches the value, the second output (Y [5: 2]) shown in FIG. 3 is output. When the operation cycle signal reaches the value indicating the third cycle, the third output (Y [7: 4]) shown in FIG. ), And when the operation cycle signal reaches a value indicating the fourth cycle, the fourth output (Y [9: 6]) shown in FIG. 3 is output.

The repetitive multiplier M1 of the first embodiment is configured to output the multiplicand X (2) of the upper 3 bits of the 4 bits output from the multiplier bit selection circuit 18 and the 10 bits output from the bit expander 12. From the multiplicand X) after the bit expansion, 10
Partial product generation circuit 20 for generating and outputting a partial product of bits
And the lower two bits of the four bits output from the multiplier bit selection circuit 18, and the three bits obtained by adding a dummy bit of “0” to the lower side of the lower two bits and the output from the bit expander 12. From the 10-bit multiplicand X
A partial product generation circuit 22 for generating and outputting a 10-bit partial product based on a secondary Booth algorithm.

Further, the repetition multiplier M1 of the first embodiment includes a sign extender 24 for sign-extending the input 10-bit data by 2 bits and outputting the sign extension, and a sign extender 24.
Adder 26 for adding the upper 10 bits of the 12-bit data output from the above and the 10-bit partial product from partial product generation circuit 20, and 10 output from adder 26.
An intermediate sum holding circuit 28 that holds and outputs bit data in synchronization with a change in the operation cycle signal, and a lower 2 bits of 12-bit data output from the sign extender 24 in synchronization with a change in the operation cycle signal. When the held shift register 30 and the operation cycle signal have a value indicating the first cycle, the 10-bit partial product from the partial product generating circuit 22 is selected and input to the sign extender 24. Is a summand selection circuit 32 that selects 10-bit data from the intermediate sum holding circuit 28 and inputs the data to the sign extender 24.
And

The shift register 30 can store 8-bit data. Also, in the repetitive multiplier M1 of the first embodiment, for example, the value of the operation cycle signal sequentially changes at the rising timing of a predetermined clock, and the intermediate sum holding circuit 28 and the shift register 30
The data holding operation is performed at the timing when the clock falls after the value of the operation cycle signal changes (that is, at the timing shifted by a half cycle of the clock with respect to the change in the operation cycle signal).

The repetitive multiplier M1 according to the first embodiment thus configured operates as follows. First, when performing a signed operation (i.e., when the switching signal indicates the execution of signed multiplication), at least during the execution of the operation in which the operation cycle signal has a value indicating the first to fourth cycles, 8 The 10-bit multiplicand X obtained by extending the bit multiplicand X by two bits is continuously output from the bit expander 12, and the 10-bit multiplier Y obtained by extending the 8-bit multiplier Y by two bits is stored in the multiplier holding circuit 16. Is output continuously. Conversely, when performing an unsigned operation (ie, when the switching signal indicates execution of unsigned multiplication)
, At least the operation cycle signal is in the first cycle to 4
During the execution of the operation indicating the cycle number, the 10-bit multiplicand X obtained by extending the 8-bit multiplicand X by 2 bits 0 is continuously output from the bit extender 12, and the 8-bit multiplier Y is set to 2 The multiplier Y of 10 bits extended by bit 0 is continuously output from the multiplier holding circuit 16.

Then, in the first cycle of the operation (that is, when the operation cycle signal becomes a value indicating the first cycle), the multiplier bit selection circuit 18 stores the data in the multiplier holding circuit 16. Of the bits constituting the bit multiplier Y, four bits Y [3: 0] of the first output shown in FIG.
(Y [3], Y [2], Y [1], Y [0]) are output, and the partial product generation circuit 22 outputs the four bits Y [3: 0] from the multiplier bit selection circuit 18. Lower 2 bits (Y [1], Y [0])
From the 3 bits with the dummy bit Y [-0] of “0” added to the lower side of the data and the 10-bit multiplicand X output from the bit expander 12, 1
A first partial product B0 of 0 bits is generated and output. Also,
The partial product generation circuit 20 outputs the upper three bits (Y [3], Y [3]) of the four bits Y [3: 0] from the multiplier bit selection circuit 18.
[2], Y [1]) and 1 output from the bit extender 12.
A 10-bit second partial product B1 is generated and output from the 0-bit multiplicand X based on the secondary Booth algorithm.

Further, in the first cycle of the operation, the first partial product B 0 from the partial product generation circuit 22 is selected by the augend selection circuit 32 and input to the sign extender 24. Therefore, as shown in the third to fifth stages from the top in FIG. 2, the 10-bit first partial product B0 from the partial product generation circuit 22 is converted into two bits ("B0" in FIG. The sign extension is performed by the adder 26, and the upper 10 bits after sign extension and the 10-bit second partial product B1 from the partial product generator 20 are added by the adder 26. Further, 10-bit data as the addition result of the adder 26 is held in the intermediate sum holding circuit 28. The lower two bits of the first partial product B0, which is the lower two bits of the output of the sign extender 24 (the two bits marked with a ".largecircle." In the "B0" stage in FIG. Are stored in the upper two bit positions of the shift register 30.

Next, in the second cycle of the operation (that is, when the operation cycle signal has a value indicating the second cycle), the 10-bit data ( In other words, the 10-bit data output from the adder 26 in the first cycle is selected and input to the sign extender 24.

Further, among the bits forming the 10-bit multiplier Y held in the multiplier holding circuit 16 from the multiplier bit selection circuit 18, the 4 bits Y [5: 2] of the second output shown in FIG. (Y [5], Y [4], Y [3], Y [2]), and the partial product generation circuit 20 outputs the four bits Y [5: 2] from the multiplier bit selection circuit 18. Upper 3 bits (Y [5],
Y [4], Y [3]) and the 10-bit multiplicand X output from the bit expander 12 to generate and output a 10-bit third partial product B2 based on a secondary Booth algorithm. .

For this reason, in the second cycle of the operation, FIG.
As shown in the fifth to seventh stages from the top, the 10-bit data held in the intermediate sum holding circuit 28 is
2, the sign extension is performed for 2 bits (2 bits marked with “□” at the stage of “intermediate sum 1” in FIG. 2), and the upper 10 bits after the sign extension and 1 from the partial product generation circuit 20.
The 0-bit third partial product B2 is added by the adder 26, and the 10-bit data as the addition result of the adder 26 is updated and held in the intermediate sum holding circuit 28. Also, the shift register 30 is shifted to the lower 2 bits by 2 bits (right shift), and the lower 2 bits of the output of the sign extender 24 and the lower 2 bits of the 10-bit data output from the adder 26 in the first cycle. Bit (the two bits marked with a “☆” at the “intermediate sum 1” stage in FIG. 2)
Upper 2 bits of 4 bits marked with “◎” in “Intermediate sum 2”
Bit) is held in the upper two bit positions of the shift register 30. As a result, the four bits marked with “◎” at the stage of “intermediate sum 2” in FIG.
It will be held at the bit position.

Next, also in the third cycle of the operation (that is, when the operation cycle signal becomes a value indicating the third cycle), the addend selection circuit 32 causes the intermediate sum holding circuit 2 to operate.
10-bit data from 8 (that is, 10-bit data output from the adder 26 in the second cycle) is selected and input to the sign extender 24.

In the third cycle of the operation, the multiplier bit selection circuit 18 outputs the bits of the 10-bit multiplier Y held in the multiplier holding circuit 16 as shown in FIG.
4 bits of the third output Y [7: 4] (Y [7], Y [6],
Y [5], Y [4]) are output, and the partial product generation circuit 20 outputs
The upper 3 bits (Y [7], Y [6], Y [5]) of the 4 bits Y [7: 4] from the multiplier bit selection circuit 18 and the 10 bits output from the bit expander 12 From the multiplicand X, a 10-bit fourth partial product B3 is generated and output based on the secondary Booth algorithm.

Therefore, in the third cycle of the operation, FIG.
As shown in the seventh to ninth stages from the top, the 10-bit data held in the intermediate sum holding circuit 28 is
2, the two bits (two bits marked with "□" at the stage of "intermediate sum 2" in FIG. 2) are sign-extended, and the upper 10 bits after sign extension and 1 from the partial product generation circuit 20.
The 0-bit fourth partial product B3 is added by the adder 26, and the 10-bit data as the addition result of the adder 26 is updated and held in the intermediate sum holding circuit 28. Also, the shift register 30 is shifted to the lower 2 bits (right shift), and the lower 2 bits of the output of the sign extender 24 and the lower 2 bits of the 10-bit data output from the adder 26 in the second cycle. Bit (the two bits marked with a “☆” at the “intermediate sum 2” stage in FIG. 2)
Upper 2 bits out of 6 bits marked with “◎” in “Intermediate sum 3” stage
Bit) is held in the upper two bit positions of the shift register 30. As a result, the 6 bits marked with “◎” at the “intermediate sum 3” stage in FIG.
It will be held at the bit position.

Next, also in the fourth cycle of the operation (that is, when the operation cycle signal becomes a value indicating the fourth cycle), the addend selection circuit 32 causes the intermediate sum holding circuit 2 to operate.
The 10-bit data from 8 (that is, the 10-bit data output from the adder 26 in the third cycle) is selected and input to the sign extender 24.

In the fourth cycle of the operation, the multiplier bit selection circuit 18 outputs the bits of the 10-bit multiplier Y held in the multiplier holding circuit 16 as shown in FIG.
4 bits of the fourth output Y [9: 6] (Y [9], Y [8],
Y [7], Y [6]) are output, and the partial product generation circuit 20
The upper 3 bits (Y [9], Y [8], Y [7]) of the 4 bits Y [9: 6] from the multiplier bit selection circuit 18 and the 10 bits output from the bit expander 12 From the multiplicand X, a 10-bit fifth partial product B4 is generated and output based on the secondary Booth algorithm. Note that, as described above, Y [9] and Y [8] are the upper two bits of the multiplier Y extended by the bit extender 14, and are indicated by “△” in FIG. .

Therefore, in the fourth cycle of the operation, FIG.
As shown in the ninth to eleventh stages from the top, the 10-bit data held in the intermediate sum holding circuit 28 is converted into two bits by the sign extender 24 (“□” in the “intermediate sum 3” stage in FIG. 2). Sign extension), the sign-extended upper 10 bits and the 10-bit fifth partial product B4 from the partial product generation circuit 20 are added by the adder 26, and further added. 10 which is the addition result of the unit 26
The bit data is updated and held in the intermediate sum holding circuit 28. Further, the shift register 30 is shifted to the lower 2 bits by 2 bits (right shift), and the lower 2 bits of the output of the sign extender 24 and the lower 2 bits of the 10-bit data output from the adder 26 in the third cycle. Bit (the two bits marked with a “☆” at the “intermediate sum 3” stage in FIG. 2)
The upper 2 bits of the 8 bits marked with “◎” in the “product” stage are held in the upper 2 bit positions of the shift register 30.

As a result, at the end of the fourth cycle of the operation, the lower 8 bits (“product” in FIG. 2) of the 16-bit data representing the product of the multiplicand X and the multiplier Y
Are stored in the shift register 30 and the upper 8 bits of the 16-bit data representing the product (the 8 bits of the “○” mark of the “product” stage in FIG. 2) ) Is held in the lower 8-bit position of the intermediate sum holding circuit 28. Then, at this point, the multiplication ends.

In the first embodiment, the multiplicand holding circuit 10 and the bit extender 12 correspond to a multiplicand holding means.
The bit expander 14 and the multiplier holding circuit 16 correspond to multiplier holding means. The multiplier bit selection circuit 18 and the partial product generation circuit 20 correspond to a first partial product generation circuit, and the multiplier bit selection circuit 18 and the partial product generation circuit 22 correspond to a second partial product generation circuit. I have. And sign extender 2
4, the adder 26, the intermediate sum holding circuit 28, and the shift register 30 correspond to a partial product accumulating and adding circuit, in which the sign extender 24 and the adder 26 correspond to the adding means, The sum holding circuit 28 and the shift register 30 correspond to an addition result holding unit.

In the repetitive multiplier M1 of the first embodiment as described above, the partial product corresponds to the lower bit of the multiplier Y by the operation of the multiplier bit selection circuit 18 and the partial product generation circuit 20 for each operation cycle. The partial products generated by the partial product generation circuit 20 at the value (intermediate sum) held in the intermediate sum holding circuit 28 and the shift register 30 at that time are added to the sign extender 24 and The addition is performed by the operation of the adder 26, and the addition result is updated and held in the intermediate sum holding circuit 28 and the shift register 30, whereby the cumulative addition of the partial products is performed.

Here, in particular, in the repetitive multiplier M1 of the first embodiment, the multiplier bit selecting circuit 18 and the partial product generating circuit 20 lower the partial products B1 to B4 other than the first partial product B0 in the lower order. The first partial product B0 is generated by the multiplier bit selection circuit 18 and the partial product generation circuit 22 in the first cycle. Then, by the augend selection circuit 32,
Only in the first cycle, the intermediate sum holding circuit 2 is supplied to the sign extender 24.
8, the first partial product B0 from the partial product generating circuit 22 is supplied.

For this reason, in the first cycle of the operation, the sign extender 24 and the adder 26 cause the partial product generating circuit 22
From the partial product generation circuit 20 to the first partial product B0 from
The partial product B1 is added. After the second cycle, the partial product generating circuit 20 sequentially operates by the operation of the sign extender 24, the adder 26, the intermediate sum holding circuit 28, and the shift register 30 as in the conventional multiplier. Cumulative addition of the generated partial products is performed.

Thus, according to the iterative multiplier M1 of the first embodiment, as is clear from the comparison between FIG. 2 and FIG. 16, the first partial product B
By adding 0 and the second partial product B1, the waste of the first cycle as in the conventional multiplier can be eliminated, and as a result,
The operation speed until obtaining the product can be improved without adding an adder having a relatively large circuit scale.

In particular, the repetition multiplier M of the first embodiment
In the case of 1, in order to execute signed multiplication and unsigned multiplication alternatively, input multiplicand X and multiplier Y are extended by 2 bits (sign extension or 0 extension) and processed. Although the fifth partial product B4 is generated one extra compared with the case of the configuration in which the multiplication is performed, since the cumulative addition of the partial products can be performed from the first cycle of the operation, the conventional multiplication shown in FIG. The operation speed equivalent to that of the conventional multiplier that performs only signed multiplication can be achieved without adding an adder as in the case of the device J2. Specifically, in the conventional signed / unsigned repetition multiplier J3 shown in FIG. 15, it takes five cycles to obtain a product.
In the iterative multiplier M1 of the first embodiment, a product can be obtained in four cycles, which has the same operation speed as the conventional iterative multiplier J1 shown in FIG. 10 that performs only signed multiplication.

As described above, according to the iterative multiplier M1 of the first embodiment, signed multiplication and unsigned multiplication are switched and executed without reducing the operation speed and with a relatively small circuit configuration. can do. Next, a second embodiment will be described with reference to FIGS.

First, FIG. 4 shows an 8-bit multiplicand X and a multiplier Y
FIG. 5 is a block diagram illustrating a configuration of a repetition multiplier (signed / unsigned repetition multiplier) M2 according to a second embodiment that performs signed multiplication and unsigned multiplication alternatively by inputting an input signal.
Is a schematic diagram showing a multiplication operation of the repetitive multiplier M2. Note that, in FIG. 4, the same components as those of the repetitive multiplier M1 of the first embodiment are denoted by the same reference numerals, and a detailed description thereof will be omitted.

As shown in FIG. 4, the iterative multiplier M2 of the second embodiment differs from the multiplier M1 of the first embodiment in the following points (1) to (4). . (1) The multiplier bit selection circuit 34 provided in place of the multiplier bit selection circuit 18 is one of the bits constituting the 10-bit multiplier Y after the 2-bit expansion held in the multiplier holding circuit 16 shown in FIG. As shown in the figure, the first bit consisting of 6 bits Y [5: 0] from the least significant bit Y [0] to the sixth bit Y [5]
The output and the second output consisting of 6 bits Y [9: 4] from the 5th bit Y [4] to the 10th bit Y [9] are synchronized with the change of the operation cycle signal from the first control line L1. And output in order from the lower order.

That is, when the operation cycle signal reaches the value indicating the first cycle, the multiplier bit selection circuit 34 of the second embodiment outputs the first output (Y [5: 0]) shown in FIG.
When the operation cycle signal reaches a value indicating the second cycle, the second output (Y [9: 4]) shown in FIG. 6 is output. Note that the two bits marked with “２” in FIG. 6 are, as in the case of FIG.
Bits (Y [9], Y [8]).

(2) Two partial product generation circuits 36 and 38 are provided instead of the partial product generation circuit 20. The one partial product generation circuit 36 outputs three bits of the lower two bits to the fourth bit of the six bits output from the multiplier bit selection circuit 34 and the ten bits output from the bit expander 12. A 10-bit partial product is generated and output from the multiplicand X (multiplicand X after 2-bit expansion) based on the second-order Booth algorithm.

Further, the other partial product generating circuit 38
Similarly to the partial product generation circuit 20 according to the embodiment, the higher order 3 bits of the 6 bits output from the multiplier bit selection circuit 34 and the 10-bit multiplicand X output from the bit expander 12 are used to calculate a second order. 1 based on Booth's algorithm
Generate and output a 0-bit partial product.

Note that also in the second embodiment, the partial product generation circuit 22 inputs the lower 2 bits of the 6 bits output from the multiplier bit selection circuit 34, and places "2" at the lower side of the lower 2 bits. A 10-bit partial product is generated and output from the 3-bit with the dummy bit of 0 ″ and the 10-bit multiplicand X output from the bit expander 12 based on the secondary Booth algorithm.

(3) A sign extender 40 and an adder 42 are additionally provided between the adder 26 and the intermediate sum holding circuit 28. Then, the first-stage adder 26 outputs the upper 10 bits of the 12-bit data output from the sign extender 24.
The bit and the 10-bit partial product from the partial product generation circuit 36 are added, and the sign extender 40 performs 2-bit sign extension on the 10-bit data output from the adder 26 and outputs the result. Further, the adder 42 in the second stage is used by the sign extender 4
The upper 10 bits of the 12-bit data output from 0 are added to the 10-bit partial product from the partial product generation circuit 38, and the 10-bit data output from the adder 42 is added to the intermediate sum holding circuit 28. Is entered.

(4) The shift register 44 provided in place of the shift register 30 stores the lower 2 bits of the 12-bit data output from the sign extender 24 and the 12-bit data output from the sign extender 40. Are held in synchronization with the change of the operation cycle signal.

The repetitive multiplier M2 according to the second embodiment thus configured operates as follows. First, when performing a signed operation (that is, when the switching signal indicates the execution of signed multiplication), at least during the execution of the operation in which the operation cycle signal has a value indicating the first cycle to the second cycle, The 10-bit multiplicand X obtained by extending the bit multiplicand X by two bits is continuously output from the bit expander 12, and the 10-bit multiplier Y obtained by extending the 8-bit multiplier Y by two bits is stored in the multiplier holding circuit 16. Is output continuously. Conversely, when performing an unsigned operation (ie, when the switching signal indicates execution of unsigned multiplication)
, At least the operation cycle signal is from the first cycle to the second
During the execution of the operation indicating the cycle number, the 10-bit multiplicand X obtained by extending the 8-bit multiplicand X by 2 bits 0 is continuously output from the bit extender 12, and the 8-bit multiplier Y is set to 2 The multiplier Y of 10 bits extended by bit 0 is continuously output from the multiplier holding circuit 16.

Then, in the first cycle of the operation (that is, when the operation cycle signal becomes a value indicating the first cycle), the multiplier bit selection circuit 34 holds the 10 bits held in the multiplier holding circuit 16. Of the bits forming the bit multiplier Y, 6 bits Y [5: 0] of the first output shown in FIG.
(Y [5], Y [4], Y [3], Y [2], Y [1], Y [0])
Is output, and the partial product generation circuit 22 outputs “0” to the lower side of the lower 2 bits (Y [1], Y [0]) of the 6 bits Y [5: 0] from the multiplier bit selection circuit 34. Dummy bit Y
A 10-bit first partial product B0 is generated and output from the 3-bit with [-0] and the 10-bit multiplicand X output from the bit expander 12 based on the secondary Booth algorithm. Further, the partial product generating circuit 36 outputs three bits (Y [3], Y [2]) of the lower 2nd to 4th bits of the 6 bits Y [5: 0] from the multiplier bit selecting circuit 34.
, Y [1]) and 10 output from the bit expander 12.
From the bit multiplicand X, a 10-bit second partial product B1 is generated and output based on the secondary Booth algorithm. Further, the partial product generation circuit 38 outputs the upper 3 bits (Y [5], Y [4], Y [3]) of the 6 bits Y [5: 0] from the multiplier bit selection circuit 34, Based on the 10-bit multiplicand X output from the expander 12, a 10-bit third partial product B2 is generated and output based on the secondary Booth algorithm.

Further, in the first cycle of the operation, the first partial product B 0 from the partial product generation circuit 22 is selected by the augend selection circuit 32 and input to the sign extender 24. Therefore, in the first cycle of the operation, first, as shown in the third to fifth stages from the top in FIG.
, The sign extension unit 24 sign-extends the first 10-bit partial product B0 by 2 bits (2 bits indicated by the "□" mark in the "B0" stage in FIG. 5) and the upper 10 bits after the sign extension. And the 10-bit second partial product B1 from the partial product generating circuit 36 are added by the adder 26. The lower two bits of the first partial product B0, which is the lower two bits of the output of the sign extender 24 ("B0" in FIG. 5)
, The lower 2 bits of the 4 bits marked “◎” in the “intermediate sum 1” are the 3rd and 4th bits from the upper bit of the shift register 44. Held in position.

Further, in the first cycle of the operation, as shown in the fifth through seventh stages from the top in FIG. In FIG. 5, “1st stage output 1” stage is “2 bits marked with“ □ ”) sign-extended, and the upper 10 bits after sign extension and 1
The 0-bit third partial product B2 is added by the adder 42, and 10-bit data as the addition result of the adder 42 is held in the intermediate sum holding circuit 28. Also,
The lower two bits of the output of the sign extender 40 (the two bits marked with a “☆” in the “first stage output 1” stage in FIG.
High-order 2 of 4 bits marked with “◎” at the stage of “Intermediate sum 1”
Bit) is held in the upper two bit positions of the shift register 44. Therefore, the four bits marked with “◎” at the stage of “intermediate sum 1” in FIG. 5 are held in the upper four bit positions of the shift register 44.

Next, in the second cycle of the operation (that is, when the operation cycle signal has a value indicating the second cycle), the 10-bit data ( That is, 10-bit data output from the adder 42 in the first cycle is selected and input to the sign extender 24.

Further, among the bits constituting the 10-bit multiplier Y held in the multiplier holding circuit 16 from the multiplier bit selection circuit 34, 6 bits Y [9: 4] of the second output shown in FIG. (Y [9], Y [8], Y [7], Y [6], Y [5],
Y [4]) is output, and the partial product generation circuit 36 outputs the lower 2 bits of the 6 bits Y [9: 4] from the multiplier bit selection circuit 34.
3 bits from bit 4 to bit 4 (Y [7], Y
[6], Y [5]) and 1 output from the bit extender 12.
A 10-bit fourth partial product B3 is generated and output from the 0-bit multiplicand X based on the secondary Booth algorithm. Further, the partial product generating circuit 38 outputs the upper 3 bits (Y [9], Y [8], Y [7]) of the 6 bits Y [9: 4] from the multiplier bit selecting circuit 34, Extender 12
From the 10-bit multiplicand X output from the first 10-bit fifth partial product B based on the second-order Booth algorithm
Generate and output 4. Note that Y [9] and Y [8] are indicated by “示” in FIG.

Therefore, in the second cycle of the operation, first, the 10-bit data held in the intermediate sum holding circuit 28 is converted by the sign extender 24 as shown in the seventh to ninth stages from the top in FIG. The two bits (two bits marked with “□” at the stage of “intermediate sum 1” in FIG. 5) are sign-extended, and the upper 10 bits after sign extension and the fourth part of 10 bits from the partial product generation circuit 36 The product B3 is added by the adder 26. Further, the shift register 44 is shifted to the lower 4 bits (right shift), and the sign extender 24 is shifted.
, And the lower 2 bits of the 10-bit data output from the adder 42 in the first cycle (the 2 bits marked with “☆” in the “intermediate sum 1” stage in FIG. 5). , And “product”, the upper 3rd and 4th bits of the 8 bits marked with “）” are held at the positions of the 3rd and 4th bits from the upper side of the shift register 44.

Further, in the second cycle of the operation, as shown in the ninth to eleventh stages from the top in FIG.
The sign extension unit 40 sign-extends the 10-bit data, which is the result of the addition, by 2 bits (2 bits indicated by “□” in the “first-stage output 2” stage in FIG. 5), 10 bits and 1 from partial product generation circuit 38
The 0-bit fifth partial product B4 is added by the adder 42, and 10-bit data as the addition result of the adder 42 is held in the intermediate sum holding circuit 28. Also,
The lower two bits of the output of the sign extender 40 (the two bits marked with a “☆” in the “first stage output 2” stage in FIG.
The upper 2 bits of the 8 bits marked with “◎” in the “product” stage are held in the upper 2 bit positions of the shift register 44.

As a result, at the time when the second cycle of the operation is completed, the lower 8 bits of the 16-bit data representing the product of the multiplicand X and the multiplier Y (“product” in FIG. 5)
Are stored in the shift register 44, and the upper 8 bits of the 16-bit data representing the product (the 8 bits indicated by the “」 ”mark in the“ product ”stage in FIG. 5) ) Is held in the lower 8-bit position of the intermediate sum holding circuit 28. Then, at this point, the multiplication ends.

In the second embodiment as well, the multiplicand holding circuit 10 and the bit extender 12 correspond to the multiplicand holding means, and the bit extender 14 and the multiplier holding circuit 16 correspond to the multiplier holding means. . The multiplier bit selection circuit 34
And the two partial product generation circuits 36 and 38 correspond to a first partial product generation circuit, and the multiplier bit selection circuit 34 and the partial product generation circuit 22 correspond to a second partial product generation circuit. Then, the sign extender 24, the adder 26, the sign extender 40,
The adder 42, the intermediate sum holding circuit 28, and the shift register 44 correspond to a partial product accumulative addition circuit, and the sign extenders 24 and 40 and the adders 26 and 42 correspond to addition means. , Intermediate sum holding circuit 28 and shift register 4
4 corresponds to the addition result holding means.

As described in detail above, in the iterative multiplier M2 of the second embodiment, the two partial product generation circuits 36, 3
8, two partial products are generated for each operation cycle, and the two partial products are once generated by the first-stage sign extender 24 and the adder 26 and the second-stage sign extender 40 and the adder 42. (During one cycle). Therefore, although two adders 26 and 42 are required as compared with the repetitive multiplier M1 of the first embodiment,
The multiplication can be completed in two cycles, and the operation speed is 2
Double.

In particular, also in the iterative multiplier M2 of the second embodiment, in the first cycle of operation, the addend selection circuit 32 sends the intermediate sum holding circuit 28 to the first-stage sign extender 24. , The partial product generation circuit 22
From the first partial product B0. Therefore, the iterative multiplier M2 of the second embodiment can also add the first partial product B0 and the second and third partial products B1 and B2 higher than the first partial product B0 from the first cycle of the operation. As a result, the calculation speed up to obtaining the product can be improved.

That is, for example, in the conventional iterative multiplier J3 shown in FIG. 15, two partial products are generated and added for each operation cycle as in the second embodiment. , The total number of partial products (= 5) is not divisible by the number of partial products (= 2) added for each cycle, and one remainder is required. However, a sufficient effect cannot be obtained in spite of the fact that is increased by one step. On the other hand, according to the iterative multiplier M2 of the second embodiment, the number of operation cycles required to obtain the product can be reduced very efficiently.

As described above, one embodiment of the present invention has been described. However, it is needless to say that the present invention is not limited to the above-described embodiments, but can take various forms. For example, in the iterative multiplier M1 of the first embodiment, the order of connection between the multiplicand holding circuit 10 and the bit extender 12 or the order of connection between the bit extender 14 and the multiplier holding circuit 16 may be changed. That is, even if the order of connection is changed, the multiplicand X of 8 bits is held by the 2-bit sign extension or 0 extension according to the switching signal and held by the multiplicand holding circuit 10 and the bit extender 12. Extender 14 and multiplier holding circuit 1
6, the 8-bit multiplier Y is 2-bit code-extended or 0-extended according to the switching signal and held. This is the same for the iterative multiplier M2 of the second embodiment.

The repetition multiplier M of each of the above embodiments is used.
In 1 and M2, as the operation cycle signal, a signal whose value changes in each cycle is used, but the present invention is not limited to this. For example, a clock signal that rises (or falls) in each cycle and an initialization signal are used as operation cycle signals, and the multiplicand holding circuit 10, the multiplier holding circuit 16,
Multiplier bit selection circuits 18 and 34 and augend selection circuit 3
Each of 2 can be configured to grasp the number of operation cycles based on the number of times the clock signal rises (or falls) after receiving the initialization signal.

On the other hand, the repetition multiplier M of each of the above embodiments
In M1 and M2, since the second-order Booth algorithm is used, the number of partial products to be generated can be reduced. You may comprise so that it may generate | generate by the algorithm other than the secondary booth algorithm.

The repetition multiplier M of each of the above embodiments is used.
1 and M2 execute signed multiplication and unsigned multiplication alternatively with common hardware, but the present invention provides a multiplier that performs only signed multiplication or only an unsigned multiplication. Can be applied in exactly the same way.

For example, the repetition multiplier M of the first embodiment
In 1, if the two bit extenders 12 and 14 are deleted, an iterative multiplier that performs only signed multiplication can be obtained. In the case of such a configuration, the number of cycles required to obtain a product is reduced from four to three as compared with the conventional repetitive multiplier J1 shown in FIG.
Can be reduced.

Further, the repetitive multipliers M1 and M2 of the above embodiments are configured to perform an 8-bit × 8-bit multiplication by inputting an 8-bit multiplicand X and a multiplier Y. The same can be applied to a repetitive multiplier that performs multiplication of another bit length.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an iterative multiplier according to a first embodiment.

FIG. 2 is a schematic diagram illustrating a multiplication operation of the iterative multiplier of FIG. 1;

FIG. 3 is an explanatory diagram illustrating an operation of a multiplier bit selection circuit in the iterative multiplier of FIG. 1;

FIG. 4 is a block diagram illustrating a configuration of an iterative multiplier according to a second embodiment.

FIG. 5 is a schematic diagram illustrating a multiplication operation of the iterative multiplier of FIG. 4;

FIG. 6 is an explanatory diagram illustrating an operation of a multiplier bit selection circuit in the iterative multiplier of FIG. 4;

FIG. 7 is a truth table illustrating a secondary Booth algorithm.

FIG. 8 is an explanatory diagram for explaining multiplication of 8 bits × 8 bits in a two's complement display format using a secondary Booth algorithm.

FIG. 9 is an explanatory diagram illustrating grouping of bits of a multiplier in a secondary Booth algorithm.

FIG. 10 is a block diagram showing a configuration of a conventional repetition multiplier that performs multiplication of 8 bits × 8 bits in a 2's complement format using a second-order Booth algorithm.

FIG. 11 is a schematic diagram illustrating a multiplication operation of the iterative multiplier of FIG.

FIG. 12 is an explanatory diagram illustrating an execution example in a case where switching is performed between 8 bit × 8 bit signed multiplication and unsigned multiplication by using a secondary Booth algorithm.

FIG. 13 is a block diagram illustrating a conventional iterative multiplier that performs signed multiplication and unsigned multiplication of 8 × 8 bits using a second-order Booth algorithm.

FIG. 14 is a schematic diagram illustrating a multiplication operation of the iterative multiplier of FIG.

FIG. 15 is a block diagram showing another conventional iterative multiplier that performs signed multiplication and unsigned multiplication of 8 bits × 8 bits using a second-order Booth algorithm.

FIG. 16 is a schematic diagram illustrating a multiplication operation of the iterative multiplier of FIG.

FIG. 17 is an explanatory diagram illustrating an operation of a multiplier bit selection circuit in the iterative multiplier of FIG. 15;

[Explanation of symbols]

M1, M2 ... iterative multiplier L1 ... first control line
L2: second control line 10: multiplicand holding circuit 12, 14: bit extender
16 Multiplier holding circuit 18, 34 Multiplier bit selection circuit 20, 22, 36, 38 ... Partial product generation circuit 24, 4
0: sign extender 26, 42 ... adder 28 ... intermediate sum holding circuit 30, 44 ... shift register 32 ... addend selection circuit

Claims (3)

[Claims] 1. A multiplicand holding means for holding a multiplicand, a multiplier holding means for holding a multiplier, and a multiplier held by the multiplier holding means in synchronization with a change in an operation cycle signal indicating the number of operation cycles. A first partial product generation circuit for selecting some of the constituent bits in order from the lower order and generating a partial product from the selected partial bits and the multiplicand held in the multiplicand holding means; And an addition means and an addition result holding means for holding the addition result of the addition means, wherein the addition means generates the value held in the addition result holding means by the first partial product generation circuit. In addition to adding the partial products, the addition result holding unit updates and holds the addition result of the addition unit in synchronization with a change in the operation cycle signal, so that the first partial product generation circuit A partial product accumulative addition circuit for accumulatively adding the partial products generated by the multiplier. The first partial product generation circuit comprises: And a partial product is generated by selecting some bits other than the least significant bit in order from the least significant bit to generate a partial product. When a cycle is indicated, a partial product is generated from a part of the least significant bits of the bits constituting the multiplier held in the multiplier holding means and the multiplicand held in the multiplicand holding means. And a partial product generation circuit, wherein when the operation cycle signal indicates the first operation cycle, the partial product generated by the second partial generation circuit is replaced with a value held in the addition result holding means. hand And a addend selection circuit for supplying the addend to the adder as an addend. 2. The multiplier according to claim 1, wherein the first partial product generation circuit and the second partial product generation circuit generate a partial product based on a secondary Booth algorithm. Multiplier characterized. 3. The multiplier according to claim 2, wherein the multiplicand holding means outputs a sign signal for setting the type of multiplication performed by the multiplier to one of signed multiplication and unsigned multiplication. When indicating the execution of multiplication with a sign, the multiplicand input from the outside is sign-extended with the most significant bit by 2 bits and held.
When the switching signal indicates the execution of unsigned multiplication, the multiplicand input from the outside is configured to hold the most significant bit side by extending 2 bits 0, and the multiplier holding means includes: When the switching signal indicates execution of signed multiplication, the multiplier input from the outside is sign-extended by 2 bits at the most significant bit and held, and when the switching signal indicates execution of unsigned multiplication. Is configured to hold a multiplier input from the outside by extending the most significant bit side by 2 bits 0, and holding the multiplier.