JP2000097987A - Method for inspecting polycrystalline silicon membrane transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize an inspecting method capable of accurately inspecting the reliability of a polycrystalline silicon membrane transistor. SOLUTION: The source and drain of a polycrystalline silicon membrane transistor 10b provided in a liquid crystal display are grounded, and a positive voltage of 10 V or higher is impressed to the gate. The polycrystalline silicon membrane transistor 10b is simultaneously maintained at temperatures equal to room temperature or higher for a predetermined time to impress stress. The amount of fluctuation in the threshold values of the polycrystalline silicon membrane transistor 10b prior to and after the impression of such voltage and temperature stress is measured, and its reliability is determined according to the amount of fluctuation in the measured threshold values.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for testing the reliability of a polycrystalline silicon thin film transistor formed on a glass substrate.

[0002]

2. Description of the Related Art Polycrystalline silicon thin film transistors have higher field-effect mobilities of electrons and holes and are superior in current driving capability as compared with thin film transistors using amorphous silicon. The application has been active. Polycrystalline silicon thin film transistors are used not only for switching elements of pixels but also for peripheral driving circuits such as shift registers, analog switches, and buffers.

However, when a polycrystalline silicon thin film transistor is used for a peripheral driving circuit, characteristics superior to those required for switching a pixel are required several times due to a limitation of an operation margin of the circuit. For example, mobility and threshold characteristics with little variation and high reliability of these values over a long period of time are required.

For this reason, conventionally, in order to evaluate the reliability of the mobility and the threshold value, a voltage stress or a temperature stress is applied to the polycrystalline silicon thin film transistor in a fixed or several types of cycles to change the characteristic of the device or to change the characteristics of the device. A so-called BTS test for examining the degree of deterioration has been performed to evaluate the reliability of the liquid crystal display device.

[0005]

However, according to the study of the present inventors, an accurate evaluation is not always obtained by the above-described BTS test for a polycrystalline silicon thin film transistor formed on a glass substrate. There was found. For example, in an N-channel polycrystalline silicon thin film transistor used in a peripheral driving circuit, the voltage applied to the gate during operation is usually the same or larger in the positive direction than the voltage applied to the source or drain. Value. Therefore, when a gate stress is applied to the polycrystalline silicon thin film transistor as a part of the BTS test, specifically, the source and the drain are set to 0 V, the gate is set to 20 V, and the temperature is set to 150 ° C.
When a stress is applied for 2000 seconds, the threshold value of the transistor normally shifts slightly to the positive side as time passes. This is explained by the fact that electrons are trapped in a trap level generated by applying a voltage stress to the gate or a trap level that already exists, and a negative charge is generated.

However, when a similar voltage stress is applied to a P-channel type polycrystalline silicon thin film transistor actually formed on a glass substrate, the threshold value may shift positively or negatively. is there. This is because, in a polycrystalline silicon thin film transistor formed on a glass substrate, a threshold shift in the positive direction occurs as described above, and at the same time, a threshold shift in mobile ionicity, which has been almost no problem in the LSI process, still remains a problem. This is because the threshold shift in the negative direction cannot be ignored.

The first cause of the threshold shift of the mobile ionic property is that the polycrystalline silicon thin film transistor has a lower manufacturing process of, for example, about 600 ° C. than the LSI, so that the gate oxide film and its surroundings are not formed. This is because excess hydrogen is present in the film, and this affects the threshold shift due to the application of voltage stress.

Alternatively, as a second reason, when compared with a silicon wafer or the like, an alkali element such as Na is present in a glass substrate, and during a process of forming a transistor, an alkali element such as Na is present in a gate oxide film or a film around the gate oxide film. This is because the ions are diffused into mobile ions.

In particular, if the threshold shift occurs due to the second reason, there is a possibility that the threshold shift may be so large that the reliability of the transistor itself and thus of the entire liquid crystal display device cannot be guaranteed. In this case, it is necessary to change the manufacturing process of the polycrystalline silicon thin film transistor to prevent the element from being contaminated by an alkali element. However, in the above-described BTS test, two phenomena of a shift in the positive direction and a shift in the negative direction overlap, which makes it difficult to accurately test the reliability of the polycrystalline silicon thin film transistor.
The present invention has been made in view of the above points, and an object of the present invention is to provide an inspection method capable of accurately inspecting the reliability of a polycrystalline silicon thin film transistor.

[0010]

In order to achieve the above object, according to the inspection method of the present invention, in order to inspect the reliability of a polysilicon thin film transistor against gate stress, the source and drain of the polysilicon thin film transistor are grounded, A voltage is applied to the gate so that the channel of the polycrystalline silicon thin film transistor is turned off, and the polycrystalline silicon thin film transistor is held at a temperature equal to or higher than room temperature for a certain period of time, before and after the application of the voltage and temperature. The method is characterized in that a variation amount of a threshold value of the polycrystalline silicon thin film transistor is measured, and reliability is determined according to the measured variation amount of the threshold value.

According to the inspection method of the present invention, a P-channel type polycrystalline silicon thin film transistor is
A BTS test is performed by applying a positive bias of 10 V or more to the gate.

In a P-channel type thin film transistor, during normal operation, a positive voltage compared to the source or drain and a voltage of 10 V or more are never applied as a gate voltage.

However, when such a voltage is applied, the threshold shift caused when electrons are trapped in the trap level and a negative charge is generated, and the threshold shift caused by mobile ions are both in the positive direction of the threshold. Therefore, the reliability of the polycrystalline silicon thin film transistor can be guaranteed by appropriately selecting the threshold shift amount allowed in the BTS test.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings. 1 and 2 show an example of a P-channel type and an N-channel type polycrystalline silicon thin film transistor used for a switching element of a liquid crystal display device or a peripheral driving circuit, respectively.

As shown in FIG. 1, a P-channel type polycrystalline silicon thin film transistor 10a has a conductive layer 16 made of a polycrystalline silicon film formed on a glass substrate 12 as a transparent insulating substrate via a silicon nitride film 14. Has,
The conductor layer includes an N-type channel layer 18, a P-type sole region 20 and a drain region 22 sandwiching the channel layer.

A gate electrode 26 made of a metal film is provided on the conductive layer 16 via a gate insulating film 24 made of silicon oxide, and is located in alignment with the channel layer 18. An insulating film 28 is formed so as to cover the gate electrode 26 and the gate insulating film 24. Further, on the insulating film 28, a source electrode 30 connected to the source region 20 via a contact hole and a contact hole are formed. A drain electrode 32 connected to the drain region 22 via the drain electrode 32 is formed.

As shown in FIG. 2, the N-channel type polycrystalline silicon thin film transistor 10b has substantially the same structure as the P type polycrystalline silicon thin film transistor 10a.
Only the configuration of the conductive layer 16 is different. That is, according to the N-type polycrystalline silicon thin film transistor 10b, the conductor layer 16 includes the P-type channel layer 34 facing the gate electrode 26, and the N-type source region 36 and the drain region located so as to sandwich the channel layer. 38.

When manufacturing a liquid crystal display device using the polycrystalline silicon thin film transistor having the above structure, first, C
After forming a silicon nitride film and an amorphous silicon film on a glass substrate by a VD method, the amorphous silicon film is crystallized by an excimer laser annealing method or the like to form a polycrystalline silicon thin film, which is used as a channel region. Are formed. A switching element of a pixel is constituted by these polycrystalline silicon thin film transistors,
A CMOS transistor including N-type and P-type transistors used for a peripheral driver circuit and the like is formed. Further, an alignment film, a protective film and the like are formed to form an array substrate of the liquid crystal display device.

On the other hand, a light-shielding film, a counter electrode, a color filter, and the like are formed on another glass substrate to form a counter substrate, and the liquid crystal display is arranged by interposing a liquid crystal layer between the array substrate and the liquid crystal layer. Form a panel. Subsequently, a liquid crystal display device is manufactured by mounting a backlight, a driving circuit, and the like on the liquid crystal display panel.

When the reliability of the polycrystalline silicon thin film transistor provided in the liquid crystal display device is inspected, an unnecessary portion of the peripheral portion of the array substrate is added to the unnecessary portion of the polycrystalline silicon thin film for the reliability inspection when the liquid crystal display device is manufactured. A silicon thin film transistor is formed. Then, after bonding the opposing substrate to the array substrate via the sealing material, the unnecessary portion is cut off and separated from the liquid crystal display device to obtain an inspection polycrystalline silicon thin film transistor for inspecting reliability.

The polycrystalline silicon thin film transistor for inspection is formed by the same process as other polycrystalline silicon thin film transistors of the liquid crystal display device, and the BTS test of the polycrystalline silicon thin film transistor for inspection is performed by the stress test of the liquid crystal display device. It can be a substitute.

In the inspection method of the present embodiment, the source electrode 30 and the drain electrode 32 are grounded to 0 V, and the gate voltage is applied to the P-channel polycrystalline silicon thin film transistor 10a for inspection formed as described above. Electrode 2
A positive voltage of 20 V, that is, a voltage opposite to the negative voltage applied to the gate electrode of the P-channel type polycrystalline silicon thin film transistor during normal operation is applied to 6. At the same time, the polycrystalline silicon thin film transistor 10a was heated to 150 ° C. by resistance heating and held in this state for 30 minutes to apply voltage stress and temperature stress to the polycrystalline silicon thin film transistor. Note that the positive voltage applied to the gate electrode 26, that is, the voltage at which the channel is turned off is selected to be 10 V or more and within the withstand voltage range.

The drain current-gate voltage characteristics of the polycrystalline silicon thin film transistor 10a were measured before and after the stress was applied. FIG. 3 shows the measurement results, and it can be seen from the figure that when the above-described stress is applied, the threshold value of the polycrystalline silicon thin film transistor 10a is shifted by 3.5 V in the negative direction.

FIG. 4 shows the result of measuring the amount of change in the threshold value of a transistor when a stress is applied to a P-channel type polycrystalline silicon thin film transistor formed by a plurality of different manufacturing processes under the same conditions as described above. As for the liquid crystal display device constituted by using the same polycrystalline silicon thin film transistor as the polycrystalline silicon thin film transistor for reliability inspection, the horizontal axis represents the point defect, the line defect, or the luminance when the liquid crystal display device is continuously operated. The vertical axis is the time when the display quality such as unevenness has decreased.
This is a graph created.

As is clear from FIG. 4, when the amount of change in the threshold value in the BTS test increases, the display quality of the liquid crystal display device deteriorates even in a short time. Based on this result, to guarantee normal operation for 10,000 hours or more, B
Only the liquid crystal display device in which the absolute value of the shift amount of the threshold value in the TS test was 0.2 V or less passed the reliability test. Therefore, when manufacturing a liquid crystal display device based on the above inspection results, the manufacturing process of the polycrystalline silicon thin film transistor is optimized so that the absolute value of the shift amount of the threshold in the BTS test is 0.2 V or less. By doing so, a highly reliable polycrystalline silicon thin film transistor,
And a liquid crystal display device.

FIG. 5 shows, for comparison, the source and drain of the N-channel type polycrystalline silicon thin film transistor 10b under the same stress conditions as described above, particularly, similarly to the P-channel type polycrystalline silicon thin film transistor. Shows the result of performing a BTS test by applying a voltage of 20 V to the gate electrode with a positive sign.

In FIG. 5, as compared with the measurement result of FIG. 4, there is not so much apparent dependency between the amount of change in the threshold value and the time when the display quality of the liquid crystal display device deteriorates.
According to the inspection method for a liquid crystal display device configured as described above, the reliability of a P-channel type polycrystalline silicon thin film transistor can be accurately inspected, and the polycrystalline silicon thin film transistor can be inspected according to the inspection result. By optimizing the manufacturing process or its design, highly reliable polycrystalline silicon thin film transistors,
And a liquid crystal display device.

[0028]

As described in detail above, according to the present invention,
By performing a test by applying a voltage stress such that the channel of the polycrystalline silicon thin film transistor is turned off, it is possible to provide a test method capable of accurately testing the reliability of the polycrystalline silicon thin film transistor, and as a result, The manufacturing process or the design of the polycrystalline silicon thin film transistor is optimized so that the amount of the characteristic variation is equal to or less than a certain value, and the polycrystalline silicon thin film transistor and the liquid crystal display device having excellent reliability can be obtained.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a P-channel polycrystalline silicon thin film transistor provided in a liquid crystal display device.

FIG. 2 is a cross-sectional view illustrating an N-channel polycrystalline silicon thin film transistor provided in a liquid crystal display device.

FIG. 3 is a graph showing a change in drain current-gate voltage characteristics of a P-channel thin film transistor before and after a BTS test.

FIG. 4 is a graph showing a relationship between a threshold fluctuation amount of a P-channel type polycrystalline silicon thin film transistor and a display failure occurrence time of a liquid crystal display device.

FIG. 5 is a graph showing a relationship between a threshold variation amount of an N-channel type polycrystalline silicon thin film transistor and a display failure occurrence time of a liquid crystal display device.

[Explanation of symbols]

 10a: P-channel type polycrystalline silicon thin film transistor 10b: N-channel type polycrystalline silicon thin film transistor 12: glass substrate 14: silicon nitride film 16: conductive layer 18: channel layer 20: source region 22 ... drain region 24: gate insulating film 26 ... Gate electrode 30 Source electrode 32 Drain electrode

Claims (5)

[Claims] An inspection method for inspecting the reliability of an N-channel or P-channel type polycrystalline silicon thin film transistor formed on a transparent insulating substrate, comprising: a step of grounding a source and a drain of the polycrystalline silicon thin film transistor; And applying a voltage such that the channel of the polycrystalline silicon thin film transistor is turned off, holding the polycrystalline silicon thin film transistor at a temperature equal to or higher than room temperature for a certain period of time, and before and after applying the voltage and temperature. A method for inspecting a polycrystalline silicon thin film transistor, comprising: measuring a fluctuation amount of a threshold value of a polycrystalline silicon thin film transistor; and determining reliability according to the measured fluctuation amount of the threshold value. 2. An inspection method for inspecting the reliability of a P-channel type polycrystalline silicon thin film transistor formed on a transparent insulating substrate, wherein a source and a drain of the polycrystalline silicon thin film transistor are grounded, and a gate of 10 V or more is provided. Applying a positive voltage, holding the polycrystalline silicon thin film transistor at a temperature equal to or higher than room temperature for a certain period of time, measuring a variation amount of a threshold value of the polycrystalline silicon thin film transistor before and after applying the voltage and the temperature, A method for inspecting a polycrystalline silicon thin film transistor, wherein reliability is determined in accordance with a variation amount of a measured threshold value. 3. When manufacturing an array substrate of a liquid crystal display device in which a plurality of display pixels respectively connected to a polycrystalline silicon thin film transistor are arranged, a P-channel type or an N-channel type inspection multi-chip is provided on a peripheral portion of the array substrate. A crystalline silicon thin film transistor is formed in the same manufacturing process as other polycrystalline silicon thin film transistors on the array substrate, and after bonding the array substrate and the opposing substrate, the periphery of the array substrate is cut off for the inspection. The polycrystalline silicon thin film transistor is taken out, the source and the drain of the polycrystalline silicon thin film transistor for inspection are grounded, and a voltage is applied to the gate so that the channel of the polycrystalline silicon thin film transistor for inspection is turned off. When the crystalline silicon thin film transistor is kept at a temperature above room temperature Holding, before and after the application of the voltage and temperature, measuring the amount of change in the threshold value of the polycrystalline silicon thin film transistor for inspection, and determining reliability according to the measured amount of change in the threshold value. Inspection method for a polycrystalline silicon thin film transistor. 4. When manufacturing an array substrate of a liquid crystal display device in which a plurality of display pixels respectively connected to the polycrystalline silicon thin film transistor are arranged, a p-channel type polycrystalline silicon thin film transistor for inspection is provided on a peripheral portion of the array substrate. ,
Formed in the same manufacturing process as other polycrystalline silicon thin film transistors on the array substrate, and after bonding the array substrate and the counter substrate, separating the peripheral portion of the array substrate to form the inspection polycrystalline silicon thin film transistor. Taking out, grounding the source and drain of the inspection polycrystalline silicon thin film transistor, applying a positive voltage of 10 V or more to the gate, and holding the inspection polycrystalline silicon thin film transistor at a temperature of room temperature or higher for a certain period of time; Measuring a variation amount of a threshold value of the inspection polycrystalline silicon thin film transistor before and after applying a temperature, and determining reliability according to the measured variation amount of the threshold value. Inspection method. 5. The semiconductor device according to claim 1, wherein said applied voltage is 10 V or more and lower than a withstand voltage of said polycrystalline silicon thin film transistor.
3. The method for testing a polycrystalline silicon thin film transistor according to the above item.