JP2000091429A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent degassing from the sidewall of a wiring groove and to suppress the lacking of embeddings of wirings in a heating process, either during the formation of metal which mainly has Cu or after its formation. SOLUTION: This manufacturing method for a semiconductor device having multilayer wiring structure is provided with a process for forming a wiring connection hole and a wiring groove in an interlayer insulating film 12 on a semiconductor substrate 11, a process for forming sidewalls 17a of high blocking property with respect to discharge of water from the sidewall of the wiring groove on the sidewall of the wiring groove, a process for stacking a barrier metal layer 13 on the whole face, a process for stacking a metal which mainly has Cu 14, which is a wiring material on the whole face, and a process for executing heat treatment, melting a metal which has Cu as the main component, leaving an embedding wiring 14a in the desired hole and the wiring groove and removing the metallic film of an surplus part and the barrier metal layer 13.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a buried wiring of a metal containing Cu as a main component.

[0002]

2. Description of the Related Art In the manufacture of a semiconductor device, when a wiring hole and a wiring groove are formed in an insulating film formed on a semiconductor substrate after an element is formed and a metal wiring mainly containing Cu is buried, usually, During or after Cu film formation, Cu is buried in holes or wiring grooves by heating.

At this time, in the heating step, if moisture is released (degas) from the side walls of the holes or the wiring grooves, the filling of the wiring is impaired and voids are generated, and the CMP (Chemical Mechanical When polishing is performed, there is a problem that a defect (notch) of the wiring occurs.

[0004] This problem will be described in detail below. FIG.
4A and 4B show cross sections of a substrate in a part of a process of forming a Cu embedded wiring in a conventional semiconductor device having a multilayer wiring structure.

First, as shown in FIG. 4 (a), a contact hole for ensuring conduction with the element and a wiring groove corresponding to an embedded wiring pattern are formed in an interlayer insulating film 32 on a semiconductor substrate (Si substrate) 31. Is formed using a dual damascene process.

Next, a barrier metal 33 is formed on the entire surface by sputtering, and Cu for buried wiring is formed on the entire surface by sputtering, and then the Cu film is melted by laser irradiation. By doing so, Cu34 is buried in the holes and the wiring grooves.

Subsequently, as shown in FIG. 4B, the Cu film and the barrier at an extra portion other than the wiring portion are formed so that Cu is left in the desired hole and the wiring groove to leave the Cu embedded wiring 34a. The metal layer 33 is polished and removed by the CMP method.

However, if moisture is released from the side wall of the hole in the heating step after the above-mentioned Cu film formation, the heating step shown in FIG.
As shown in FIG.
5 is generated and the CMP of the Cu film is performed in a later process.
As shown in (b), a defective portion 36 of the wiring occurs.
FIG. 5 is a plan view showing a state in which the deficient portion 36 of the Cu embedded wiring 34a is intermittently generated in the length direction on the side wall of the wiring groove.

[0009]

As described above, the conventional method for forming a buried Cu wiring requires the release of moisture from the side wall of a hole or a wiring groove during a heating process during or after the formation of Cu. There is a problem in that the embedding of the wiring is impaired, voids are generated, and the loss of the wiring is caused.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and prevents degassing from a side wall of a hole or a wiring groove in a heating step during or after the formation of a metal containing Cu as a main component. In addition, a method of manufacturing a semiconductor device capable of suppressing the loss of buried wiring and suppressing the occurrence of wiring loss when performing CMP of a metal film containing Cu as a main component in a later process, thereby realizing a good buried wiring. The purpose is to provide.

[0011]

A method of manufacturing a semiconductor device according to the present invention comprises the steps of forming a wiring connection hole and a wiring groove in an interlayer insulating film on a semiconductor substrate, and forming a wiring groove on at least a side wall of the wiring groove. A step of forming a sidewall having a high blocking property against moisture release from the side wall, a step of depositing a barrier metal layer on the entire surface, and a metal containing Cu as a main component as a wiring material on the entire surface And then, after performing a heat treatment to melt the metal containing Cu as a main component, a desired hole, a metal film in an extra portion so as to leave an embedded wiring in the wiring groove, and Removing the barrier metal layer.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings. 1 (a) to 2 (c)
1 shows a cross section of a substrate in a main step of a method for forming a buried Cu wiring in a semiconductor device having a multilayer wiring structure according to a first embodiment of the present invention.

First, as shown in FIG. 1A, a TEOS-based SiO ₂ film 12 is formed as an interlayer insulating film on a semiconductor substrate (eg, a Si substrate) 11 on which an element has been formed.
Flatten by the MP method.

Thereafter, a contact hole for ensuring conduction with the element and a wiring groove corresponding to the embedded wiring pattern connected to the contact hole are formed in the SiO ₂ film 12 using a dual damascene process.

Next, before embedding the Cu wiring, sidewalls having a high blocking property against moisture release (degas) from the side walls of the holes and the wiring grooves are formed on the side walls of the holes and the wiring grooves.

In this case, first, as shown in FIG. 1B, a P-SiN film 17 is formed as a sidewall material on the entire surface by P-CVD (plasma vapor deposition) to a thickness of 200 nm.
A film is formed to a degree. Further, as shown in FIG. 1 (c), the P-SiN film which is to be the side wall 17a is removed by removing the P-SiN film only in the flat portion by the whole surface etch-back method.
Leave the N film.

Next, as shown in FIG. 2A, after a WSiN film is formed on the entire surface as a barrier metal layer 13, Cu 14 for buried wiring is formed on the entire surface by sputtering to a thickness of 1 μm.
A film is formed to a degree.

Thereafter, as shown in FIG. 2B, the Cu 14 is melted by a laser irradiation method. Subsequently, as shown in FIG. 2 (c), the Cu film and the barrier metal layer 1 in extra places are formed so as to leave Cu only in desired holes and wiring grooves and leave the Cu embedded wiring 14a.
3 is polished and removed by the CMP method.

A Cu surface protective film (and a Cu diffusion preventing film) for preventing the surface of the Cu buried wiring 14a from being oxidized by a strong oxidizing atmosphere in a subsequent O ₂ plasma process is used. A film may be formed over the entire surface.

The method of embedding the Cu wiring in the above embodiment is as follows.
By embedding Cu14 into holes and wiring grooves, buried wiring 1
Before forming 4a, sidewalls 17a having a high blocking property against degas from the side walls of holes and wiring grooves are formed on the side walls.

According to such a method of embedding Cu wiring, degassing from the side walls of holes and wiring grooves is prevented during the heating step during or after the formation of Cu14, and the conventional example shown in FIG. Embedding defect (void) as shown in
35 can be suppressed. as a result,
When the CMP of the Cu film and the barrier metal layer is performed in a later step, it is possible to suppress the generation of the wiring defect 36 as shown in FIG. 4B of the conventional example, and to realize a good embedded wiring 14a. Become.

FIG. 3 shows that the Cu buried wiring 14a has intermittent wiring defects in the longitudinal direction along the side wall of the wiring groove as a result of employing the Cu wiring burying method of the above embodiment. No appearance is shown.

The side wall 17a not only has a high blocking property against degas, but also the Cu in the hole and the Cu buried wiring 14a in the wiring groove is formed in the interlayer insulating film 12 from the side wall of the hole and the wiring groove. It also has a function as a Cu diffusion prevention film for preventing diffusion.

In the above embodiment, the method of embedding the Cu wiring has been described. However, the same effects as in the above embodiment can be obtained also when the embedded wiring is formed by embedding a metal containing Cu as a main component.

In the above embodiment, the case where the contact hole and the wiring groove are formed has been described. However, the present invention relates to the case where the via hole and the wiring groove for the interlayer wiring are formed. In general, the present invention can be applied to a case where a hole for interlayer wiring and a wiring groove are formed, such as a case where a groove is formed simultaneously.

The material of the side wall 17a is not limited to the SiN film. When the SiN film is inconvenient, the same effect as in the above embodiment can be obtained by using a SiO film. Further, the barrier metal layer 13 is not limited to the WSiN film, but may be a layer containing a high melting point metal such as W, Ta, or Ti.

[0027]

As described above, according to the method of manufacturing a semiconductor device of the present invention, when a metal containing Cu as a main component is buried in a hole or a wiring groove to form an embedded wiring, the metal containing Cu as a main component is used. Prevents degassing from the side walls of holes and wiring grooves in the heating step during or after film formation, and suppresses the occurrence of wiring defects when performing CMP of a metal film containing Cu as a main component in a subsequent step. In addition, a good embedded wiring can be realized.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a part of main steps of a method for forming a buried Cu wiring according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a step that follows the step of FIG. 1;

FIG. 3 is a plan view showing a state in which a defect is not generated in a side wall portion of a wiring groove in a Cu embedded wiring formed by the steps of FIGS. 1 and 2;

FIG. 4 is a view showing a cross section of a substrate in a part of a conventional process of forming a Cu embedded wiring.

FIG. 5 is a plan view showing a state in which a defect is generated intermittently in the length direction on the side wall of the wiring groove in the Cu-buried wiring formed by the process of FIG. 4;

[Explanation of symbols]

11: semiconductor substrate, 12: interlayer insulating film (SiO ₂ film), 13: barrier metal layer, 14a: Cu embedded wiring, 17a: sidewall (P-SiN film).

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Kenichi Tomita 1 Komagi Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Inside the Toshiba Tamagawa Plant (72) Inventor Koichi Mase Komukai Toshiba, Kochi-ku, Kawasaki-shi, Kanagawa No. 1 town Toshiba Tamagawa Plant (72) Inventor Yoshitaka Matsui No. 1 Komukai Toshiba Town, Koyuki-ku, Kawasaki-shi, Kanagawa Prefecture Toshiba Tamagawa Plant Co., Ltd. (72) Inventor Kenji Iwade Koyuki-ku, Kawasaki-shi, Kanagawa 1 Muko Toshiba Town Co., Ltd. Toshiba Tamagawa Plant (72) Inventor Toshihiko Kitamura 1 Koko Toshiba Town, Koyuki-ku, Kawasaki-shi, Kanagawa Prefecture Co., Ltd. Toshiba Tamagawa Plant F-term (reference) 4M104 AA01 BB04 BB14 BB17 BB18 BB28 BB33 CC01 DD07 DD37 DD75 DD78 EE09 EE14 EE17 FF09 FF18 FF22 FF23 HH20 5F033 AA29 AA64 AA67 AA71 BA17 BA24 BA25 BA37

Claims (3)

[Claims] A step of forming a wiring connection hole and a wiring groove in an interlayer insulating film on a semiconductor substrate; and a side wall having a high blocking property against water release from a side wall of the wiring groove at least on a side wall of the wiring groove. Forming a barrier metal layer on the entire surface; depositing a metal mainly composed of Cu as a wiring material on the entire surface; and performing a heat treatment to melt the metal mainly composed of Cu. And removing a metal film and a barrier metal layer in unnecessary portions while leaving embedded wirings in desired holes and wiring trenches after the mounting. 2. The method of manufacturing a semiconductor device according to claim 1, wherein said sidewall is a SiN film or a SiO film. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the barrier metal layer is formed of at least one of W, Ta, and Ti.
A method for manufacturing a semiconductor device, comprising: