JP2000091382A - Mounting of semiconductor chip on multilayer wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for mounting a semiconductor chip on a multilayer wiring board, which can prevent the generation of swellings or crackings of an insulation layer in the most upper layer due to the air remaining in the inside space of a cylindrical conductor via hole, having a bottom and an opening on the upper end. SOLUTION: In an insulation layer 80 in the uppermost layer of a multilayer wring board 10, a through-hole 70 is formed which is a vacant conductor via hole 50 of a cylindrical shape having the bottom with its inside space which is exposed. When heating the multilayer wiring board 10 for connecting conductor bumps formed on electrodes of a semiconductor chip to a conductor pad 92 exposed in a through-hole 40 formed in the insulation layer 80 in the uppermost layer, the expanded air remaining in the inside space of the vacant conductor via hole 50 is released outside, through the through-hole 70 formed in the insulation layer 80 in the uppermost layer. Thereby, the insulation layer 80 in the uppermost layer swellings or crackings due to expanded air is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip mounting method used for flip-chip mounting a semiconductor chip on a multilayer wiring board formed by alternately stacking insulating layers and conductor patterns.

[0002]

2. Description of the Related Art With the recent high integration and high density of electronic devices, corresponding multilayer wiring boards called build-up substrates have been developed and used for various electronic devices. The multilayer wiring board 10 called this build-up board
As shown in FIG. 6, an insulating layer 14 made of an epoxy resin or the like and conductor patterns 16 and 90 made of a Cu layer or the like are alternately stacked on a core substrate 12 made of a glass epoxy resin or the like. ing. An uppermost insulating layer 80 constituting a solder resist layer is formed on the surface of the uppermost conductive pattern 90 and the insulating layer 14 on which the conductive pattern is formed. The uppermost conductive pattern 90 and the surface of the insulating layer 14 on which the conductive pattern is formed are covered with the uppermost insulating layer 80. The upper and lower conductor patterns 16 and 90 of the multilayer wiring board 10 are provided with a bottomed cylindrical conductor via 50 having an open upper end and provided vertically through an insulating layer 14 interposed between the conductor patterns 16 and 90.
Are electrically connected to each other. This conductor via 50
Insulating layer 1 interposed between upper and lower conductor patterns 16 and 90
4 is provided with a hole (not shown) vertically penetrating the insulating layer 14, and a conductive layer such as a Cu plating layer extends over the inner peripheral surface of the hole and the surface of the lower conductive pattern 16 exposed on the inner bottom surface of the hole. Are continuously provided and formed.

As shown in FIG. 6, a through hole 40 is provided in the uppermost insulating layer 80 constituting the solder resist layer, and the uppermost conductive pattern 90 is formed in the through hole 40. It is exposed on the conductor pad 92. Then, as shown in FIG. 7, the conductor bumps 32 such as solder bumps and Au stud bumps formed on the electrodes of the semiconductor chip 30 can be electrically connected to the conductor pads 92 exposed in the through holes 40. It is configured. The semiconductor chip 30 is configured to be flip-chip mounted on the multilayer wiring board 10.

In a multilayer wiring board 10 called a build-up board, as shown in FIG. 8, an uppermost conductor pattern 90 and an insulating layer 1 on which the conductor pattern is formed are formed.
The surface of the conductive via 50 electrically connects the uppermost conductive pattern 90 and the conductive pattern 16 therebelow.
, Except for the portion of the through hole 40 exposing the conductive pad 92 formed on the uppermost conductive pattern 90, the uppermost insulating layer 80 constituting a solder resist layer made of epoxy resin or the like is continuous. Covered.

[0005]

By the way, the surface of the uppermost conductive pattern 90 and the surface of the insulating layer 14 on which the conductive pattern is formed are continuously covered with the uppermost insulating layer 80 constituting the solder resist layer. As shown in FIG. 8, the uppermost insulating layer 80 is not uniformly filled in the inner space of the bottomed cylindrical conductive via 50 whose upper end is open in the multilayered wiring board 10 as shown in FIG. The void 20 was present in the space inside the conductive via 50. This is because an insulating layer precursor (not shown) for forming an uppermost insulating layer 80 constituting a solder resist layer on the surface of the uppermost conductive pattern 90 and the insulating layer 14 on which the conductive pattern is formed.
Is applied in a layered form, the viscosity of the insulating layer precursor for forming a solder resist layer made of an epoxy resin or the like is high, and the insulating layer precursor hinders the air remaining in the space inside the conductive via 50. This is because it is impossible to smoothly and uniformly flow into the inside space of the minute diameter of the bottomed cylindrical conductor via 50 whose upper end is open. Incidentally, the viscosity of the insulating layer precursor for forming a solder resist layer made of an epoxy resin is as high as 100 poise or more.

As a result, as described above, when the semiconductor chip 30 is flip-chip mounted on the multilayer wiring board 10 and the multilayer wiring board 10 is subjected to a heat treatment for solder reflow or the like as described above, The air remaining in the void 20 in the space inside the conductor via 50 expands, and the air causes the uppermost insulating layer 80 to expand, and the air causes the uppermost insulating layer 80 to crack. In extreme cases, the air exploded the uppermost insulating layer 80. The swelling generated in the uppermost insulating layer 80 causes the semiconductor chip 30
Has been hindered in flip chip mounting. Further, the conductor pattern 90 and the conductor via 50 of the uppermost layer immediately below the cracked portion or the blasted portion of the uppermost insulating layer 80 were exposed to the outside air. Then, corrosion occurred in the conductor pattern 90 and the conductor via 50, and the electrical characteristics of the conductor pattern 90 and the conductor via 50 were impaired.

[0007] Further, as shown in FIG. 7, a semiconductor chip 30 to be flip-chip mounted on the multilayer wiring board 10 has:
It is normal to adhere to the multilayer wiring board 10 via the underfill material 60. In such a case, the conductor via 50 immediately below the uppermost insulating layer 80 of the multilayer wiring board 10
When the void 20 exists in the inner space of the semiconductor chip 3,
The air remaining in the void 20 in the space inside the conductor via 50 expands due to the heat generated by the zero, and the air causes cracks in the uppermost insulating layer 80 and the underfill material 60. Then, the adhesive strength of the semiconductor chip 30 to the multilayer wiring board 10 was reduced, and the good electrical connectivity of the electrodes of the semiconductor chip 30 to the conductor pads 92 was impaired.

The present invention has been made in view of such a problem, and a void is generated in a space inside a conductor via electrically connecting a top conductor pattern and a conductor pattern therebelow. The air remaining in the void in the space inside the conductor via causes swelling or cracks in the uppermost insulating layer, explosion of the uppermost insulating layer, It is an object of the present invention to provide a method for mounting a semiconductor chip on a multilayer wiring board (hereinafter, referred to as a semiconductor chip mounting method) that can prevent a crack from occurring in an underfill material adhered to a semiconductor device.

[0009]

In order to achieve the above object, a method of mounting a semiconductor chip according to the present invention is directed to a method of mounting a semiconductor chip on a multilayer wiring board formed by alternately stacking insulating layers and conductor patterns. A method for mounting a semiconductor chip to be mounted on a chip, the method including the following steps. A. In the uppermost insulating layer constituting the solder resist layer of the multilayer wiring board, a through hole exposing a conductive pad formed on the uppermost conductive pattern immediately below the insulating layer, and the uppermost conductive pattern And a through hole exposing an empty inner space of a bottomed cylindrical conductive via having an open upper end and electrically connecting the lower conductive pattern to the conductor pattern vertically through the insulating layer. Process. B. Electrically connecting conductive bumps formed on the electrodes of the semiconductor chip to the conductive pads exposed in the through holes, and flip-chip mounting the semiconductor chip on the multilayer wiring board. C. An underfill material is filled between the semiconductor chip and the multilayer wiring board below the semiconductor chip, and the semiconductor chip is bonded to the multilayer wiring board via the underfill material, and the semiconductor chip is provided below and / or below the semiconductor chip. A step of filling an underfill material in the empty inner space of the through-hole and the conductor via exposed in the through-hole arranged in a peripheral portion.

In this method of mounting a semiconductor chip,
In step A, in the uppermost insulating layer, in addition to the through holes exposing the conductive pads, the empty state of the conductive via electrically connecting the uppermost conductive pattern and the conductive pattern below the conductive pattern is formed. A through hole exposing the inner space is provided so that the empty inner space of the conductor via is not covered with the uppermost insulating layer. Therefore, in the step B, the multilayer wiring board is soldered to electrically connect the conductor bumps formed on the electrodes of the semiconductor chip to the conductor pads exposed in the through holes provided in the uppermost insulating layer. When heated in a heating furnace for reflow or the like, the heated and expanded air present in the empty inner space of the conductor via is passed through a through hole provided in the uppermost insulating layer. Can be released into the open air. The expanded air prevents the uppermost insulating layer from bulging, the uppermost insulating layer from cracking, or the uppermost insulating layer from exploding. Can be.

In the step C, an underfill material is filled between the semiconductor chip and the multilayer wiring board thereunder, and when the semiconductor chip is bonded to the multilayer wiring board via the underfill material, An underfill material is caused to flow into a through hole disposed below and / or in the periphery of a semiconductor chip and an empty inner space of a bottomed tubular conductive via having an open upper end exposed to the through hole. The underfill material is filled in the through hole and the space inside the conductor via exposed in the through hole.

[0012] Therefore, below the semiconductor chip or /
And a conductor via formed of a Cu plating layer or the like around the inner space of the conductor via exposed in the through hole arranged in the peripheral portion thereof is exposed to the outside air, and the conductor via corrodes and the like. The underfill material can prevent the electrical characteristics of the via from deteriorating.

The underfill material is for filling a very narrow gap between the semiconductor chip and the multilayer wiring board therebelow, and is made of a material having a very low viscosity and a very high permeability. Has become. Therefore, when the underfill material is caused to flow into a through hole disposed below the semiconductor chip and / or a peripheral portion thereof and the inside space of the conductor via exposed to the through hole, the through hole and the through hole The underfill material can smoothly and uniformly flow into the small-diameter inner space of the bottomed cylindrical conductor via whose upper end is exposed to the outside. The through hole and the space inside the conductor via connected to the through hole can be completely filled with the underfill material without voids.

In addition, as described above, the underfill material is completely and completely filled in the inner space of the conductor via which electrically connects the uppermost conductor pattern and the conductor pattern therebelow. However, since voids can be prevented from being generated in the space inside the conductor via, air remaining in the void generated in the space inside the conductor via expands due to heat generated by the semiconductor chip and the like, and the semiconductor chip is damaged. Cracks can be prevented from occurring in the underfill material adhered to the multilayer wiring board.

In the method of mounting a semiconductor chip according to the present invention, it is preferable that the through hole and the through hole are provided in the uppermost insulating layer in the following step A in the step A. a. An insulating layer precursor for forming a solder resist layer is applied to the surface of the uppermost conductive pattern and the insulating layer on which the conductive pattern is formed, and the uppermost conductive pattern and the surface of the insulating layer on which the conductive pattern is formed Covering with the insulating layer precursor, including the conductor via electrically connecting the uppermost conductor pattern and the conductor pattern therebelow. b. The insulating layer precursor is subjected to exposure and development treatment, the insulating layer precursor, through-holes that expose the conductive pads formed on the uppermost conductive pattern, the uppermost conductive pattern and the Forming a through hole exposing an empty inner space of a conductor via electrically connecting the lower conductor pattern to the lower conductor pattern; c. The insulating layer precursor having the through-hole and the through-hole formed therein is subjected to a curing treatment to form an uppermost insulating layer, and the through-hole exposing the conductive pad to the uppermost insulating layer. Providing a through hole exposing an empty inner space of the conductor via.

In this method of mounting a semiconductor chip,
In the step a, the uppermost conductive pattern and the surface of the insulating layer on which the conductive pattern is formed, including the conductive via electrically connecting the uppermost conductive pattern and the lower conductive pattern, It can be covered with an insulating layer precursor for forming a solder resist layer. Next, in the step b, the uppermost conductor pattern and the insulating layer precursor covering the surface of the insulating layer on which the conductor pattern is formed are subjected to exposure and development treatment, and the uppermost conductor A through hole exposing a conductor pad formed in a pattern, and a through hole exposing an empty inner space of a conductor via electrically connecting a conductor pattern of an uppermost layer and a conductor pattern therebelow. Can be provided. Next, in step c, the insulating layer precursor having the through-hole and the through-hole formed therein is subjected to a curing treatment to form the uppermost insulating layer. At the same time, a through hole exposing the conductive pad formed on the uppermost conductive pattern in the uppermost insulating layer, and a conductor electrically connecting the uppermost conductive pattern and the lower conductive pattern. And a through-hole exposing the empty inner space of the via.

Alternatively, in the method of mounting a semiconductor chip according to the present invention, in the above-mentioned step A, it is preferable that the through-hole and the through-hole are provided in the uppermost insulating layer in the following step. a. An insulating layer precursor for solder resist layer formation was applied by screen printing on the surface of the uppermost conductive pattern and the insulating layer on which the conductive pattern was formed, and the uppermost conductive pattern and the conductive pattern were formed. The surface of the insulating layer is covered with an insulating layer precursor, and the insulating layer precursor has a through hole exposing a conductive pad formed on the uppermost conductive pattern, and a conductive pattern on the uppermost layer and a conductive pattern thereunder. Forming a through hole exposing an empty inner space of the conductor via electrically connecting the conductive via. b. The insulating layer precursor having the through-hole and the through-hole formed therein is subjected to a curing treatment to form an uppermost insulating layer, and the through-hole exposing the conductive pad to the uppermost insulating layer. Providing a through hole exposing an empty inner space of the conductor via.

In this semiconductor chip mounting method,
In the step (a), a through hole exposing a conductor pad formed on the uppermost conductor pattern on the surface of the uppermost conductor pattern and the insulating layer on which the conductor pattern is formed; An insulating layer precursor provided with a through-hole exposing an empty inner space of a conductor via electrically connecting the pattern can be formed by screen printing. Next, in the step b, the insulating layer precursor is subjected to a curing treatment to form the uppermost insulating layer. At the same time, the through hole exposing the conductive pad formed in the uppermost conductive pattern is electrically connected to the uppermost insulating layer, and the uppermost conductive pattern and the lower conductive pattern are electrically connected to each other. And a through hole exposing the empty inner space of the conductor via.

[0019]

Next, embodiments of the present invention will be described with reference to the drawings. 1 to 5 show a preferred embodiment of a method for mounting a semiconductor chip according to the present invention, and FIGS. 1 to 5 are process explanatory diagrams of the method for mounting a semiconductor chip.
Hereinafter, a method of mounting the semiconductor chip will be described.

In the method of mounting a semiconductor chip shown in FIG. 1, as shown in FIG. 1, the uppermost insulating layer 80 constituting the solder resist layer of the multilayer wiring board 10 is provided on the uppermost conductive pattern 90 immediately below the insulating layer. The through hole 40 exposing the conductive pad 92 formed in the uppermost layer is provided through the uppermost insulating layer 80 vertically. At the same time, the uppermost conductive pattern 90 and the lower conductive pattern 16 are electrically connected to the uppermost insulating layer 80 constituting the solder resist layer by vertically passing through the insulating layer 14 interposed therebetween. A through hole 70 exposing the empty inner space of the bottomed cylindrical conductor via 50 having an open upper end is provided through the uppermost insulating layer 80 vertically. When the through holes 40 and the through holes 70 are provided in the uppermost insulating layer 80, the following is performed. As shown in FIG. 2, on the surface of the uppermost conductive pattern 90 during the formation of the multilayer wiring board 10 and the insulating layer 14 on which the conductive pattern is formed, an insulation for forming a solder resist layer made of an epoxy resin or the like is formed. The layer precursor 800 is applied in layers. Then, the conductor pattern 90 of the uppermost layer
And the surface of the insulating layer 14 on which the conductive pattern is formed, the uppermost conductive pattern 90 and the lower conductive pattern 16.
Are continuously covered with the insulating layer precursor 800, including the conductive vias 50 electrically connecting the. Next, the insulating layer precursor 800 is exposed and developed.
Then, as shown in FIG. 3, the insulating layer precursor 800
The through hole 40 exposing the conductor pad 92 formed on the uppermost conductor pattern 90 and the uppermost conductor pattern 9
A through hole 70 that exposes the empty inner space of the conductor via 50 that electrically connects the conductor pattern 16 with the conductor pattern 16 therebelow is formed. After that, the insulating layer precursor 800 in which the through-holes 40 and the through-holes 70 are formed is subjected to a curing treatment such as a heating treatment or an ultraviolet irradiation treatment. Then, as shown in FIG. 1, the uppermost insulating layer 8 constituting a solder resist layer continuously covering the uppermost conductive pattern 90 and the surface of the insulating layer 14 on which the conductive pattern is formed.
0 is formed. At the same time, the uppermost insulating layer 8
0, the through hole 40 exposing the conductor pad 92 and the through hole 70 exposing the empty inner space of the conductor via 50 are provided.

Alternatively, the uppermost insulating layer 8 is formed as follows.
0 is provided with the through hole 40 and the through hole 70 described above. FIG.
As shown in the figure, an insulating layer precursor 800 for forming a solder resist layer is screen-printed on the surface of the uppermost conductive pattern 90 during formation of the multilayer wiring board 10 and the insulating layer 14 on which the conductive pattern is formed. It is applied in layers.
Then, the surface of the uppermost conductive pattern 90 and the surface of the insulating layer 14 on which the conductive pattern is formed are placed on the insulating layer precursor 80.
It covers continuously with 0. At the same time, the through hole 40 exposing the conductor pad 92 formed on the uppermost conductor pattern 90, the uppermost conductor pattern 90, and the conductor pattern 16 thereunder are electrically connected to the insulating layer precursor 800. And a through hole 70 that exposes the empty inner space of the conductor via 50 connected to the through hole 70. After that, the insulating layer precursor 800 having the through hole 40 and the through hole 70 formed therein,
Hardening treatment such as heat treatment and ultraviolet irradiation treatment is performed. Then, as shown in FIG. 1, an uppermost insulating pattern 80 which forms a solder resist layer that continuously covers the uppermost conductive pattern 90 and the surface of the insulating layer 14 on which the conductive pattern is formed is formed. I have. At the same time, the through hole 40 exposing the conductor pad 92 formed on the uppermost conductor pattern 90 and the uppermost conductor pattern 90 and the conductor pattern 16 thereunder are electrically connected to the uppermost insulating layer 80. And a through hole 70 exposing an empty inner space of the conductive via 50 that is electrically connected.

Next, as described above, after forming the uppermost insulating layer 80 constituting the solder resist layer in which the through holes 40 and the through holes 70 are provided in the multilayer wiring board 10, as shown in FIG. A conductor bump 32 such as a substantially hemispherical solder bump or an Au stud bump formed on an electrode of the semiconductor chip 30 is formed on the conductor pad 92 exposed in the through hole 40 provided in the uppermost insulating layer 80. Electrically connected. Then, the semiconductor chip 30 is flip-chip mounted on the multilayer wiring board 10.

Thereafter, as shown in FIG. 5, an underfill material (a kind of adhesive) made of an epoxy resin or / and a polyimide resin is provided between the semiconductor chip 30 and the multilayer wiring board 10 therebelow. 60 are filled. Then, the semiconductor chip 30 is bonded to the multilayer wiring board 10 via the underfill material 60. At the same time, the through-hole 70 disposed below and / or in the periphery of the semiconductor chip 30 and the conductor via 50 exposed in the through-hole
The underfill material 60 flows into the empty inner space and the underfill material 60 fills the through hole 70 and the inner space of the conductor via 50 exposed in the through hole.

The method of mounting the semiconductor chip shown in FIGS. 1 to 5 comprises the above steps. In this semiconductor chip mounting method, as shown in FIG. 4, the conductor bumps 32 formed on the electrodes of the semiconductor chip 30 are formed on the conductor pads 92 exposed in the through holes 40 provided in the uppermost insulating layer 80. When the multilayer wiring board 10 is heated, for example, by being placed in a heating furnace for solder reflow, in order to electrically connect the conductor patterns 90 to each other, the conductor pattern 90 of the uppermost layer and the conductor pattern 16 thereunder are electrically connected. The heated and expanded air existing in the empty inner space of the conductor via 50 connected to the first through hole can be released into the outside air through the through hole 70 provided in the uppermost insulating layer 80. The expanded air causes swelling of the uppermost insulating layer 80, cracks of the uppermost insulating layer 80,
Alternatively, the uppermost insulating layer 80 can be prevented from exploding.

As shown in FIG. 5, when the semiconductor chip 30 is adhered to the multilayer wiring board 10 via the underfill material 60, the semiconductor chip 30 is placed below the semiconductor chip 30 or / and when the semiconductor chip 30 is bonded to the multilayer wiring board 10.
The underfill material 60 is allowed to flow into the through hole 70 arranged in the periphery thereof and the empty inner space of the conductor via 50 exposed to the through hole, and the underfill material 60 is exposed to the through hole 70 and the through hole. The underfill material 60 can be filled with the empty inner space of the conductor via 50. Then, the conductor via 50 formed of a Cu layer or the like around the inner space of the conductor via 50 is exposed to the outside air, and the conductor via 50 is corroded and the electrical characteristics of the conductor via 50 deteriorate. Can be prevented by the underfill material 60.

Further, since the underfill material 60 has extremely low viscosity and extremely high permeability, when the underfill material 60 is filled between the semiconductor chip 30 and the multilayer wiring board 10, the underfill material 60 has a low viscosity. 60 is an empty small-diameter inner space of a through-hole 70 disposed below and / or in the periphery of the semiconductor chip 30 and a bottomed cylindrical conductor via 50 having an open upper end exposed to the through-hole; Can be smoothly and uniformly flowed into Then, the conductor via 50
Can be completely filled with the underfill material 60 without voids. Incidentally, the viscosity of the underfill material 60 is 20 poise or less.

[0027]

As described above, according to the semiconductor chip mounting method of the present invention, when the semiconductor chip is flip-chip mounted on the multilayer wiring board, the uppermost conductive pattern of the multilayer wiring board and the lower part thereof are formed. Of a conductive via that has a bottom and is open at the upper end, which is electrically connected to the conductive pattern of the semiconductor via, and which is exposed in a through hole disposed below and / or in the periphery of the semiconductor chip. Can be completely filled by the underfill material without voids. Then, it is possible to reliably prevent a void in which air remains from being generated in the space inside the conductor via. As a result, it is possible to prevent the air remaining in the void in the above-described conductor via from expanding due to heat generated by the semiconductor chip and the like, thereby preventing the air from cracking the uppermost insulating layer and the underfill material. it can. Then, it is possible to prevent the good electrical connectivity between the electrodes of the semiconductor chip and the conductive pads of the multilayer wiring board from being impaired.

When connecting the conductive bumps formed on the electrodes of the semiconductor chip to the conductive pads of the multilayer wiring board, the uppermost conductive pattern of the multilayer wiring board is electrically connected to the conductive pattern thereunder. The empty inner space of the conductive via is exposed to a through hole provided in the uppermost insulating layer. Therefore, as described above,
In order to connect the conductor bumps formed on the electrodes of the semiconductor chip to the conductor pads of the multilayer wiring board, etc., when the multilayer wiring board is heated by being placed in a heating furnace for solder reflow, the uppermost conductive pattern is formed. The heated and expanded air existing in the empty inner space of the conductor via electrically connecting the conductive pattern and the conductor pattern therebelow is passed through the through-hole provided in the uppermost insulating layer to allow the air to pass through the outside air. Can escape smoothly. The air can prevent the uppermost insulating layer from cracking or swelling, and prevent the uppermost insulating layer from exploding. Then, the conductor pattern and the conductor via directly under the uppermost insulating layer are exposed to the outside air, and the conductor pattern and the conductor via are corroded, and the electrical characteristics of the conductor pattern and the conductor via deteriorate. Can be prevented.

[Brief description of the drawings]

FIG. 1 is a process explanatory view of a semiconductor chip mounting method of the present invention.

FIG. 2 is a process explanatory view of a semiconductor chip mounting method of the present invention.

FIG. 3 is a process explanatory view of a semiconductor chip mounting method of the present invention.

FIG. 4 is a process explanatory view of the semiconductor chip mounting method of the present invention.

FIG. 5 is a process explanatory view of the semiconductor chip mounting method of the present invention.

FIG. 6 is a partial cross-sectional view of a conventional multilayer wiring board.

FIG. 7 is a partially enlarged sectional view showing a conventional semiconductor chip mounting method.

FIG. 8 is a partially enlarged sectional view of a conventional multilayer wiring board.

[Explanation of symbols]

 Reference Signs List 10 multilayer wiring board 12 core substrate 14 insulating layer 16 conductive pattern 20 void 30 semiconductor chip 32 conductive bump 40 through hole 50 conductive via 60 underfill material 70 through hole 80 uppermost insulating layer 90 uppermost conductive pattern 92 conductive pad 800 Insulating layer precursor

Claims (3)

[Claims] 1. A semiconductor chip mounting method for flip-chip mounting a semiconductor chip on a multilayer wiring board formed by alternately stacking insulating layers and conductor patterns,
A method for mounting a semiconductor chip on a multilayer wiring board, comprising the following steps. A. In the uppermost insulating layer constituting the solder resist layer of the multilayer wiring board, a through hole exposing a conductive pad formed on the uppermost conductive pattern immediately below the insulating layer, and the uppermost conductive pattern And a through hole exposing an empty inner space of a bottomed cylindrical conductive via having an open upper end and electrically connecting the lower conductive pattern to the conductor pattern vertically through the insulating layer. Process. B. Electrically connecting conductive bumps formed on the electrodes of the semiconductor chip to the conductive pads exposed in the through holes, and flip-chip mounting the semiconductor chip on the multilayer wiring board. C. An underfill material is filled between the semiconductor chip and the multilayer wiring board below the semiconductor chip, and the semiconductor chip is bonded to the multilayer wiring board via the underfill material, and the semiconductor chip is provided below and / or below the semiconductor chip. A step of filling an underfill material in the empty inner space of the through-hole and the conductor via exposed in the through-hole arranged in a peripheral portion. 2. The method of mounting a semiconductor chip on a multilayer wiring board according to claim 1, wherein in the step A, the through-hole and the through-hole are provided in the uppermost insulating layer in the following step. a. An insulating layer precursor for forming a solder resist layer is applied to the surface of the uppermost conductive pattern and the insulating layer on which the conductive pattern is formed, and the uppermost conductive pattern and the surface of the insulating layer on which the conductive pattern is formed Covering with the insulating layer precursor, including the conductor via electrically connecting the uppermost conductor pattern and the conductor pattern therebelow. b. The insulating layer precursor is subjected to exposure and development treatment, the insulating layer precursor, through-holes that expose the conductive pads formed on the uppermost conductive pattern, the uppermost conductive pattern and the Forming a through hole exposing an empty inner space of a conductor via electrically connecting the lower conductor pattern to the lower conductor pattern; c. The insulating layer precursor having the through-hole and the through-hole formed therein is subjected to a curing treatment to form an uppermost insulating layer, and the through-hole exposing the conductive pad to the uppermost insulating layer. Providing a through hole exposing an empty inner space of the conductor via. 3. The method of mounting a semiconductor chip on a multilayer wiring board according to claim 1, wherein in the step A, the through-hole and the through-hole are provided in the uppermost insulating layer in the following step. a. An insulating layer precursor for solder resist layer formation was applied by screen printing on the surface of the uppermost conductive pattern and the insulating layer on which the conductive pattern was formed, and the uppermost conductive pattern and the conductive pattern were formed. The surface of the insulating layer is covered with an insulating layer precursor, and the insulating layer precursor has a through hole exposing a conductive pad formed on the uppermost conductive pattern, and a conductive pattern on the uppermost layer and a conductive pattern thereunder. Forming a through hole exposing an empty inner space of the conductor via electrically connecting the conductive via. b. The insulating layer precursor having the through-hole and the through-hole formed therein is subjected to a curing treatment to form an uppermost insulating layer, and the through-hole exposing the conductive pad to the uppermost insulating layer. Providing a through hole exposing an empty inner space of the conductor via.