JP2000091366A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JP2000091366A
JP2000091366A JP26212698A JP26212698A JP2000091366A JP 2000091366 A JP2000091366 A JP 2000091366A JP 26212698 A JP26212698 A JP 26212698A JP 26212698 A JP26212698 A JP 26212698A JP 2000091366 A JP2000091366 A JP 2000091366A
Authority
JP
Japan
Prior art keywords
semiconductor device
semiconductor
semiconductor chip
external electrode
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP26212698A
Other languages
Japanese (ja)
Other versions
JP3777822B2 (en
Inventor
Toshiki Nakayama
敏紀 中山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP26212698A priority Critical patent/JP3777822B2/en
Publication of JP2000091366A publication Critical patent/JP2000091366A/en
Application granted granted Critical
Publication of JP3777822B2 publication Critical patent/JP3777822B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device having especially high level of integration, which can achieve the substantial compactness and thin size, and the manufacturing method thereof. SOLUTION: For this manufacturing method, at the conducting plate comprising a copper plate and the like, etching is performed so that the part corresponding to external electrode-terminal forming part 201 is made to remain on one side of a semiconductor chip-mounting region. The chip mounting and the remaining land undergo wire bonding. Resin sealing is performed. The external electrode-terminal forming part 201 is divided by cutting, and an L-shaped electrode is formed at the corner part of the resin. A pair of the semiconductor package elements formed in this way are stuck together, to obtain a semiconductor device. Or the device is formed in series as a integrated body, or it is stuck together and bonded as an integrated body.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体チップを搭
載し、樹脂封止して形成される半導体装置の製造方法、
および半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a semiconductor chip mounted thereon and sealed with a resin.
And a semiconductor device.

【0002】[0002]

【従来の技術】従来の半導体装置の一例として、図7に
示す構造がある。この技術は、半導体装置用導電性板と
してのリードフレーム1上に半導体チップ2を接着剤3
を用いて設置し、導電性ワイヤ4を用いて半導体チップ
2とリードフレーム1とを接続する。次いで、チップ周
囲をトランスファーモールドと呼ばれる技術を使い樹脂
5で封止し、この封止樹脂5の側端面より突出したリー
ドフレーム1の部分をクランク状に折り曲げることによ
り半導体装置6を製造する。
2. Description of the Related Art As an example of a conventional semiconductor device, there is a structure shown in FIG. In this technique, a semiconductor chip 2 is attached to a lead frame 1 as a conductive plate for a semiconductor device by an adhesive 3.
The semiconductor chip 2 and the lead frame 1 are connected using the conductive wires 4. Next, the semiconductor device 6 is manufactured by sealing the periphery of the chip with a resin 5 using a technique called transfer molding, and bending a portion of the lead frame 1 protruding from a side end surface of the sealing resin 5 into a crank shape.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、このよ
うな半導体装置は、以下のような課題を有する。
However, such a semiconductor device has the following problems.

【0004】すなわち、トランスファーモールド技術を
用いるために、モールド用の金型やその駆動装置、ま
た、リードフレーム1を曲げるための金型とその駆動装
置が必要であり、非常に大きな設備投資を必要としてい
る。また、リードフレーム1を半導体装置毎に折り曲げ
るために、工数が多くかかり、半導体装置が高価にな
る。また、リードフレーム1が樹脂5より突出している
ことにより、半導体装置が大きくなり、実装した場合に
大きな面積を基板上で必要とし、製品としての小型化が
困難である。
That is, in order to use the transfer molding technique, a mold for molding and a driving device thereof, and a mold for bending the lead frame 1 and a driving device thereof are required. And In addition, since the lead frame 1 is bent for each semiconductor device, a large number of steps are required, and the semiconductor device becomes expensive. Further, since the lead frame 1 protrudes from the resin 5, the semiconductor device becomes large, and a large area is required on the substrate when mounted, and it is difficult to reduce the size of the product.

【0005】本発明は、このような従来技術の課題を解
決するものであり、その目的とするところは、従来に比
して大幅に小型、薄型にすることができ、特に集積度の
高い半導体装置とその製造方法を提供することにある。
SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and it is an object of the present invention to make a semiconductor device which can be made much smaller and thinner as compared with the conventional one, and in particular, a highly integrated semiconductor. An object of the present invention is to provide an apparatus and a method of manufacturing the same.

【0006】[0006]

【課題を解決するための手段】上記目的を達成するため
に、本発明に係る半導体装置は、半導体チップの電極と
外部電極端子部とを電気的導通を図って樹脂封止すると
ともに、前記封止樹脂のコーナ外表面部に前記外部電極
端子をL字状に露出形成させてなる半導体パッケージを
複数用いて、該各半導体パッケージにおける前記L字状
を形成する前記電極の一方の露出面を同一平面に位置す
るように前記半導体パッケージを貼り合わせ一体化して
形成されたことを特徴としている。この場合において、
前記半導体チップは、メモリ系の回路が形成されたもの
であることが望ましい。また、前記半導体装置は半導体
パッケージの外面に半導体チップもしくはチップ搭載領
域のダイパッドを露出させて構成すればよい。
In order to achieve the above-mentioned object, a semiconductor device according to the present invention is characterized in that an electrode of a semiconductor chip and an external electrode terminal are electrically sealed with a resin and the resin is sealed. Using a plurality of semiconductor packages in which the external electrode terminals are exposed and formed in an L-shape on a corner outer surface portion of a resin stopper, one exposed surface of the electrode forming the L-shape in each semiconductor package is the same. The semiconductor package is characterized in that it is bonded and integrated so as to be located on a plane. In this case,
It is desirable that the semiconductor chip has a memory circuit formed thereon. The semiconductor device may be configured such that a semiconductor chip or a die pad in a chip mounting region is exposed on an outer surface of a semiconductor package.

【0007】また、別の構成に係る半導体装置は、メモ
リ系回路が形成された半導体チップを搭載した半導体装
置であって、前記半導体チップの電極と外部電極端子部
とを電気的導通を図って構成される半導体装置構成要素
を複数連接配列して樹脂封止するとともに、前記封止樹
脂のコーナ外表面部に前記外部電極端子をL字状に露出
形成させた構成とした。
A semiconductor device according to another configuration is a semiconductor device on which a semiconductor chip on which a memory circuit is formed is mounted, in which an electrode of the semiconductor chip is electrically connected to an external electrode terminal. A plurality of semiconductor device constituent elements are connected and arranged to be resin-sealed, and the external electrode terminals are exposed and formed in an L-shape on corner outer surface portions of the sealing resin.

【0008】他の構成に係る半導体装置は、半導体チッ
プの電極と外部電極端子部とを電気的導通を図って構成
される半導体装置要素を複数連接配列して樹脂封止する
とともに、前記封止樹脂のコーナ外表面部に前記外部電
極端子をL字状に露出形成させてなる半導体パッケージ
ユニットを複数用いて、該各半導体パッケージユニット
における前記L字状を形成する前記電極の一方の露出面
を同一平面に位置するように前記半導体パッケージユニ
ット同士を貼り合わせ一体化して形成されたことを特徴
としている。
In a semiconductor device according to another configuration, a plurality of semiconductor device elements formed by electrically connecting an electrode of a semiconductor chip and an external electrode terminal are connected and sealed with a resin. A plurality of semiconductor package units each having the external electrode terminal exposed and formed in an L-shape on the outer surface of the corner of the resin are used, and one exposed surface of the electrode forming the L-shape in each semiconductor package unit is formed. The semiconductor package units are bonded and integrated so as to be located on the same plane.

【0009】本発明に係る半導体装置の製造方法は、第
1に1枚の導電性板上に複数の半導体装置構成要素の領
域を設定し、前記導電性板の片面にて前記半導体装置構
成要素の各領域において少なくとも半導体チップ搭載領
域の周囲に配置される外部電極端子形成領域を残してそ
の周囲に薄肉部を形成するエッチング工程と、各半導体
装置構成要素の各領域にて前記薄肉部としての半導体チ
ップ搭載領域上に半導体チップを搭載する工程と、前記
半導体チップと前記外部電極端子形成領域とを電気的に
導通させるボンディング工程と、前記導電性板の半導体
チップ搭載面側にて半導体チップおよび外部電極端子を
内包する樹脂封止工程と、前記導電性板の非エッチング
面側から少なくとも当該導電性板の薄肉部相当厚さ分を
研削除去することにより前記半導体チップ搭載領域と外
部電極形成領域相互間とを分離させる工程と、前記半導
体チップ搭載領域と外部電極形成領域相互間とを分離さ
せた後に複数の半導体装置構成要素の領域毎に切り離し
分断処理して半導体パッケージを形成する工程と、半導
体装置構成要素単位に分断された半導体パッケージを貼
り合わせ接合して一体化する工程と、からなる構成とし
た。この場合において、前記樹脂封止工程では導電性板
に搭載された半導体チップを全て一括樹脂封止すること
が望ましい。
A method for manufacturing a semiconductor device according to the present invention
A plurality of semiconductor device component regions are set on one conductive plate, and are arranged at least around the semiconductor chip mounting region in each region of the semiconductor device components on one surface of the conductive plate. An etching step of forming a thin portion around the external electrode terminal forming region, and a step of mounting a semiconductor chip on a semiconductor chip mounting region as the thin portion in each region of each semiconductor device component; A bonding step of electrically connecting the semiconductor chip to the external electrode terminal formation region, a resin sealing step of enclosing the semiconductor chip and the external electrode terminal on the semiconductor chip mounting surface side of the conductive plate; By grinding and removing at least a portion corresponding to a thin portion of the conductive plate from the non-etched surface side of the plate, the semiconductor chip mounting region and the external electrode formation region are removed. Forming a semiconductor package by separating the semiconductor chip mounting region and the external electrode forming region from each other, and then separating and separating the plurality of semiconductor device components into regions. Bonding and joining the semiconductor packages divided into device component units to integrate them. In this case, in the resin sealing step, it is preferable that all of the semiconductor chips mounted on the conductive plate be resin-sealed.

【0010】また、更に別の半導体装置の製造方法は、
1枚の導電性板上に複数の半導体装置構成要素の領域を
設定し、前記導電性板の片面にて前記半導体装置構成要
素の各領域において少なくとも半導体チップ搭載領域の
周囲に配置される外部電極端子形成領域を残してその周
囲に薄肉部を形成するエッチング工程と、各半導体装置
構成要素の各領域にて前記薄肉部としての半導体チップ
搭載領域上に半導体チップを搭載する工程と、前記半導
体チップと前記外部電極端子形成領域とを電気的に導通
させるボンディング工程と、前記導電性板の半導体チッ
プ搭載面側にて半導体チップおよび外部電極端子を内包
する樹脂封止工程と、前記導電性板の非エッチング面側
から少なくとも当該導電性板の薄肉部相当厚さ分を研削
除去することにより前記半導体チップ搭載領域と外部電
極形成領域相互間とを分離させる工程と、前記半導体装
置構成要素に複数をユニット単位として分断処理すると
ともに、ユニット内の外部電極端子形成領域を厚み方向
に切断することにより、封止樹脂のコーナ部に外部電極
端子をL字形状に臨ませる工程と、から構成した。
[0010] Still another method of manufacturing a semiconductor device is as follows.
A plurality of regions of semiconductor device components are set on one conductive plate, and external electrodes arranged on at least a periphery of a semiconductor chip mounting region in each region of the semiconductor device components on one surface of the conductive plate An etching step of forming a thin portion around the terminal forming region, and a step of mounting a semiconductor chip on a semiconductor chip mounting region as the thin portion in each region of each semiconductor device component; A bonding step of electrically connecting the external electrode terminal formation region to the external electrode terminal forming region; a resin sealing step of enclosing a semiconductor chip and external electrode terminals on the semiconductor chip mounting surface side of the conductive plate; By grinding and removing at least the thickness corresponding to the thin portion of the conductive plate from the non-etched surface side, the gap between the semiconductor chip mounting region and the external electrode formation region And separating the plurality of semiconductor device components into unit units, and cutting the external electrode terminal formation region in the unit in the thickness direction, thereby forming the external electrode terminals in the corner portions of the sealing resin. And a step of approaching an L-shape.

【0011】更に、他の構成に係る半導体装置の製造方
法は、1枚の導電性板上に複数の半導体装置構成要素の
領域を設定し、前記導電性板の片面にて前記半導体装置
構成要素の各領域において少なくとも半導体チップ搭載
領域の周囲に配置される外部電極端子形成領域を残して
その周囲に薄肉部を形成するエッチング工程と、各半導
体装置構成要素の各領域にて前記薄肉部としての半導体
チップ搭載領域上に半導体チップを搭載する工程と、前
記半導体チップと前記外部電極端子形成領域とを電気的
に導通させるボンディング工程と、前記導電性板の半導
体チップ搭載面側にて半導体チップおよび外部電極端子
を内包する樹脂封止工程と、前記導電性板の非エッチン
グ面側から少なくとも当該導電性板の薄肉部相当厚さ分
を研削除去することにより前記半導体チップ搭載領域と
外部電極形成領域相互間とを分離させる工程と、前記半
導体装置構成要素に複数をユニット単位として分断処理
するとともに、ユニット内の外部電極端子形成領域を厚
み方向に切断することにより、封止樹脂のコーナ部に外
部電極端子をL字形状に臨ませる工程と、半導体装置ユ
ニット単位に分断されたユニットパッケージを貼り合わ
せ接合して一体化する工程と、からなることを特徴とし
ている。
Further, in a method of manufacturing a semiconductor device according to another configuration, a plurality of regions of a semiconductor device component are set on one conductive plate, and the semiconductor device component is formed on one surface of the conductive plate. An etching step of forming a thin portion around the external electrode terminal forming region disposed at least around the semiconductor chip mounting region in each region, and forming the thin portion in each region of each semiconductor device component. Mounting the semiconductor chip on the semiconductor chip mounting area, bonding step for electrically connecting the semiconductor chip and the external electrode terminal formation area, and forming the semiconductor chip and the semiconductor chip on the semiconductor chip mounting surface side of the conductive plate. A resin sealing step of enclosing the external electrode terminals, and grinding and removing at least a portion corresponding to a thin portion of the conductive plate from the non-etched surface side of the conductive plate. Separating the semiconductor chip mounting region and the external electrode formation region from each other, performing a dividing process on the semiconductor device components in units of a plurality, and cutting the external electrode terminal formation region in the unit in the thickness direction. Accordingly, the method comprises the steps of: making the external electrode terminals face the L-shape at the corners of the sealing resin; and bonding and joining unit packages divided into semiconductor device units. And

【0012】[0012]

【発明の実施の形態】以下に、本発明に係る半導体装置
の製造方法および半導体装置の具体的実施の形態を図面
を参照して詳細に説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of a method for manufacturing a semiconductor device and a semiconductor device according to the present invention will be described in detail with reference to the drawings.

【0013】図1は第1の実施形態に係る半導体装置の
製造工程を示し、図2は同方法によって製造された半導
体装置を示し、図3は同半導体装置をハンダ実装した状
態の正面図を示している。
FIG. 1 shows a manufacturing process of the semiconductor device according to the first embodiment, FIG. 2 shows a semiconductor device manufactured by the same method, and FIG. 3 is a front view showing a state where the semiconductor device is solder-mounted. Is shown.

【0014】まず、第1実施形態に係る半導体装置が図
2に示されている。図示のように、この半導体装置10
は、一対の半導体パッケージ12を貼り合わせて1つの
半導体装置として構成したものである。半導体パッケー
ジ12を一つのチップサイズパッケージ(CSP)とし
て作成し、製造された一対の半導体パッケージ12同士
を接合一体化することにより一つの半導体装置10を作
成するようにしている。
First, a semiconductor device according to the first embodiment is shown in FIG. As shown, the semiconductor device 10
Is configured as a single semiconductor device by bonding a pair of semiconductor packages 12 together. The semiconductor package 12 is created as one chip size package (CSP), and a pair of manufactured semiconductor packages 12 are joined and integrated to create one semiconductor device 10.

【0015】まず、半導体パッケージ12は樹脂14に
より半導体チップ16を封止して構成されている。すな
わち、半導体チップ16の入出力電極パッド18と、当
該チップ16の片側に片寄せて配列された外部電極端子
20とがボンディングワイヤ22により電気的に導通さ
れている。半導体チップ16におけるボンディング側の
全体を覆って樹脂封止するとともに、チップ16の裏面
側は封止樹脂14から露出するように形成されている。
チップ16の一部が露出している封止樹脂14の一面の
コーナ部分にて、前記外部電極端子20がL字状に露出
するように形成させている。このような半導体パッケー
ジ12を一対を準備し、これらをボンディングワイヤ2
2側が対面するようにして接着結合することで半導体装
置10を作成している。このとき、半導体装置10にお
ける一平面の両縁辺に前記外部電極端子20の配列する
ように接合して貼り合わせ一体化するのである。
First, the semiconductor package 12 is formed by sealing a semiconductor chip 16 with a resin 14. That is, the input / output electrode pads 18 of the semiconductor chip 16 and the external electrode terminals 20 arranged on one side of the chip 16 are electrically connected by the bonding wires 22. The semiconductor chip 16 is formed so as to cover the entire bonding side of the semiconductor chip 16 with resin and to expose the back surface of the chip 16 from the sealing resin 14.
The external electrode terminals 20 are formed so as to be exposed in an L-shape at a corner portion of one surface of the sealing resin 14 where a part of the chip 16 is exposed. A pair of such semiconductor packages 12 is prepared, and these are connected to the bonding wires 2.
The semiconductor device 10 is manufactured by adhesive bonding so that two sides face each other. At this time, the external electrode terminals 20 are joined and bonded to both edges of one plane of the semiconductor device 10 so as to be arranged.

【0016】このような半導体装置10を製造する工程
を図1を参照して説明する。まず、図1(1)に示して
いるように、これは複数の半導体装置を複数同時に製造
するためのもので、複数の装置構成要素を形成できるよ
うな平面積を有する例えば銅板製導電性板24を準備す
る。この導電性板24には装置構成要素単位ごとに半導
体チップ搭載領域Cの1辺部に沿って配置される外部電
極端子形成領域Tのみをランド部として残し、図1
(2)に示しているように、その周囲に等方性エッチン
グにより表面層が除去された薄肉部26を形成し、この
薄肉部26は非エッチング面側からの研削により前記外
部電極端子形成領域Tの相互間を分離可能な深さに設定
し、ランド部は隣接するパッケージ構成要素の外部電極
端子形成部と共用するようにしている。
A process for manufacturing such a semiconductor device 10 will be described with reference to FIG. First, as shown in FIG. 1 (1), this is for manufacturing a plurality of semiconductor devices at the same time, and is a conductive plate made of, for example, a copper plate having a plane area capable of forming a plurality of device components. Prepare 24. In this conductive plate 24, only the external electrode terminal forming region T arranged along one side of the semiconductor chip mounting region C for each device component is left as a land portion.
As shown in (2), a thin portion 26 having a surface layer removed by isotropic etching is formed around the thin portion 26, and the thin portion 26 is ground by grinding from the non-etched surface side to form the external electrode terminal formation region. T is set to a separable depth, and the lands are shared with the external electrode terminal forming portions of the adjacent package components.

【0017】この導電性板24では、半導体チップ16
を搭載する部分を薄肉部26とし、外部電極端子形成部
201の両側の位置に半導体チップ16を搭載するよう
にしている。この搭載領域は、薄肉部26の表面の一部
である。厚肉部突起箇所である外部電極端子形成部20
1は、半導体チップ16の入出力電極パッド18からワ
イヤ22などで接続される部分となる。外部電極端子形
成部201は、独立した突起になるように薄肉部26よ
り厚くしてあるとともに、隣接するパッケージ構成要素
と共用するようにしているため、幅寸法は隣接するチッ
プ16からのボンディングワイヤ22をそれぞれ溶着で
きるスペースを確保できるように設定する。また、外部
電極形成部201の一部あるいは全部の上面には、ボン
ディングの際の接合性の向上の為に、図1(3)に示し
ているように、導電性めっき28を施す場合がある。
In the conductive plate 24, the semiconductor chip 16
Is mounted on the thin portion 26, and the semiconductor chip 16 is mounted on both sides of the external electrode terminal forming portion 201. This mounting area is a part of the surface of the thin portion 26. External electrode terminal forming portion 20 which is a thick portion projecting portion
Reference numeral 1 denotes a portion connected from the input / output electrode pad 18 of the semiconductor chip 16 by a wire 22 or the like. The external electrode terminal forming portion 201 is thicker than the thin portion 26 so as to be an independent projection and is shared with an adjacent package component. 22 are set so as to secure a space for welding. In addition, as shown in FIG. 1C, the conductive plating 28 may be applied to part or all of the upper surface of the external electrode forming portion 201 to improve the bonding property at the time of bonding. .

【0018】同じく、図1(3)の断面図に示すよう
に、導電性板24のダイ付け部(ダイパッド)の上に半
導体チップ16を接着剤30などを用いて搭載し、続い
て、図1(4)に示しているように、半導体チップ16
の入出力電極パッド18と導電性板24の外部電極形成
部201の上部平坦部を導電性ワイヤ22を用い接続す
る。
Similarly, as shown in the sectional view of FIG. 1C, the semiconductor chip 16 is mounted on the die attaching portion (die pad) of the conductive plate 24 using an adhesive 30 or the like. As shown in FIG. 1 (4), the semiconductor chip 16
The input / output electrode pad 18 and the upper flat portion of the external electrode forming portion 201 of the conductive plate 24 are connected using the conductive wire 22.

【0019】その後、図1(5)に示すように導電性板
24の上の突起が存在する面、すなわち半導体チップ1
6の搭載面のダイ付け部(ダイパッド)、外部電極形成
部201、半導体チップ16、導電性ワイヤ22の全て
を覆うように、樹脂14にて全体を封止する。封止した
のち、導電性板24を薄肉部26側、すなわち樹脂封止
されていない面すなわち非エッチング面側から、導電性
板24が露出している面から研削(あるいはカッティン
グ)する。その際の研削は、薄肉部24が完全になくな
るまで行う。すなわち、外部電極端子20が電気的に完
全に独立する厚み方向の研削面32に示す位置まで研削
する。この場合、半導体チップ16の底面は、外部電極
端子形成部201の上面より下方の位置にある為に、研
削面32まで研削する際には、半導体チップ16の下面
の一部は研削されることになる(図1(5)参照)。
Thereafter, as shown in FIG. 1 (5), the surface of the conductive plate 24 where the projections exist, that is, the semiconductor chip 1
The whole is sealed with the resin 14 so as to cover all of the die attaching portion (die pad), the external electrode forming portion 201, the semiconductor chip 16 and the conductive wire 22 on the mounting surface of No. 6. After sealing, the conductive plate 24 is ground (or cut) from the thin-walled portion 26 side, that is, from the surface that is not resin-sealed, that is, the non-etched surface side, from the surface where the conductive plate 24 is exposed. The grinding at that time is performed until the thin portion 24 is completely removed. That is, the external electrode terminals 20 are ground to a position shown on the ground surface 32 in the thickness direction in which the external electrode terminals 20 are completely completely electrically independent. In this case, since the bottom surface of the semiconductor chip 16 is located below the upper surface of the external electrode terminal forming portion 201, a part of the lower surface of the semiconductor chip 16 is ground when grinding to the grinding surface 32. (See FIG. 1 (5)).

【0020】ところで、図1(5)から明らかなよう
に、この実施例では複数のパッケージ要素単位が平面状
に多数同時に形成されるため、これらを分離するための
厚み方向の分断位置を外部電極端子形成部201を中央
から分断するように分断線34と、隣接半導体チップ1
6同士の分断線36が設定されている。これにより、各
半導体パッケージ12の一方のコーナ部分に図2に示す
ようなL字形状の外部電極端子20が形成される。図示
のように、実施形態では、L字形外部電極端子20は、
エッチング深さにもよるが、直方体のパッケージにおけ
る長辺に沿った側端面側で長く、パッケージ裏面に露出
した面すなわち半導体チップが露出したつ面が短くなる
ように設定されている。
By the way, as is apparent from FIG. 1 (5), in this embodiment, since a plurality of package element units are formed at the same time in a plane, the dividing position in the thickness direction for separating these is separated from the external electrode. The dividing line 34 and the adjacent semiconductor chip 1 are separated so as to divide the terminal forming portion 201 from the center.
The dividing lines 36 between the six are set. As a result, an L-shaped external electrode terminal 20 as shown in FIG. 2 is formed at one corner of each semiconductor package 12. As shown, in the embodiment, the L-shaped external electrode terminal 20 is
Although it depends on the etching depth, it is set to be long on the side end surface side along the long side of the rectangular parallelepiped package, and to shorten the surface exposed on the back surface of the package, that is, the surface on which the semiconductor chip is exposed.

【0021】なお、上記実施例では、外部電極端子形成
部201を半導体チップ16の片側だけに片寄せて配置
し、これにワイヤボンディングして樹脂封止させ、導伝
板24の研削による電極分離と、厚み方向に沿って装置
単位間を分離する分断線34、36で外部電極端子形成
部201の分断とチップ16間分断とによってパッケー
ジ要素を分割するような位置に設定したものである。
In the above embodiment, the external electrode terminal forming portion 201 is arranged only on one side of the semiconductor chip 16 and is wire-bonded to the semiconductor chip 16 for resin sealing. The package elements are set at such positions that the package elements are divided by dividing the external electrode terminal forming portions 201 and dividing the chips 16 by dividing lines 34 and 36 that separate the device units along the thickness direction.

【0022】このような研磨・分割処理により、図1
(6)に示しているように、半導体パッケージ12が多
数作成される。このパッケージ12は、当該パッケージ
12の片側の側縁にのみ外部電極端子20が配置形成さ
れる。このようにして製造された半導体パッケージ12
を一対の組み合わせとして、これらを背中合わせ状態、
すなわちワイヤボンディングを施した面どうしを接着剤
38により接合一体化して半導体装置10が出来上が
る。
By such a polishing and dividing process, FIG.
As shown in (6), many semiconductor packages 12 are created. In the package 12, the external electrode terminals 20 are arranged and formed only on one side edge of the package 12. The semiconductor package 12 thus manufactured
As a pair, these are back to back,
That is, the surfaces subjected to the wire bonding are joined and integrated by the adhesive 38 to complete the semiconductor device 10.

【0023】このような半導体装置10は、図3に示す
ように、パッケージを立設して基板実装することがで
き、基板40への実装面積を小さくすることができる利
点がある。特に、コーナL型の外部電極端子20はハン
ダ溶着した場合の溶着面積が大きいため、フィレット4
2が確実に形成されて安定した実装を行なえる。
As shown in FIG. 3, such a semiconductor device 10 has the advantage that a package can be erected and mounted on a substrate, and the mounting area on the substrate 40 can be reduced. In particular, since the corner L-shaped external electrode terminal 20 has a large welding area when soldered, the fillet 4
2 can be formed reliably and stable mounting can be performed.

【0024】このように当該実施形態では半導体装置の
高集積化が実現でき、また、個々にパッケージを作成し
た後に合体接合するので、良品を選別してから合体させ
ることが可能となり、歩留まりの向上効果が高い。な
お、半導体チップ52の電極54は図2において2列構
造のものへの適用例を示したが、近年ではチップ電極は
中央1列のものも存在するので、このような中央配列の
チップを用いることで分散処理が可能となる。
As described above, in this embodiment, high integration of the semiconductor device can be realized, and since the individual packages are formed and then joined together, it is possible to select good products and then join them, thereby improving the yield. High effect. In addition, FIG. 2 shows an example in which the electrode 54 of the semiconductor chip 52 is applied to a two-row structure. However, recently, there is a chip electrode having a single center line. This makes distributed processing possible.

【0025】次に、図4および図5には第2の実施形態
に係る半導体装置の製造方法の説明図と、当該方法によ
り製造された半導体装置50の斜視図を示す。この第2
の実施形態に係る半導体装置50は、半導体チップ52
の電極54と外部電極端子56とをワイヤ58で電気的
導通を図って構成される半導体パッケージ要素60を複
数直列に連接配列して樹脂62で封止するとともに、前
記封止樹脂62のコーナ外表面部に前記外部電極端子5
6をL字状に露出形成させて構成している。
Next, FIGS. 4 and 5 show an explanatory view of a method of manufacturing a semiconductor device according to the second embodiment and a perspective view of a semiconductor device 50 manufactured by the method. This second
The semiconductor device 50 according to the first embodiment includes a semiconductor chip 52
A plurality of semiconductor package elements 60 configured by electrically connecting the electrodes 54 and the external electrode terminals 56 with wires 58 are connected in series and sealed with a resin 62, and the outside of the corner of the sealing resin 62. The external electrode terminal 5 is provided on the surface.
6 is formed to be exposed in an L-shape.

【0026】このような半導体装置50は、図4に示し
ているように、導電板64を複数の領域に区分し、各区
分領域に各々半導体パッケージ要素60を形成する。こ
のとき、共通の外部電極端子形成部501を挟んで対象
に各要素60を配置すると共に、これらに連続的に直列
した配列となるようにして、半導体パッケージ要素60
がマトリックス状に配列するように構築する。チップ5
2、外部電極端子56、これらの導電用ワイヤ58の接
続、樹脂封入の処理は図1に示したものと同様の工程を
経て行なわれる。この実施形態ではマトリックス状に複
数の半導体パッケージ要素60を同時に配列している点
が図1の場合と異なる。なお、上記複数のエッチングを
形成しようとする方法は等方性エッチングとして行なう
ことが望ましい。等方性エッチングであるためエッチン
グ領域は奥に進むほどえぐれた状態となる。したがっ
て、薄肉部から立設した状態にある非エッチング領域
は、表面側に至るにしたがって迫り出し、オーバハング
状態となる。このため後工程で樹脂封止が行われるが、
樹脂内への埋め込み側の相当直径が大きくなり、これが
アンカとして作用するために薄肉部を研削除去して島と
して残されても樹脂から抜け出ることが防止される こ
のように配列された半導体パッケージ要素60を2個1
組のユニットとして半導体装置50が構成されるよう
に、図4に示している分離線66、68にしたがって分
離するのである。なお、1組となるパッケージ要素60
の数は2個に限らず、2以上の複数のパッケージ要素60
を1組のユニットとすることができるのは当然である。
これによって図5に示される半導体装置50が製造でき
る。更に、この図5の半導体装置50同士を一体接合す
ることで形成された例が図6の半導体装置70である。
このように構成することで、完成した半導体装置50,
70はメモリユニットとしてそのまま基板ソケットに入
れて用いるようにすることが可能である。
In such a semiconductor device 50, as shown in FIG. 4, the conductive plate 64 is divided into a plurality of regions, and a semiconductor package element 60 is formed in each of the divided regions. At this time, the semiconductor package elements 60 are arranged in such a manner that the respective elements 60 are arranged on the target with the common external electrode terminal forming portion 501 interposed therebetween, and are arranged continuously in series.
Are arranged in a matrix. Chip 5
2. The process of connecting the external electrode terminals 56, these conductive wires 58, and encapsulating the resin is performed through the same steps as those shown in FIG. This embodiment differs from the embodiment shown in FIG. 1 in that a plurality of semiconductor package elements 60 are simultaneously arranged in a matrix. It is desirable that the method for forming the plurality of etchings is performed as isotropic etching. Since the etching is isotropic etching, the etching region becomes more hollow as it goes deeper. Therefore, the non-etched region that is standing upright from the thin portion protrudes toward the surface side and is in an overhang state. For this reason, resin sealing is performed in a later process,
The equivalent diameter on the side embedded in the resin becomes large, and this acts as an anchor. Therefore, even if the thin portion is ground and removed and left as an island, it is prevented from falling out of the resin. Semiconductor package elements arranged in this manner. 60 two 1
The semiconductor devices 50 are separated according to the separation lines 66 and 68 shown in FIG. 4 so that the semiconductor device 50 is configured as a set of units. Note that one set of package elements 60
The number of package elements 60 is not limited to two, and may be two or more.
Can be a set of units.
Thereby, the semiconductor device 50 shown in FIG. 5 can be manufactured. Further, an example formed by integrally joining the semiconductor devices 50 of FIG. 5 is a semiconductor device 70 of FIG.
With this configuration, the completed semiconductor device 50,
70 can be used as it is in a board socket as a memory unit.

【0027】このような実施形態によれば、従来のメモ
リボードに用いられるメモリユニットに代わって極めて
小型化したメモリとして使用することができる。また、
メモリカードに用いる場合、従来のメモリボードではパ
ッケージの製造の後に基板実装を行なってメモリカード
が完成したが、この実施形態ではパッケージの製造と同
時にメモリカードとして完成するので、工程が簡易にな
る効果がある。
According to such an embodiment, the memory unit can be used as an extremely miniaturized memory instead of the memory unit used for the conventional memory board. Also,
When used for a memory card, a conventional memory board is mounted on a board after manufacturing a package to complete the memory card. In this embodiment, the memory card is completed simultaneously with the manufacture of the package, so that the process is simplified. There is.

【0028】[0028]

【発明の効果】以上説明したように、本発明によれば、
予め銅板などからなる導伝板に、半導体チップ搭載領域
の片側に外部電極端子形成部に相当する部分を残してい
わゆるハーフエッチングを行ない、チップ搭載と、残さ
れたランドとをワイヤボンディングし、樹脂封止を行な
い、外部電極端子形成部を分断して樹脂のコーナ部分に
L字型の電極ができるようにした半導体パッケージ要素
を一対貼り合わせて一つの半導体装置とし、または直列
に一体成形し、あるいはそれを貼り合わせて接合一体化
した半導体装置としたので、チップサイズパッケージが
接合、連接した集積度の高い半導体装置とすることがで
きる。この種の半導体装置のパッケージサイズを大幅に
小さく、薄型化しつつ、このような小型で薄型の半導体
装置を簡便な方法により製造することができる。
As described above, according to the present invention,
A so-called half-etching is performed on a conductive plate made of a copper plate or the like in advance so as to leave a portion corresponding to the external electrode terminal forming portion on one side of the semiconductor chip mounting region, and the chip mounting and the remaining land are wire-bonded, and a resin is formed. Sealing is performed, the external electrode terminal forming portion is divided, and a pair of semiconductor package elements that allow an L-shaped electrode to be formed at the corner portion of the resin are bonded to one semiconductor device, or integrally molded in series, Alternatively, since the semiconductor device is bonded and integrated by bonding it, a highly integrated semiconductor device in which a chip size package is bonded and connected can be obtained. Such a small and thin semiconductor device can be manufactured by a simple method while the package size of this type of semiconductor device is significantly reduced and thinned.

【図面の簡単な説明】[Brief description of the drawings]

【図1】第1の実施形態に係る半導体装置の製造方法の
工程図である。
FIG. 1 is a process chart of a method for manufacturing a semiconductor device according to a first embodiment.

【図2】同方法により製造された半導体装置の断面図と
斜視図である。
FIG. 2 is a cross-sectional view and a perspective view of a semiconductor device manufactured by the same method.

【図3】同半導体装置の実装状態の説明図である。FIG. 3 is an explanatory diagram of a mounting state of the semiconductor device.

【図4】第2実施形態に係る製造方法を説明するための
もので、導電板に半導体パッケージ要素を配列した平面
図である。
FIG. 4 is a plan view for explaining a manufacturing method according to a second embodiment, in which semiconductor package elements are arranged on a conductive plate.

【図5】同方法により製造された半導体装置の斜視図で
ある。
FIG. 5 is a perspective view of a semiconductor device manufactured by the same method.

【図6】第3実施形態の係る半導体装置の斜視図であ
る。
FIG. 6 is a perspective view of a semiconductor device according to a third embodiment.

【図7】従来の半導体装置の断面図である。FIG. 7 is a sectional view of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

10 半導体装置 12 半導体パッケージ 14 封止樹脂 16 半導体チップ 18 入出力電極パッド 20 外部電極端子 201 外部電極端子形成部 22 ボンディングワイヤ 24 導電性板 26 薄肉部 28 導電性めっき 30 接着剤 32 研削面 34 分断線 36 分断線 38 接着剤 40 実装基板 42 ハンダフィレット 50 第2実施形態の半導体装置 52 半導体チップ 54 電極パッド 56 外部電極端子 58 ワイヤ 60 半導体パッケージ要素 62 封止樹脂 64 導電板 66 分断線 68 分断線 70 第3実施形態の半導体装置 74 放電ユニット DESCRIPTION OF SYMBOLS 10 Semiconductor device 12 Semiconductor package 14 Sealing resin 16 Semiconductor chip 18 I / O electrode pad 20 External electrode terminal 201 External electrode terminal formation part 22 Bonding wire 24 Conductive plate 26 Thin part 28 Conductive plating 30 Adhesive 32 Grinding surface 34 minutes Disconnection 36 disconnection 38 adhesive 40 mounting substrate 42 solder fillet 50 semiconductor device of second embodiment 52 semiconductor chip 54 electrode pad 56 external electrode terminal 58 wire 60 semiconductor package element 62 sealing resin 64 conductive plate 66 disconnection 68 disconnection 68 70 Semiconductor Device of Third Embodiment 74 Discharge Unit

Claims (9)

【特許請求の範囲】[Claims] 【請求項1】 半導体チップの電極と外部電極端子部と
を電気的導通を図って樹脂封止するとともに、前記封止
樹脂のコーナ外表面部に前記外部電極端子をL字状に露
出形成させてなる半導体パッケージを複数用いて、該各
半導体パッケージにおける前記L字状を形成する前記電
極の一方の露出面を同一平面に位置するように前記半導
体パッケージを貼り合わせ一体化して形成されたことを
特徴とする半導体装置。
An electrode is formed between the electrode of the semiconductor chip and an external electrode terminal portion so as to establish electrical continuity, and the external electrode terminal is exposed and formed in an L-shape on a corner outer surface portion of the sealing resin. Using a plurality of semiconductor packages, the semiconductor packages are bonded and integrated so that one exposed surface of the electrode forming the L-shape in each semiconductor package is located on the same plane. Characteristic semiconductor device.
【請求項2】 前記半導体チップは、メモリ系の回路が
形成されたものであることを特徴とする請求項1に記載
の半導体装置。
2. The semiconductor device according to claim 1, wherein the semiconductor chip has a memory circuit formed thereon.
【請求項3】 前記半導体装置は半導体パッケージの外
面に半導体チップもしくはチップ搭載領域のダイパッド
を露出させてなることを特徴とする請求項1に記載の半
導体装置。
3. The semiconductor device according to claim 1, wherein the semiconductor device has a semiconductor chip or a die pad in a chip mounting area exposed on an outer surface of a semiconductor package.
【請求項4】 メモリ系回路が形成された半導体チップ
を搭載した半導体装置であって、前記半導体チップの電
極と外部電極端子部とを電気的導通を図って構成される
半導体装置構成要素を複数連接配列して樹脂封止すると
ともに、前記封止樹脂のコーナ外表面部に前記外部電極
端子をL字状に露出形成させてなる半導体装置。
4. A semiconductor device on which a semiconductor chip on which a memory system circuit is formed is mounted, wherein a plurality of semiconductor device components configured by electrically connecting electrodes of the semiconductor chip and external electrode terminals are provided. A semiconductor device in which the external electrode terminals are exposed and formed in an L-shape on a corner outer surface portion of the sealing resin while being connected and arranged to seal the resin.
【請求項5】 半導体チップの電極と外部電極端子部と
を電気的導通を図って構成される半導体装置要素を複数
連接配列して樹脂封止するとともに、前記封止樹脂のコ
ーナ外表面部に前記外部電極端子をL字状に露出形成さ
せてなる半導体パッケージユニットを複数用いて、該各
半導体パッケージユニットにおける前記L字状を形成す
る前記電極の一方の露出面を同一平面に位置するように
前記半導体パッケージユニット同士を貼り合わせ一体化
して形成されたことを特徴とする半導体装置。
5. A semiconductor device comprising a plurality of semiconductor device elements which are electrically connected between an electrode of a semiconductor chip and an external electrode terminal portion, are connected and sealed, and are resin-sealed. Using a plurality of semiconductor package units having the external electrode terminals exposed in an L-shape, one exposed surface of the electrode forming the L-shape in each semiconductor package unit is positioned on the same plane. A semiconductor device, wherein the semiconductor package units are bonded and integrated.
【請求項6】 1枚の導電性板上に複数の半導体装置構
成要素の領域を設定し、前記導電性板の片面にて前記半
導体装置構成要素の各領域において少なくとも半導体チ
ップ搭載領域の周囲に配置される外部電極端子形成領域
を残してその周囲に薄肉部を形成するエッチング工程
と、 各半導体装置構成要素の各領域にて前記薄肉部としての
半導体チップ搭載領域上に半導体チップを搭載する工程
と、 前記半導体チップと前記外部電極端子形成領域とを電気
的に導通させるボンディング工程と、 前記導電性板の半導体チップ搭載面側にて半導体チップ
および外部電極端子を内包する樹脂封止工程と、 前記導電性板の非エッチング面側から少なくとも当該導
電性板の薄肉部相当厚さ分を研削除去することにより前
記半導体チップ搭載領域と外部電極形成領域相互間とを
分離させる工程と、 前記薄肉部の研削除去により半導体チップ搭載領域と外
部電極形成領域相互間とを分離させた後に複数の半導体
装置構成要素の領域毎に切り離し分断処理して半導体パ
ッケージを形成する工程と、 半導体装置構成要素単位に分断された半導体パッケージ
を貼り合わせ接合して一体化する工程と、からなること
を特徴とする半導体装置の製造方法。
6. A region for a plurality of semiconductor device components is set on one conductive plate, and at least a periphery of a semiconductor chip mounting region in each region of the semiconductor device components on one surface of the conductive plate. An etching step of forming a thin portion around the external electrode terminal forming region to be disposed, and a step of mounting a semiconductor chip on the semiconductor chip mounting region as the thin portion in each region of each semiconductor device component A bonding step of electrically connecting the semiconductor chip and the external electrode terminal formation region, and a resin sealing step of including the semiconductor chip and the external electrode terminals on the semiconductor chip mounting surface side of the conductive plate; By grinding and removing at least a portion corresponding to a thin portion of the conductive plate from the non-etched surface side of the conductive plate, the semiconductor chip mounting area and the external power supply are removed. Forming a semiconductor chip mounting region and an external electrode forming region by grinding and removing the thin-walled portion, and separating and separating the semiconductor device mounting regions for each of a plurality of semiconductor device components. A method of manufacturing a semiconductor device, comprising: a step of forming a semiconductor package; and a step of laminating and joining semiconductor packages divided into constituent elements of a semiconductor device.
【請求項7】 前記樹脂封止工程では導電性板に搭載さ
れた半導体チップを全て一括樹脂封止することを特徴と
する請求項6に記載の半導体装置の製造方法。
7. The method of manufacturing a semiconductor device according to claim 6, wherein in the resin sealing step, all of the semiconductor chips mounted on the conductive plate are sealed with resin.
【請求項8】 1枚の導電性板上に複数の半導体装置構
成要素の領域を設定し、前記導電性板の片面にて前記半
導体装置構成要素の各領域において少なくとも半導体チ
ップ搭載領域の周囲に配置される外部電極端子形成領域
を残してその周囲に薄肉部を形成するエッチング工程
と、 各半導体装置構成要素の各領域にて前記薄肉部としての
半導体チップ搭載領域上に半導体チップを搭載する工程
と、 前記半導体チップと前記外部電極端子形成領域とを電気
的に導通させるボンディング工程と、 前記導電性板の半導体チップ搭載面側にて半導体チップ
および外部電極端子を内包する樹脂封止工程と、 前記導電性板の非エッチング面側から少なくとも当該導
電性板の薄肉部相当厚さ分を研削除去することにより前
記半導体チップ搭載領域と外部電極形成領域相互間とを
分離させる工程と、 前記半導体装置構成要素に複数を
ユニット単位として分断処理するとともに、ユニット内
の外部電極端子形成領域を厚み方向に切断することによ
り、封止樹脂のコーナ部に外部電極端子をL字形状に臨
ませる工程と、からなることを特徴とする半導体装置の
製造方法。
8. A region of a plurality of semiconductor device components is set on one conductive plate, and at least one semiconductor device component region is surrounded on at least a periphery of a semiconductor chip mounting region on each surface of the semiconductor device components on one surface of the conductive plate. An etching step of forming a thin portion around the external electrode terminal forming region to be disposed, and a step of mounting a semiconductor chip on the semiconductor chip mounting region as the thin portion in each region of each semiconductor device component A bonding step of electrically connecting the semiconductor chip and the external electrode terminal formation region, and a resin sealing step of including the semiconductor chip and the external electrode terminals on the semiconductor chip mounting surface side of the conductive plate; By grinding and removing at least a portion corresponding to a thin portion of the conductive plate from the non-etched surface side of the conductive plate, the semiconductor chip mounting area and the external power supply are removed. A step of separating the formation regions from each other, and dividing the semiconductor device component into a plurality of units, and cutting the external electrode terminal formation region in the unit in the thickness direction to form a corner portion of the sealing resin. Exposing the external electrode terminals to an L-shape.
【請求項9】 1枚の導電性板上に複数の半導体装置構
成要素の領域を設定し、前記導電性板の片面にて前記半
導体装置構成要素の各領域において少なくとも半導体チ
ップ搭載領域の周囲に配置される外部電極端子形成領域
を残してその周囲に薄肉部を形成するエッチング工程
と、 各半導体装置構成要素の各領域にて前記薄肉部としての
半導体チップ搭載領域上に半導体チップを搭載する工程
と、 前記半導体チップと前記外部電極端子形成領域とを電気
的に導通させるボンディング工程と、 前記導電性板の半導体チップ搭載面側にて半導体チップ
および外部電極端子を内包する樹脂封止工程と、 前記導電性板の非エッチング面側から少なくとも当該導
電性板の薄肉部相当厚さ分を研削除去することにより前
記半導体チップ搭載領域と外部電極形成領域相互間とを
分離させる工程と、 前記半導体装置構成要素に複数をユニット単位として分
断処理するとともに、ユニット内の外部電極端子形成領
域を厚み方向に切断することにより、封止樹脂のコーナ
部に外部電極端子をL字形状に臨ませる工程と、 半導体装置ユニット単位に分断されたパッケージユニッ
トを貼り合わせ接合して一体化する工程と、からなるこ
とを特徴とする半導体装置の製造方法。
9. A region of a plurality of semiconductor device components is set on one conductive plate, and at least a periphery of a semiconductor chip mounting region in each region of the semiconductor device components on one surface of the conductive plate. An etching step of forming a thin portion around the external electrode terminal forming region to be disposed, and a step of mounting a semiconductor chip on the semiconductor chip mounting region as the thin portion in each region of each semiconductor device component A bonding step of electrically connecting the semiconductor chip and the external electrode terminal formation region, and a resin sealing step of including the semiconductor chip and the external electrode terminals on the semiconductor chip mounting surface side of the conductive plate; By grinding and removing at least a portion corresponding to a thin portion of the conductive plate from the non-etched surface side of the conductive plate, the semiconductor chip mounting area and the external power supply are removed. A step of separating the formation regions from each other, and dividing the semiconductor device component into a plurality of units, and cutting the external electrode terminal formation region in the unit in the thickness direction to form a corner portion of the sealing resin. A step of exposing external electrode terminals to an L-shape, and a step of bonding and integrating package units divided into individual semiconductor device units.
JP26212698A 1998-09-16 1998-09-16 Manufacturing method of semiconductor device Expired - Lifetime JP3777822B2 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002118080A (en) * 2000-10-06 2002-04-19 Disco Abrasive Syst Ltd Method of dividing semiconductor plate and cutting blade

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002118080A (en) * 2000-10-06 2002-04-19 Disco Abrasive Syst Ltd Method of dividing semiconductor plate and cutting blade

Also Published As

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