JP2000082751A - Semiconductor memory and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory which can improve cell ratio by restraining increase of gate capacity and a manufacturing method thereof. SOLUTION: An N--diffusion layer 22 which becomes a low concentration region of an access transistor 25 is formed longer than an N--diffusion layer 18 which becomes a low concentration region of a driver transistor 24 by making a sidewall spacer which is used as a mask during formation of a source/ drain region of the access transistor 25 practically thicker than that of the driver transistor 24. As a result, ON-current of the access transistor 25 is made small. The sidewall spacer 15 and the sidewall spacer 18 are insulation films of different materials.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a semiconductor memory device constituting a memory cell of a static random access memory (SRAM) and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 5 shows an example of a conventional semiconductor memory device.
The fabrication method will be described. First, as shown in FIG.
A gate is formed on the substrate on which the gate oxide film 2 is formed by a known method.
After the oxide film 3 is formed, a gate electrode 4 is formed.
Implantation of phosphorus, for example, using the gate electrode 4 as a mask
By doing, N^- The diffusion layer 7 is formed. Subsequently, FIG.
As shown in (b), a first layer of a predetermined thickness is formed of an oxide film.
The gate spacer 4 and the gate oxide film 3
Is formed on the side wall.

[0005] Subsequently, as shown in FIG. 5C, for example, 30
An N ⁺ diffusion layer 8 is formed by ion-implanting arsenic at keV and 5E15 cm ⁻² . As a result, FIG.
(C) Medium, an access transistor ATr of a memory cell of an SRAM and a MOS serving as a driver transistor DTr
A field effect transistor (FET) is formed.

Here, it is said that a memory cell having a larger cell ratio operates more stably. Therefore, SRA
In order to secure a cell ratio in the M memory cells, it is necessary to make a difference between the current capabilities of the driver transistor and the access transistor. That is, the cell ratio referred to here is a ratio generally represented by (ON current of driver transistor) / (ON current of access transistor) in the SRAM. In order to improve the cell ratio, the cell ratio is higher than the ON current of the driver transistor. This is because it is necessary to reduce the ON current of the access transistor.

For this reason, conventionally, as shown in FIG. 6, the current of the access transistor ATr is suppressed by increasing the length L of the access transistor ATr or narrowing the width W. Further, the cell ratio is improved by increasing the thickness Tox of the gate oxide film of the access transistor ATr or by suppressing the current of the access transistor ATr by setting the substrate concentration.

As another example of a structure for providing a difference in current driving capability in a conventional semiconductor memory device, see Japanese Patent Application Laid-Open No.
A semiconductor memory device disclosed in Japanese Patent Application Publication No. 02428 is known. FIG. 7 is a sectional view of an example of the conventional semiconductor memory device. In FIG. 1, a field oxide film 2 is formed on a substrate 1, a gate electrode 4 is formed on one side of a memory cell portion via a gate oxide film 3, and an interlayer insulating film 12 is further formed thereon. Is formed. This insulating film 12
By using the gate electrode 4 as a mask and ion implantation of N-type impurities, a low-concentration N ^- diffusion layer 7 is formed.

On the side walls of the interlayer insulating film 12 and the gate electrode 4, a first side wall spacer 5 and a second side wall spacer 6 are formed so as to be narrower on the upper side. As a result, a high concentration N ⁺ diffusion layer 9 is formed by ion implantation of an N-type impurity. Thus, a MOS transistor 13 is formed. This MOS transistor 13 functions as an access transistor of a memory cell. The first sidewall spacer 5 and the second sidewall spacer 6
Are insulating films of the same material.

On the peripheral circuit side of the other region separated by the field oxide film 2, a gate electrode 4 is formed via a gate oxide film 3.
First sidewall spacers 5 are formed, and using these as a mask, low-concentration N ^- diffusion layer 8 is formed by ion implantation of N-type impurities in a self-aligned manner. Then, a high-concentration N ⁺ diffusion layer 10 is formed as a source / drain region in a self-aligned manner by ion implantation of N-type impurities using the first sidewall spacer 5 as a mask.
A second sidewall spacer 6 is formed outside the sidewall spacer 5 in such a shape that the upper side becomes thinner. Thus, a MOS transistor 14 is formed. This MOS transistor 14 functions as a driver transistor of a memory cell.

[0009] Thus, the conventional semiconductor memory device, compared to the MOS transistor 13 serving as access transistors, the MOS transistor 14 as a driver transistor N ^- N of the diffusion layer 8 MOS transistor 13 ^- diffusion By making the length shorter than that of the layer 7, a large ON current flows (lower resistance) and the cell ratio is made higher.

[0010]

However, in the conventional semiconductor memory device shown in FIG. 5, in order to suppress the current of the access transistor in order to improve the cell ratio, as shown in FIG. Gate length L
In this case, it is conceivable to increase the word line capacitance, and reducing the gate width W of the access transistor is also effective in improving the cell ratio. In this case, however, the bird's beak length is controlled. Is difficult,
Stable production of the access transistor becomes difficult.

In the conventional semiconductor memory device shown in FIG. 7, the first sidewall spacer 5 is formed by etch back, and the second sidewall spacer 5 is formed by another process in another step.
Since the sidewall spacer 6 is formed, the etch-back process is performed twice in total. However, since the first sidewall spacer 5 and the second sidewall spacer 6 are made of the same oxide film, the sidewall spacer 6 is formed. Spacer 5
In addition, since there is no selectivity between the etching of the field oxide film 2 and that of the field oxide film 2, the field oxide film 2 becomes thin during the etch-back process, the parasitic transistor is easily turned on, and the breakdown voltage in the memory cell deteriorates.

The present invention has been made in view of the above points,
An object of the present invention is to provide a semiconductor memory device capable of improving a cell ratio by suppressing an increase in gate capacitance and a method of manufacturing the same.

It is another object of the present invention to provide a semiconductor memory device capable of minimizing abrasion of a field oxide film by etching and a method of manufacturing the same.

[0014]

In order to achieve the above object, a semiconductor memory device according to the present invention comprises an SRA having a driver transistor and an access transistor formed on a substrate.
In a semiconductor memory device forming M memory cells, a high-concentration diffusion layer region serving as a source / drain region of a driver transistor is formed on a first side wall of a gate electrode.
The high-concentration diffusion layer region formed at the position defined by the side wall spacer and serving as the source / drain region of the access transistor is defined by the second side wall spacer formed outside the first side wall spacer. Characterized in that the structure is formed at the specified position.

In the present invention, the high-concentration diffusion layer serving as the source / drain region of the access transistor is located outside the high-concentration diffusion layer serving as the source / drain region of the driver transistor. The ON current of the access transistor can be made smaller than the current.

Further, in the semiconductor memory device of the present invention, the driver transistor and the access transistor each have a gate oxide film and a gate electrode laminated on a substrate, and a first film formed of an insulating film on a side wall of the gate oxide film and the gate electrode. A sidewall spacer is formed, and a second sidewall spacer made of an insulating film of a material different from the material of the first sidewall spacer is formed on a side wall of the first sidewall spacer.

According to the present invention, at least one of the first sidewall spacer and the second sidewall spacer can be an insulating film made of a material different from that of the field oxide film. At the time of forming at least one of the side wall spacers by etch-back, it is possible to have selectivity with the field oxide film.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device, comprising the steps of: forming a field oxide film on a substrate; Stacking a gate oxide film and a first gate electrode, and stacking a second gate oxide film and a second gate electrode of an access transistor of the SRAM memory cell; After forming a low concentration impurity diffusion layer using the first gate electrode, the second gate oxide film, and the second gate electrode as a mask, the first gate oxide film, the first gate electrode, and the second gate oxide film are formed. A third step of forming a first sidewall spacer made of an insulating film on each side wall of the gate oxide film and the second gate electrode, and a step of forming a second side wall formed on the second gate electrode and the side wall thereof; After covering the side wall spacer and the low-concentration impurity diffusion layer around it with the first resist, the first gate electrode and the first side wall spacer formed on the side wall thereof are used as a mask to form a high-concentration first spacer. Forming a fourth impurity diffusion layer on the substrate, and removing the first resist, and then forming an insulating film of a material different from the material of the first sidewall spacer on the side wall of the first sidewall spacer. A fifth step of forming a second side wall spacer, a first gate electrode, a first side wall spacer and a second side wall spacer formed on a side wall thereof, and a low concentration impurity diffusion layer therearound; And after covering the high-concentration impurity diffusion layer with a second resist, a first sidewall spacer and a second sidewall are sequentially formed on the second gate electrode and its side wall. A sixth step of forming a high-concentration second impurity diffusion layer on the substrate using the sidewall spacer as a mask, and removing the second resist to form a first gate electrode and a first gate electrode formed on the side wall thereof; A driver transistor including a side wall spacer and a second side wall spacer and a first impurity diffusion layer around the first and second side wall spacers; a second gate electrode and a first side wall spacer and a second side wall formed on the side wall thereof A seventh step of forming a spacer and an access transistor including a second impurity diffusion layer around the spacer.

According to the present invention, it is possible to manufacture an SRAM memory cell in which the ON current of the access transistor is smaller than the ON current of the driver transistor.

[0020]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of one embodiment of a semiconductor memory device according to the present invention. Referring to FIG. 1, a field oxide film 2 is formed on a substrate 1 to form a MOS transistor constituting a driver transistor 24 of an SRAM memory cell.
A type transistor and a MOS type transistor constituting the access transistor 25 are formed.

In the driver transistor 24, a gate electrode 4 is formed on a substrate 1 with a gate oxide film 3 interposed therebetween, a first sidewall spacer 15 is formed on the side wall of the gate electrode 4, and a second side wall spacer 15 is formed outside the first side wall spacer 15. A spacer 16 is formed. Further, using the gate electrode 4 as a mask, N
Implantation of low-concentration N ^- diffusion layer 18
Are formed in a self-aligned manner, and a high-concentration N ⁺ diffusion layer 19 is formed in a self-aligned manner by ion implantation of N-type impurities using the gate electrode 4 and the first sidewall spacer 15 as a mask. The diffusion layer 19 is a source / drain region.

On the other hand, the access transistor 25 has a gate electrode 4 formed on a substrate 1 with a gate oxide film 3 interposed therebetween, and a first sidewall spacer 1
5 are formed, and a second side wall spacer 16 is formed outside thereof. Further, by ion implantation of an N-type impurity using the gate electrode 4 as a mask, a low-concentration N ⁻ diffusion layer 22 is formed in a self-aligned manner, and the gate electrode 4, the first sidewall spacer 15, and the second sidewall A high-concentration N ⁺ diffusion layer 23 is formed in a self-aligned manner by ion implantation of N-type impurities using the spacer 16 as a mask. The diffusion layer 23 is a source / drain region.

That is, in this embodiment, the source
By making the side wall spacer used as a mask when forming the drain region, the access transistor 25 is substantially thicker than that of the driver transistor 24, the N ⁺ diffusion layer serving as the source / drain region of the access transistor 25 is formed. 23 is located outside of the N ⁺ diffusion layer 19 serving as the source / drain region of the driver transistor 24, whereby the access transistor 25 is smaller than the ON current of the driver transistor 24.
The on-state current is reduced to improve the cell ratio.

The first side wall spacer 15
The second sidewall spacer 16 and the second sidewall spacer 16 are insulating films made of different materials, and minimize the shaving amount of the field oxide film 2 when the first sidewall spacer 15 and the second sidewall spacer are formed by etch back. I try to suppress it.

Next, a method of manufacturing the memory cell of this embodiment will be described with reference to element cross-sectional views in respective manufacturing steps of FIGS. First, as shown in FIG. 2A, a field oxide film 2 is formed on a P-type silicon substrate 1 by a known method. Subsequently, as shown in FIG. 2B, a gate oxide film 3 having a thickness of, for example, 90.degree., For example, a gate electrode 4 made of polysilicon having a thickness of, for example, 2000.degree. For example, a low-concentration N ^- diffusion layer 17 is formed on the substrate 1 in a self-aligning manner by ion implantation of, for example, phosphorus of 50 keV and 1E13 cm ^-2 .

Subsequently, a silicon oxide film is formed on the entire surface of the device by CV.
After coating by a predetermined method such as the D method, the silicon oxide film is selectively etched back, and as shown in FIG.
A first sidewall spacer 15 of an oxide film of Å is formed. Therefore, the first sidewall spacer 15
Is the same material as the field oxide film 2. Note that the thickness of the first sidewall spacer 15 becomes smaller toward the upper portion.

Subsequently, of the two gate electrodes 4 shown in FIG. 2 (c), one of the gate electrodes 4 on the side to be an access transistor, the first sidewall spacer 15 formed on the side wall thereof, and 3A is formed as shown in FIG. 3A, and arsenic of, for example, 30 keV and 5E15 cm ^-2 is ion-implanted into a portion not covered with the resist 20. As a result, the high concentration N ⁺ diffusion layer is self-aligned using the gate electrode 4 on the side to be the driver transistor, which is not covered with the resist 20, and the first sidewall spacer 15 formed on the side wall thereof as a mask. 19 are formed.

[0028] The N ⁺ diffusion layer 19 is to be formed the first sidewall spacers 15 as a mask, the end portion is formed on a defined position in the first sidewall spacers 15, N ^- diffusion layer 17 is reduced in size to about the width of the first sidewall spacer 15 as indicated by 18 in FIG.

Next, after removing the resist 20 by a known method, the entire surface of the element is coated with a material different from the silicon oxide film, for example, a nitride film, and the nitride film is selectively etched back. As shown in FIG. 3B, a second sidewall spacer 16 having a thickness of, for example, 1200 ° is formed on the side wall of the first sidewall spacer 15. Note that the thickness of the second sidewall spacer 16 becomes smaller toward the upper portion.

Here, at the time of forming the second side wall spacer 16, a nitride film different from the silicon oxide film, which is the material of the field oxide film 2 and the first side wall spacer 15, is etched back. Therefore, since the silicon oxide film has selectivity to the silicon oxide film, the amount of etching of the field oxide film 2 at the time of this etch back can be minimized.

Subsequently, after the entire surface of the element is coated with a resist, a known method such as photolithography or the like is used to cover the element as shown in FIG.
As shown in FIG. 7, the gate electrode 4 on the side to be a driver transistor, the first sidewall spacer 15 formed on the side wall thereof, and the second sidewall spacer 16
Then, only the resist 21 covering the N ⁺ diffusion layer 19 serving as the drain / source region is left, and the other portions are removed.
Arsenic ions of keV and 5E15 cm ^-2 are ion-implanted.

As a result, the gate electrode 4 on the side to be an access transistor, which is not covered with the resist 21, and the first sidewall spacer 15 formed on the side wall thereof
And the second sidewall spacer 16 as a mask, a high-concentration N ⁺ diffusion layer 23 is formed in a self-aligned manner. Since the N ⁺ diffusion layer 23 is formed using the first sidewall spacer 15 and the second sidewall spacer 16 as a mask, its end is located at a position defined by the second sidewall spacer 16. It is formed, N ^-
The diffusion layer 17 is reduced in size to about the total thickness of the first sidewall spacer 15 and the second sidewall spacer 16, as indicated by 22 in FIG.

Therefore, the source of the access transistor
The N ⁺ diffusion layer 23 serving as the drain region is closer to the N ⁺ diffusion layer 1 serving as the source / drain region of the driver transistor.
Outside of 9. That is, the size of the low concentration region of the access transistor is longer than the size of the low concentration region of the driver transistor. Finally, by removing the resist 21 by a known method, the SRAM memory cell shown in FIG. 1 can be manufactured.

FIG. 4 is an equivalent circuit diagram of an example of a memory cell of the SRAM. In the figure, MOS transistors Tr1 and Tr2, whose sources are commonly grounded and whose gates are connected to the drains of the other transistors, are driver transistors, and their drains are separately connected to resistors (registers) R1 and R2. Connected to a common high-potential-side power supply terminal via the same to form a flip-flop.

Further, a gate is connected to the word line WL,
The drain (or source) is the bit line BL1, BL2
MOS transistors Tr3 and Tr connected to
Reference numeral 4 denotes an access transistor whose source (or drain) is connected to the drains of the driver transistors Tr1 and Tr2.

As is well known, in this memory cell, the access transistors Tr3 and Tr4 connect and disconnect the cell and the bit lines BL1 and BL2 in accordance with the voltage level of the word line WL. Since these are turned off, the driver transistor T
The cell including r1 and Tr2 is separated from the bit lines BL1 and BL2. At the time of reading, when the word line WL goes high, the access transistors Tr3 and Tr
4 is turned on, and at this time, the driver transistor Tr1
Is on, current is drawn from the bit line BL1 through the access transistor Tr3, but the potential of the bit line BL2 does not change because the driver transistor Tr2 is off.

Further, for example, the driver transistor Tr2
Is turned on, the bit line BL1 is set to the high level, the bit line BL2 is set to the low level, and the word line WL is set to the high level, so that the node Q1 is at the high level and the node Q2 is at the low level. Therefore, information for turning on the driver transistor Tr2 is written.

The driver transistor 24 in FIG. 1 is used as the driver transistors Tr1 and Tr2, and the access transistor 25 in FIG. 1 is used as the access transistors Tr3 and Tr4.

In the above embodiment, the first side wall spacer 15 formed on the side wall of the gate oxide film 3 is preferably made of the same material as the gate oxide film 3 in terms of characteristics. Although the second side wall spacer 16 is made of a nitride film, the present invention is not limited to this, and the first side wall spacer 15
May be a nitride film, the second sidewall spacer 16 may be an oxide film, or both the sidewall spacers 15 and 16 may be nitride films. Furthermore, the first
Since the side wall spacer 15 and the second side wall spacer 16 need only be formed of an insulating film,
Any insulating film having a selectivity with respect to the field oxide film 2 may be used.

[0040]

As described above, according to the present invention,
The high-concentration diffusion layer serving as the source / drain region of the access transistor is located outside the high-concentration diffusion layer serving as the source / drain region of the driver transistor. By making the size longer than the size of the low-concentration impurity diffusion layer region of the driver transistor, the ON current of the access transistor is made smaller than the ON current of the driver transistor, so that the gate dimensions and gate capacitance of the access transistor are made larger. Without this, the cell ratio can be improved.

According to the present invention, at least one of the first sidewall spacer and the second sidewall spacer is formed of an insulating film made of a material different from that of the field oxide film. Second
The first side wall spacer and the second side wall spacer have the selectivity to the field oxide film at the time of forming at least one of the side wall spacers by the etch back.
In the formation of at least one of the side wall spacers by the etch back, the amount of etching removal of the field oxide film can be minimized, and the withstand voltage can be improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of one embodiment of a semiconductor memory device of the present invention.

FIG. 2 is an element cross-sectional view of each step of the embodiment of the method for manufacturing a semiconductor memory device of the present invention (Part 1).

FIG. 3 is an element cross-sectional view of each step of the embodiment of the method for manufacturing a semiconductor memory device of the present invention (part 2).

FIG. 4 is an equivalent circuit diagram of an example of an SRAM memory cell.

FIG. 5 is an element cross-sectional view for explaining a method of manufacturing an example of a conventional semiconductor memory device.

FIG. 6 is an explanatory diagram of a cell ratio improving method in a conventional SRAM.

FIG. 7 is a sectional view of another example of a conventional semiconductor memory device.

[Explanation of symbols]

Reference Signs List 1 substrate 2 field oxide film 3 gate oxide film 4 gate electrode 15 first sidewall spacer 16 second sidewall spacer 17, 18, 22 N ⁻ diffusion layer 19, 23 N ⁺ diffusion layer 20 first resist 21st 2 resist 24, Tr1, Tr2 Driver transistor 25, Tr3, Tr4 Access transistor

Claims (6)

[Claims] 1. A semiconductor memory device comprising an SRAM memory cell having a driver transistor and an access transistor formed on a substrate, wherein a high-concentration diffusion layer region serving as a source / drain region of the driver transistor has a gate electrode. A high-concentration diffusion layer region formed at a position defined by a first sidewall spacer formed on the side wall of the access transistor and serving as a source / drain region of the access transistor is formed outside the first sidewall spacer. A semiconductor memory device having a structure formed at a position defined by the second sidewall spacer. 2. The driver transistor and the access transistor, wherein a gate oxide film and a gate electrode are respectively laminated on the substrate, and a first sidewall spacer made of an insulating film is formed on a side wall of the gate oxide film and the gate electrode. 2. A second sidewall spacer comprising an insulating film made of a material different from that of the first sidewall spacer is formed on a side wall of the first sidewall spacer. Semiconductor storage device. 3. The semiconductor device according to claim 1, wherein one of the first sidewall spacer and the second sidewall spacer is formed of an oxide film of the same material as the field oxide film. 3. The semiconductor memory device according to 2. 4. A first step of forming a field oxide film on a substrate, and laminating a first gate oxide film and a first gate electrode of a driver transistor of an SRAM memory cell on the substrate, A second step of stacking a second gate oxide film and a second gate electrode of an access transistor of the SRAM memory cell; the first gate oxide film and the first gate electrode; and the second gate oxide. After forming a low concentration impurity diffusion layer using the film and the second gate electrode as a mask, the first gate oxide film and the first gate electrode and the second gate oxide film and the second gate electrode are formed. A third step of forming a first side wall spacer made of an insulating film on each side wall; and forming the second gate electrode and the first side wall formed on the side wall thereof.
After covering the side wall spacer and the low concentration impurity diffusion layer around the side wall with a first resist, a high concentration is formed by using the first gate electrode and the first side wall spacer formed on the side wall thereof as a mask. Forming a first impurity diffusion layer on the substrate, and removing the first resist, and then forming a material of the first sidewall spacer on a sidewall of the first sidewall spacer. A fifth step of forming a second sidewall spacer made of an insulating film of a different material; and a step of forming the first gate electrode and the first gate electrode formed on a side wall thereof.
After covering the side wall spacer and the second side wall spacer and the low concentration impurity diffusion layer and the high concentration impurity diffusion layer around the second side wall spacer with a second resist, the second gate electrode and the side wall thereof are sequentially formed. The first formed in
A sixth step of forming a high-concentration second impurity diffusion layer on the substrate using the side wall spacers and the second side wall spacers as a mask; and removing the second resist to form the first gate. An electrode, the first side wall spacer and the second side wall spacer formed on the side wall thereof, the driver transistor including the first impurity diffusion layer around the first side wall spacer, the second side wall spacer, and the second gate electrode and the side wall thereof. A seventh step of forming the formed first and second sidewall spacers and the access transistor including the second impurity diffusion layer around the first and second sidewall spacers. A method for manufacturing a storage device. 5. The semiconductor device according to claim 4, wherein one of the first sidewall spacer and the second sidewall spacer is formed of an oxide film of the same material as the field oxide film. Manufacturing method of a semiconductor memory device. 6. The semiconductor memory according to claim 4, wherein both the first sidewall spacer and the second sidewall spacer are formed of an oxide film made of a different material from the field oxide film. Device manufacturing method.