JP2000077725A - Semiconductor package and manufacture thereof - Google Patents

Semiconductor package and manufacture thereof

Info

Publication number
JP2000077725A
JP2000077725A JP10256121A JP25612198A JP2000077725A JP 2000077725 A JP2000077725 A JP 2000077725A JP 10256121 A JP10256121 A JP 10256121A JP 25612198 A JP25612198 A JP 25612198A JP 2000077725 A JP2000077725 A JP 2000077725A
Authority
JP
Japan
Prior art keywords
metal substrate
semiconductor
semiconductor package
sealing resin
collective
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10256121A
Other languages
Japanese (ja)
Other versions
JP4215306B2 (en
Inventor
Makoto Nagayama
誠 長山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SHICHIZUN DENSHI KK
Original Assignee
SHICHIZUN DENSHI KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SHICHIZUN DENSHI KK filed Critical SHICHIZUN DENSHI KK
Priority to JP25612198A priority Critical patent/JP4215306B2/en
Publication of JP2000077725A publication Critical patent/JP2000077725A/en
Application granted granted Critical
Publication of JP4215306B2 publication Critical patent/JP4215306B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Led Device Packages (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor package of a structure, wherein the heat dissipation of the semiconductor package is enhanced by using a metal substrate and, at the same time, the production cost of the package is reduced, and a method of manufacturing the package. SOLUTION: This package has a structure, wherein a semiconductor 2 is die-bonded on one part of a metal substrate 1, an electrode on the semiconductor 2 is bonded on the other part of the substrate 1 and both parts of the substrate 1 are splitted, but are coupled with each other with a sealing resin 4, and the package has a structure wherein both parts of the substrate 1 are used also as an electrode terminal. Moreover, as a method of manufacturing the package, the following method is conducted: a multitude of semiconductors 2 are respectively die-bonded on prescribed positions on an aggregate metal board 100, electrodes on the semiconductors 2 are respectively wire-bonded on the other prescribed positions on the board 100, and, after a resin 4 for sealing the semiconductors 2 is filled in the whole surface of the board 100 and is cured. A processing of splitting each of the prescribed regions of the board 100 and each of the other prescribed regions of the board 100 leaving the sealing resin 4, and a processing of separating by cutting the board 100 and the resin 4 in each device, are performed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は半導体を基板上に実
装し、樹脂封止を行った半導体のパッケージの構造およ
びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package structure in which a semiconductor is mounted on a substrate and sealed with a resin, and a method of manufacturing the same.

【０００２】[0002]

【従来の技術】従来の半導体素子を用いたパッケージ型
のデバイスとして、例えばＬＥＤ発光素子がある。これ
らは、回路パターン（ボンディングおよび端子用の金属
性パターン）が表面に予め形成された絶縁性の回路基
板、例えば表面に銅箔のパターンを有するガラス繊維入
りエポキシ樹脂製基板（ガラエポ基板）あるいはＭＩＤ
基板（立体的な形状を有し、表面に金属メッキとエッチ
ングにより回路パターンを形成した樹脂製基板）上にま
ず多数のＬＥＤ素子を導電性接着剤を用いてダイボンデ
ィングし、更に個々にワイヤボンディングを行った後、
素子およびワイヤ部を樹脂封止し、その後ダイシング加
工により１個づつのＬＥＤ素子を含むデバイスに分割し
て製造されていた。2. Description of the Related Art As a conventional package type device using a semiconductor element, there is an LED light emitting element, for example. These are insulated circuit boards having a circuit pattern (metallic pattern for bonding and terminals) formed on the surface in advance, such as a glass fiber-containing epoxy resin board having a copper foil pattern on the surface (glass epoxy board) or MID.
First, a large number of LED elements are die-bonded using a conductive adhesive on a substrate (a resin substrate having a three-dimensional shape and a circuit pattern formed on the surface by metal plating and etching), and then individually wire-bonded After doing
The device and the wire portion are sealed with a resin, and then divided into devices each including one LED element by dicing to manufacture the device.

【０００３】以下従来技術を図面により具体的に述べ
る。図２（ａ）は第１の従来例であるＬＥＤパッケージ
デバイスの断面図を示す。６はガラエポ基板、即ちガラ
ス繊維を混入し強化されたエポキシ樹脂性の回路基板で
ある。その上下表面には銅箔７が接着されている。上面
の銅箔はエッチングにより形成された分割部７３によっ
て第１部分７１と第２部分７２に分割パターニングされ
ている。下面の銅箔は図示のように上面の各部分に応じ
たより狭い面積の部分が基板の端に形成されており、上
面の銅箔とは基板の側面に施されたメッキ皮膜で接続さ
れている。側面および下面のパターンはＳＭＤ（表面実
装型デバイス）用の電極となる。The prior art will be specifically described below with reference to the drawings. FIG. 2A is a sectional view of an LED package device according to a first conventional example. Reference numeral 6 denotes a glass epoxy board, that is, a circuit board made of epoxy resin reinforced by mixing glass fibers. Copper foil 7 is adhered to the upper and lower surfaces. The copper foil on the upper surface is divided and patterned into a first portion 71 and a second portion 72 by a divided portion 73 formed by etching. As shown in the drawing, the copper foil on the lower surface has a smaller area corresponding to each part of the upper surface formed at the end of the substrate, and the copper foil on the upper surface is connected by a plating film applied to the side surface of the substrate. . The patterns on the side surface and the lower surface serve as electrodes for SMD (Surface Mount Device).

【０００４】２はＬＥＤ素子で銅箔パターンの第１部分
７１上に例えば導電接着剤でダイボンディングされる。
３はボンディングワイヤであり、ＬＥＤ素子の電極と銅
箔パターンの第２部分７２とをワイヤボンディングで接
続している。４は封止樹脂でありデバイスを封入・保護
する。封止樹脂はＬＥＤの発する光の波長に対して透明
な材質を用いる。Reference numeral 2 denotes an LED element which is die-bonded on the first portion 71 of the copper foil pattern by using, for example, a conductive adhesive.
A bonding wire 3 connects the electrode of the LED element and the second portion 72 of the copper foil pattern by wire bonding. Reference numeral 4 denotes a sealing resin for enclosing and protecting the device. As the sealing resin, a material transparent to the wavelength of light emitted from the LED is used.

【０００５】図２（ｂ）は第２の従来例であるＬＥＤパ
ッケージデバイスの断面図を示す。８はＭＩＤ(Molded
Interconnection Device) 技法による立体樹脂基板であ
り、メッキ触媒が混入されて立体成形され、表面に金属
メッキ膜９が施されている。この金属メッキ膜はエッチ
ングにより形成された分割溝９３によって第１部分９１
と第２部分９２とに分割されている。立体樹脂基板８の
凹部を覆う第１部分９１の底にはＬＥＤ素子である半導
体２がダイボンディングされ、半導体２の上部電極と金
属メッキ膜の第２部分９２とはボンディングワイヤ３で
接続され、全体は封止樹脂４で封入されている。FIG. 2B is a sectional view of a second conventional LED package device. 8 is MID (Molded
This is a three-dimensional resin substrate formed by a technique of Interconnection Device), which is three-dimensionally molded with a plating catalyst mixed therein, and has a metal plating film 9 on its surface. This metal plating film is divided into first portions 91 by division grooves 93 formed by etching.
And a second portion 92. The semiconductor 2, which is an LED element, is die-bonded to the bottom of the first portion 91 covering the concave portion of the three-dimensional resin substrate 8, and the upper electrode of the semiconductor 2 and the second portion 92 of the metal plating film are connected by the bonding wire 3, The whole is sealed with a sealing resin 4.

【０００６】２つのメッキパターンは立体樹脂基板の側
面から裏面にまで導かれ、ＳＭＤ用電極となっている。
また立体樹脂基板８の凹部の斜面８１の表面に残された
金属メッキ膜は反射鏡の役割を演じ、ＬＥＤ素子の側方
に出た光を前方（画面の上方）に反射させて実質的な発
光強度を高めている。この反射面の形成が本第２の従来
例で立体樹脂基板を用いた理由である。[0006] The two plating patterns are guided from the side surface to the back surface of the three-dimensional resin substrate and serve as SMD electrodes.
Further, the metal plating film left on the surface of the inclined surface 81 of the concave portion of the three-dimensional resin substrate 8 plays the role of a reflector, and reflects light emitted to the side of the LED element forward (upward of the screen) to substantially reduce the light. The emission intensity is increased. The formation of the reflecting surface is the reason for using the three-dimensional resin substrate in the second conventional example.

【０００７】[0007]

【発明が解決しようとする課題】上記のような従来技術
においては、回路基板を構成する絶縁性樹脂の熱伝導性
が低いのでデバイスの放熱性があまり良くなかった。ま
た特殊性のある樹脂材料であってかつ表面に電極パター
ンを形成せねばならないため製造コストが高かった。In the prior art as described above, the heat dissipation of the device is not so good because the insulating resin constituting the circuit board has low thermal conductivity. In addition, the manufacturing cost is high because it is a special resin material and an electrode pattern must be formed on the surface.

【０００８】本発明の目的は、回路基板からの放熱性お
よび製造コストを大幅に改良した、半導体が内部基板に
実装されたパッケージの構造およびその製造方法を提供
することである。なお半導体とは所定の加工を施された
所定の材質の半導体ウエハから多数分割して切り出され
た個々の機能素子あるいは集積回路を主に意味し、これ
らはチップ型の半導体と呼ばれる場合も多いが、いわゆ
るチップ型であることが絶対的な必要条件ではない。It is an object of the present invention to provide a structure of a package in which a semiconductor is mounted on an internal substrate and a method of manufacturing the package, in which heat radiation from a circuit board and manufacturing cost are significantly improved. Note that a semiconductor mainly means individual functional elements or integrated circuits that are cut out from a semiconductor wafer of a predetermined material that has been subjected to a predetermined process by dividing into a large number, and these are often called chip-type semiconductors. However, it is not an absolute requirement that the device be a so-called chip type.

【０００９】[0009]

【課題を解決するための手段】上記問題点を解決するた
め、本発明の半導体パッケージの構造においては以下の
特徴を有する。 （１）金属基板の一部分に半導体がダイボンディングさ
れ、他の部分と前記半導体の電極がワイヤボンディング
され、前記金属基板の両部分が封止樹脂で覆われ、前記
金属基板の前記両部分は分割されているが前記封止樹脂
によって相互に連結された構造を有し、かつ前記金属基
板の両部分のそれぞれ少なくとも一部が端子となってい
ること。To solve the above problems, the structure of the semiconductor package of the present invention has the following features. (1) The semiconductor is die-bonded to a part of the metal substrate, the other part and the electrode of the semiconductor are wire-bonded, both parts of the metal substrate are covered with sealing resin, and both parts of the metal substrate are divided. But having a structure interconnected by the sealing resin, and at least a part of each of both parts of the metal substrate is a terminal.

【００１０】また本発明の半導体パッケージの構造にお
いては、更に以下の特徴の少なくとも１つを有すること
がある。 （２）前記ワイヤボンディングのワイヤは前記両部分を
分割する溝を越えて横断していること。The structure of the semiconductor package of the present invention may further have at least one of the following features. (2) The wire of the wire bonding crosses over the groove dividing the two portions.

【００１１】（３）前記金属基板は立体的に変形させる
加工が施されていること。 （４）前記金属基板にはハンダ付け性を向上させる表面
処理が施されていること。 （５）前記金属基板の表面の一部には絶縁皮膜が形成さ
れていること。(3) The metal substrate has been subjected to a three-dimensionally deforming process. (4) The metal substrate has been subjected to a surface treatment for improving solderability. (5) An insulating film is formed on a part of the surface of the metal substrate.

【００１２】上記問題点を解決するため、本発明の半導
体パッケージの製造方法においては以下の特徴を有す
る。 （６）集合金属基板上の所定領域に多数の半導体をダイ
ボンディングする工程と、前記半導体の各々の電極と前
記集合金属基板上の他の所定領域とをそれぞれワイヤボ
ンディングする工程と、前記半導体を封入する封止樹脂
を前記集合金属基板の少なくとも一方の面に充填しかつ
硬化させる工程とを上記の順で含み、その後前記集合金
属基板の各所定領域と各他の所定領域とを前記封止樹脂
を残して分割加工する工程と、前記集合金属基板および
前記封止樹脂をデバイス毎に分離する工程とを任意の順
序であるいは混合して含むこと。In order to solve the above problems, the method of manufacturing a semiconductor package according to the present invention has the following features. (6) a step of die-bonding a large number of semiconductors to a predetermined region on the collective metal substrate, a step of wire-bonding each electrode of the semiconductor to another predetermined region on the collective metal substrate, and Filling and curing at least one surface of the collective metal substrate with the sealing resin to be sealed in the above order, and thereafter sealing each predetermined region and each other predetermined region of the collective metal substrate with the sealing. The method may further include a step of performing a dividing process while leaving a resin and a step of separating the assembled metal substrate and the sealing resin for each device in an arbitrary order or in a mixture.

【００１３】また本発明の半導体パッケージの製造方法
においては、更に以下の特徴の少なくとも１つを有する
ことがある。 （７）前記集合金属基板の各所定領域と各他の所定領域
とを前記封止樹脂を残して分割加工する工程と、前記集
合金属基板および前記封止樹脂をデバイス毎に分離する
工程とは、それらの少なくとも一部が交互に行われるこ
と。 （８）前記集合金属基板の各所定領域と各他の所定領域
とを前記封止樹脂を残して分割加工する工程と、前記集
合金属基板および前記封止樹脂をデバイス毎に分離する
工程とは、それらの少なくとも一部が同時に行われるこ
と。The method for manufacturing a semiconductor package according to the present invention may further have at least one of the following features. (7) A step of dividing each predetermined region and each other predetermined region of the collective metal substrate while leaving the sealing resin, and a step of separating the collective metal substrate and the sealing resin for each device. That at least some of them are alternated. (8) A step of dividing each predetermined region and each other predetermined region of the collective metal substrate while leaving the sealing resin, and a step of separating the collective metal substrate and the sealing resin for each device That at least some of them are done simultaneously.

【００１４】（９）前記集合金属基板に製品の品質を向
上させる予備加工工程を前記ダイボンディング工程以前
に有すること。 （１０）前記予備加工工程は前記集合金属基板を立体的
に変形加工する工程であること。 （１１）前記予備加工工程は前記集合金属基板のハンダ
付け性を向上させる表面処理工程であること。 （１２）前記予備加工工程は前記集合金属基板の一部の
表面に絶縁皮膜を形成する工程であること。(9) A pre-processing step for improving the quality of a product on the collective metal substrate is provided before the die bonding step. (10) The pre-processing step is a step of three-dimensionally deforming the assembled metal substrate. (11) The preliminary processing step is a surface treatment step for improving the solderability of the collective metal substrate. (12) The preliminary processing step is a step of forming an insulating film on a part of the surface of the collective metal substrate.

【００１５】[0015]

【発明の実施の形態】図１は本発明の半導体パッケージ
の断面図で、（ａ）はその第１の実施の形態、（ｂ）は
その第２の実施の形態、（ｃ）はその第３の実施の形態
を示す。（ａ）図において、１は金属基板である。その
材質としては銅、アルミニウム、鉄、黄銅、青銅、その
他かなり自由な範囲から選択できる。選択の基準は、材
料コスト、強度、表面の安定性、表面処理とその容易
さ、ハンダ付け性、放熱性、塑性加工性、切削性等が考
慮される。1 is a cross-sectional view of a semiconductor package according to the present invention. FIG. 1A is a first embodiment, FIG. 1B is a second embodiment, and FIG. 3 shows a third embodiment. 1A, reference numeral 1 denotes a metal substrate. The material can be selected from copper, aluminum, iron, brass, bronze, and a fairly free range. Selection criteria take into account material cost, strength, surface stability, surface treatment and ease, solderability, heat dissipation, plastic workability, machinability, and the like.

【００１６】金属基板１は最終的には分割溝５によって
第１部分１１と第２部分１２とに分割されるが、半導体
２の実装、封止段階ではまだこの分割はなされず、両部
分は一体である。ＬＥＤ素子である半導体２は金属基板
１の第１部分１１となるべき領域内に導電性接着剤（銀
ペースト等）でダイボンディングされる。その上部電極
と金属基板１の第２部分１２となるべき領域とは例えば
金のボンディングワイヤ３で接続される。最終的形態に
おいてはボンディングワイヤ３は分割溝５を越えて張り
渡されることになる。The metal substrate 1 is finally divided into the first part 11 and the second part 12 by the dividing groove 5, but this division is not yet made at the stage of mounting and sealing the semiconductor 2, and both parts are not separated. It is one. The semiconductor 2, which is an LED element, is die-bonded with a conductive adhesive (silver paste or the like) in a region to be the first portion 11 of the metal substrate 1. The upper electrode and a region to be the second portion 12 of the metal substrate 1 are connected by, for example, gold bonding wires 3. In the final form, the bonding wire 3 is stretched over the dividing groove 5.

【００１７】４は封止樹脂で、例えばエポキシ樹脂を主
成分とし、ＬＥＤの発光の波長に対して透明度が高く、
半導体２とボンディングワイヤ３の周囲に充填されたあ
と固化され、デバイスを保護する。また樹脂が固化した
後に分割溝５が下面よりダイシングソーなどで切り込ま
れ、金属基板１を複数の部分に分割する。分割溝５の深
さはは封止樹脂４の厚さの途中で止められ、封止樹脂の
残厚がデバイスの強度を担うので、封止樹脂４には強度
のある材質を用いるのが好ましい。金属基板１の第１部
分１１と第２部分１２の下面は、そのままＳＭＤ用の面
電極として使用される。Reference numeral 4 denotes a sealing resin which is mainly composed of, for example, an epoxy resin and has high transparency with respect to the wavelength of light emitted from the LED.
After being filled around the semiconductor 2 and the bonding wire 3, it is solidified and protects the device. After the resin is solidified, the dividing groove 5 is cut from the lower surface by a dicing saw or the like, and the metal substrate 1 is divided into a plurality of portions. Since the depth of the division groove 5 is stopped in the middle of the thickness of the sealing resin 4 and the remaining thickness of the sealing resin bears the strength of the device, it is preferable to use a strong material for the sealing resin 4. . The lower surfaces of the first portion 11 and the second portion 12 of the metal substrate 1 are directly used as SMD surface electrodes.

【００１８】図１（ｂ）に示す本発明の第２の実施の形
態において、基本的な構成は（ａ）と同様であるが、金
属基板１にあらかじめプレス加工が施されて両縁が下面
から持ち上げられ予備加工部１３を形成している。この
予備加工がなされた後で金属基板１には更にハンダ付け
性を向上させる表面処理（例えばハンダに濡れ性の良い
金属のメッキやフラックスの塗布等）を施しておくこと
もできる。上記第１の実施の形態においては金属基板１
の左右両端面はデバイスの切断分離により金属材料の地
肌が現れる場合があり、材質によっては側面でのハンダ
との濡れ上がりが悪いことがあるが、第２の実施の形態
においてはハンダに接する予備加工部１３は前処理済の
表面を持つのでそのようなおそれはない。In the second embodiment of the present invention shown in FIG. 1 (b), the basic structure is the same as that of FIG. 1 (a), but the metal substrate 1 is pre-pressed so that both edges are lower. To form a pre-processed portion 13. After the preliminary processing, the metal substrate 1 may be subjected to a surface treatment for further improving the solderability (for example, plating of a metal having good wettability to the solder or application of a flux). In the first embodiment, the metal substrate 1
In some cases, the surface of the metal material may appear on the left and right end surfaces of the device due to the cutting and separation of the device, and depending on the material, the wettability with the solder on the side surface may be poor. Since the processing section 13 has a pre-processed surface, there is no such fear.

【００１９】図１（ｃ）に示す本発明の第３の実施の形
態においては、金属基板１には更に高度の立体加工が施
され、ＬＥＤの光反射面１５も予備加工部として形成さ
れている。もちろん金属基板の材質あるいはその表面処
理は光の波長に対する反射特性が考慮される。１４は安
全溝であり、ハーフダイシング溝５の下面からの切り込
みが金属基板１の上面を越えてボンディングワイヤ３を
切断することのないよう、切り込みの底をボンディング
ワイヤ３の入り込めない安全溝１４内に止め得るために
設けた。また１６は絶縁皮膜でこれも金属基板に施した
予備加工部であり、ボンディングワイヤ３と金属基板の
第１部分１１との接触を避けるため基板表面の要所に予
め形成しておいたものである。In the third embodiment of the present invention shown in FIG. 1 (c), the metal substrate 1 is subjected to a more advanced three-dimensional processing, and the light reflecting surface 15 of the LED is also formed as a preliminary processing part. I have. Of course, the material of the metal substrate or its surface treatment takes into account the reflection characteristics with respect to the wavelength of light. Reference numeral 14 denotes a safety groove, and the bottom of the cut is formed so that the cut from the lower surface of the half dicing groove 5 does not exceed the upper surface of the metal substrate 1 and cut the bonding wire 3. It is provided so that it can be stopped inside. Reference numeral 16 denotes an insulating film, which is a pre-processed portion also applied to the metal substrate, which is formed in advance on a key portion of the substrate surface in order to avoid contact between the bonding wire 3 and the first portion 11 of the metal substrate. is there.

【００２０】次に本発明の半導体パッケージデバイスの
製造方法について説明する。図３の各図は本発明の半導
体パッケージの製造方法を説明する途中工程の状態を示
し、（ａ）は半導体実装中の状態の一部平面図、（ｂ）
はその一部側面図、（ｃ）は樹脂封止と分割溝の形成加
工を終わった状態の一部側面図である。Next, a method of manufacturing a semiconductor package device according to the present invention will be described. 3A and 3B show a state of an intermediate step for explaining a method of manufacturing a semiconductor package according to the present invention, wherein FIG. 3A is a partial plan view showing a state during semiconductor mounting, and FIG.
Is a partial side view thereof, and (c) is a partial side view in a state where resin sealing and formation of a dividing groove have been completed.

【００２１】図３（ａ）、（ｂ）において、作業は集合
金属基板１００上で多数個取り方式で行われる。本例は
図１（ｂ）に示す本発明の第２の実施の形態のデバイス
構造を採用している。即ち集合金属基板１００には予備
加工部１３があらかじめ段差のある平行な畝状に設けら
れている。また太い一点鎖線１０１は後工程で加工され
るハーフダイシング溝の位置を示し、太い２点鎖線１０
２は最終的にデバイス毎の分割を行うカットラインの位
置を示す。なおハッチングを施した部分１０３は、カッ
トライン１０２によって最後に分離されるデバイス１個
分の単位デバイス領域を示している。3 (a) and 3 (b), the work is performed on the collective metal substrate 100 in a multi-cavity method. This example employs the device structure of the second embodiment of the present invention shown in FIG. That is, the pre-processed portion 13 is provided in advance on the collective metal substrate 100 in a parallel ridge shape with a step. A thick dashed line 101 indicates the position of a half dicing groove to be processed in a later step, and a thick dashed line 10
Reference numeral 2 denotes a position of a cut line at which division is finally performed for each device. A hatched portion 103 indicates a unit device region for one device which is finally separated by the cut line 102.

【００２２】平面図（ａ）、側面図（ｂ）においては、
集合金属基板１００上の第１部分となるべき領域１１１
に多数の半導体２がダイボンディングされかつ第２部分
となるべき領域１１２とワイヤボンディングされてい
る。平面図上ではダイボンディングは上から２行目左か
ら５列目までなされ、上から３行目左から５列目までは
ダイボンディングのみが行われた状態を示している。こ
れは説明の便宜上の図示方法で、実際にはダイボンディ
ングが全行全列終わってからワイヤボンディングがなさ
れるのは当然である。In the plan view (a) and the side view (b),
Region 111 to be First Part on Collective Metal Substrate 100
A large number of semiconductors 2 are die-bonded and wire-bonded to a region 112 to be a second portion. In the plan view, die bonding is performed in the second row from the top to the fifth column from the left, and only the die bonding is performed in the third row from the top to the fifth column from the left. This is a drawing method for convenience of explanation, and it is natural that the wire bonding is actually performed after the die bonding is completed in all rows and all columns.

【００２３】次いで側面図（ｃ）に示すように液状の封
止樹脂が実装の終わった金属基板上に所定の高さになる
ようポッティングされ、キュアを行って硬化される。そ
の後ダイシングソー（ダイサー）の切り込み深さを適切
に調整してハーフダイシング溝１０１が加工され、金属
基板の第１部分となるべき領域１１１と第２部分となる
べき領域１１２とが分割される。これが図示の状態であ
る。ハーフダイシング溝１０１内には、必要に応じて接
着剤を充填して強度改善を図る。その後縦横のカットラ
イン１０２位置を、パッケージデバイスの総厚より大き
い十分な切り込み深さに改めて設定したダイシングソー
によって切断し、各単位デバイスを分離すると主要な工
程が終了しパッケージが完成する。Next, as shown in a side view (c), a liquid sealing resin is potted to a predetermined height on the mounted metal substrate, cured and cured. Thereafter, the cutting depth of the dicing saw (dicer) is appropriately adjusted to process the half dicing groove 101, and the region 111 to be the first portion and the region 112 to be the second portion of the metal substrate are divided. This is the state shown in the figure. The half dicing groove 101 is filled with an adhesive as needed to improve the strength. Thereafter, the positions of the vertical and horizontal cut lines 102 are cut by a dicing saw that has been newly set to a sufficient cutting depth larger than the total thickness of the package device, and when each unit device is separated, the main process is completed and the package is completed.

【００２４】以上で本発明の実施の形態について述べた
が、本発明の技術的範囲はもちろん既述のものにとどま
らない。本発明の基本構成に伴って付与させたい任意の
特性があれば、それによって細部の構成は異なって来
る。例えば実施の形態に例示した単色のＬＥＤ以外のデ
バイスに対する応用もできる。１個のデバイス内での金
属基板のハーフダイシング溝数を平行、縦横、斜め等に
複数設定しあるいは穴明け加工を併用して金属基板の分
割される領域数を増せば、ワイヤボンディング数も複数
化できて、半導体として多端子の機能素子や集積回路チ
ップも利用可能である。Although the embodiments of the present invention have been described above, the technical scope of the present invention is, of course, not limited to the above. If there are any characteristics desired to be imparted with the basic structure of the present invention, the details of the structure will differ depending on the characteristics. For example, application to devices other than the monochromatic LED exemplified in the embodiment is also possible. If the number of half dicing grooves of the metal substrate in one device is set to be plural, such as parallel, vertical, horizontal, diagonal, etc., or if the number of divided regions of the metal substrate is increased by using drilling, the number of wire bonding will also be Multi-terminal functional elements and integrated circuit chips can also be used as semiconductors.

【００２５】また金属基板の材質の選択、金属基板に与
える成形や表面処理等の予備加工の内容の任意の選択
（例えば狭いハーフダイシング溝を越えてハンダでショ
ートしないように溝の脇にハンダレジスト皮膜を形成し
ておくことなどもデバイスのハンダ付け性の歩留りの向
上処理となる）、封止樹脂の材質、基本的な製造方法に
対する付加的工程の追加（例えば補強加工）等が考えら
れる。Further, selection of the material of the metal substrate and arbitrary selection of the contents of the pre-processing such as forming and surface treatment given to the metal substrate (for example, a solder resist is provided beside the narrow half dicing groove so as not to be short-circuited with the solder so as to avoid short circuit. The formation of a film also serves to improve the yield of the solderability of the device), the addition of additional steps to the material of the sealing resin, the basic manufacturing method (for example, reinforcement), and the like.

【００２６】またハーフダイシング溝加工とデバイス分
離のダイシング溝加工とを混合してカッターの切り込み
を溝の種類毎に交互に変えながら行ってもよいし、ある
いは１本のカッターの主軸に大小の直径の円盤ソーを所
定の間隔で固定し、１度の切削行程で深浅複数の溝を同
時に加工することもできる。なお溝加工法も必ずしも通
常のダイシングソーの使用に限られない。The cutting of the cutter may be alternately performed for each type of groove by mixing the half dicing groove processing and the dicing groove processing for device separation, or the diameter of the main shaft of one cutter may be large or small. And a plurality of deep and shallow grooves can be simultaneously machined in one cutting stroke. The groove processing method is not necessarily limited to the use of a normal dicing saw.

【００２７】[0027]

【発明の効果】本発明においては半導体のパッケージに
おいて金属基板を用いたので次の効果を有する。 （１）金属基板は樹脂製の回路基板よりも一般に安価に
することが容易であるので製品コストを低減し得る。 （２）金属は樹脂よりも熱伝導性が高いため、半導体デ
バイスの放熱性が良好になる。According to the present invention, the following effects are obtained because the metal substrate is used in the semiconductor package. (1) In general, it is easy to make the metal substrate cheaper than the circuit board made of resin, so that the product cost can be reduced. (2) Since the metal has higher thermal conductivity than the resin, the heat dissipation of the semiconductor device is improved.

【００２８】また本発明は更に次の製造上の効果を有す
る。 （３）金属基板の加工は樹脂製基板の加工よりも低コス
ト化が可能である。 （４）ハーフダイシング工程が追加されるが、例えばデ
バイス分離のためのダイシング工程と同じダイサーを使
用し加工プログラムを変更すれば足りるので、設備費あ
るいは工程やコストの実質的な増加なしで実施すること
ができる。Further, the present invention has the following production effects. (3) The cost of processing a metal substrate can be lower than that of processing a resin substrate. (4) Although a half dicing step is added, for example, it is sufficient to use the same dicer as the dicing step for device separation and change the processing program, and therefore, the processing is performed without a substantial increase in equipment costs or steps or costs. be able to.

【００２９】（５）製品品質を向上させる種々の予備加
工が金属材料に対しては容易に実施できる。例えば高反
射率の反射面の形成、要所の絶縁処理、耐食処理、ハン
ダ付け性を向上させる形状設定または表面処理、あるい
は逆にハンダ流れを制限するレジスト膜の形成、その他
である。(5) Various pre-processes for improving product quality can be easily performed on metal materials. For example, formation of a reflective surface having high reflectivity, insulation treatment, corrosion resistance treatment at important points, shape setting or surface treatment for improving solderability, or formation of a resist film for restricting solder flow, etc.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の半導体パッケージの断面図で、（ａ）
はその第１の実施の形態、（ｂ）はその第２の実施の形
態、（ｃ）はその第３の実施の形態を示す。FIG. 1 is a cross-sectional view of a semiconductor package according to the present invention;
Shows the first embodiment, (b) shows the second embodiment, and (c) shows the third embodiment.

【図２】従来の半導体パッケージの断面図で、（ａ）は
第１の従来例、（ｂ）は第２の従来例を示す。2A and 2B are cross-sectional views of a conventional semiconductor package, wherein FIG. 2A shows a first conventional example and FIG. 2B shows a second conventional example.

【図３】本発明の半導体パッケージの製造方法を説明す
る途中工程の状態を示し、（ａ）は半導体実装中の状態
の一部平面図、（ｂ）はその一部側面図、（ｃ）は樹脂
封止と分割溝の形成加工を終わった状態の一部側面図で
ある。3A and 3B show a state of an intermediate step for explaining a method of manufacturing a semiconductor package according to the present invention, wherein FIG. 3A is a partial plan view of a state during semiconductor mounting, FIG. 3B is a partial side view thereof, and FIG. FIG. 4 is a partial side view showing a state after the resin sealing and the forming process of the dividing groove have been completed.

【符号の説明】[Explanation of symbols]

１ 金属基板 １１ 第１部分 １２ 第２部分 １３ 予備加工部 １４ 安全溝 １５ 光反射面 １６ 絶縁皮膜 ２ 半導体 ３ ボンディングワイヤ ４ 封止樹脂 ５ 分割溝 ６ ガラエポ基板 ７ 銅箔 ７１ 第１部分 ７２ 第２部分 ７３ 分割部 ８ 立体樹脂基板 ８１ 斜面 ９ 金属メッキ膜 ９１ 第１部分 ９２ 第２部分 ９３ 分割部 １００ 集合金属基板 １０１ ハーフダイシング溝 １０２ カットライン １０３ 単位デバイス領域 １１１ 第１部分となる領域 １１２ 第２部分となる領域 DESCRIPTION OF SYMBOLS 1 Metal substrate 11 1st part 12 2nd part 13 Preliminary processing part 14 Safety groove 15 Light reflection surface 16 Insulating film 2 Semiconductor 3 Bonding wire 4 Sealing resin 5 Division groove 6 Glass epoxy board 7 Copper foil 71 First part 72 Second Part 73 Divided part 8 Three-dimensional resin substrate 81 Slope 9 Metal plating film 91 First part 92 Second part 93 Divided part 100 Collective metal substrate 101 Half dicing groove 102 Cut line 103 Unit device region 111 First region 112 Second Partial area

Claims (12)

【特許請求の範囲】[Claims] 【請求項１】 金属基板の一部分に半導体がダイボンデ
ィングされ、他の部分と前記半導体の電極がワイヤボン
ディングされ、前記金属基板の両部分が封止樹脂で覆わ
れ、前記金属基板の前記両部分は分割されているが前記
封止樹脂によって相互に連結された構造を有し、かつ前
記金属基板の両部分のそれぞれ少なくとも一部が端子と
なっていることを特徴とする半導体のパッケージ。1. A semiconductor device is die-bonded to a part of a metal substrate, another part and an electrode of the semiconductor are wire-bonded, and both parts of the metal substrate are covered with a sealing resin. Are divided but connected to each other by the sealing resin, and at least a part of each of both parts of the metal substrate is a terminal. 【請求項２】 前記ワイヤボンディングのワイヤは前記
両部分を分割する溝を越えて横断していることを特徴と
する請求項１の半導体のパッケージ。2. The semiconductor package according to claim 1, wherein said wire for wire bonding crosses over a groove dividing said both portions. 【請求項３】 前記金属基板は立体的に変形させる加工
が施されていることを特徴とする請求項１あるいは２の
半導体のパッケージ。3. The semiconductor package according to claim 1, wherein the metal substrate is subjected to a process of three-dimensionally deforming the metal substrate. 【請求項４】 前記金属基板にはハンダ付け性を向上さ
せる表面処理が施されていることを特徴とする請求項１
あるいは２の半導体のパッケージ。4. The metal substrate according to claim 1, wherein a surface treatment for improving solderability is performed.
Or 2 semiconductor packages. 【請求項５】 前記金属基板の表面の一部には絶縁皮膜
が形成されていることを特徴とする請求項１あるいは２
の半導体のパッケージ。5. The method according to claim 1, wherein an insulating film is formed on a part of the surface of the metal substrate.
Semiconductor package. 【請求項６】 集合金属基板上の所定領域に多数の半導
体をダイボンディングする工程と、前記半導体の各々の
電極と前記集合金属基板上の他の所定領域とをそれぞれ
ワイヤボンディングする工程と、前記半導体を封入する
封止樹脂を前記集合金属基板の少なくとも一方の面に充
填しかつ硬化させる工程とを上記の順で含み、その後前
記集合金属基板の各所定領域と各他の所定領域とを前記
封止樹脂を残して分割加工する工程と、前記集合金属基
板および前記封止樹脂をデバイス毎に分離する工程とを
任意の順序であるいは混合して含むことを特徴とする半
導体のパッケージの製造方法。6. A step of die-bonding a large number of semiconductors to a predetermined region on the collective metal substrate, a step of wire bonding each electrode of the semiconductor to another predetermined region on the collective metal substrate, A step of filling and curing at least one surface of the collective metal substrate with a sealing resin for encapsulating a semiconductor in the above order, and thereafter, each predetermined region of the collective metal substrate and each other predetermined region A method of manufacturing a semiconductor package, comprising a step of dividing and processing the assembly metal substrate and the sealing resin for each device in an arbitrary order or in a mixture, while leaving a sealing resin. . 【請求項７】 前記集合金属基板の各所定領域と各他の
所定領域とを前記封止樹脂を残して分割加工する工程
と、前記集合金属基板および前記封止樹脂をデバイス毎
に分離する工程とは、それらの少なくとも一部が交互に
行われることを特徴とする請求項６の半導体のパッケー
ジの製造方法。7. A step of dividing each predetermined region and each other predetermined region of the collective metal substrate while leaving the sealing resin, and a step of separating the collective metal substrate and the sealing resin for each device. 7. The method for manufacturing a semiconductor package according to claim 6, wherein at least a part of the steps is performed alternately. 【請求項８】 前記集合金属基板の各所定領域と各他の
所定領域とを前記封止樹脂を残して分割加工する工程
と、前記集合金属基板および前記封止樹脂をデバイス毎
に分離する工程とは、それらの少なくとも一部が同時に
行われることを特徴とする請求項６の半導体のパッケー
ジの製造方法。8. A step of dividing each predetermined region and each other predetermined region of the collective metal substrate while leaving the sealing resin, and a step of separating the collective metal substrate and the sealing resin for each device. 7. The method of manufacturing a semiconductor package according to claim 6, wherein at least part of the steps is performed simultaneously. 【請求項９】 前記集合金属基板に製品の品質を向上さ
せる予備加工工程を前記ダイボンディング工程以前に有
することを特徴とする請求項６ないし８のいずれかの半
導体のパッケージの製造方法。9. The method of manufacturing a semiconductor package according to claim 6, further comprising a pre-processing step for improving the quality of the product on the collective metal substrate before the die bonding step. 【請求項１０】 前記予備加工工程は前記集合金属基板
を立体的に変形加工する工程であることを特徴とする請
求項９の半導体のパッケージの製造方法。10. The method of manufacturing a semiconductor package according to claim 9, wherein said preliminary processing step is a step of three-dimensionally deforming said collective metal substrate. 【請求項１１】 前記予備加工工程は前記集合金属基板
のハンダ付け性を向上させる表面処理工程であることを
特徴とする請求項９の半導体のパッケージの製造方法。11. The method of manufacturing a semiconductor package according to claim 9, wherein said preliminary processing step is a surface processing step for improving solderability of said collective metal substrate. 【請求項１２】 前記予備加工工程は前記集合金属基板
の一部の表面に絶縁皮膜を形成する工程であることを特
徴とする請求項９の半導体のパッケージの製造方法。12. The method of manufacturing a semiconductor package according to claim 9, wherein said pre-processing step is a step of forming an insulating film on a part of the surface of said collective metal substrate.
JP25612198A 1998-08-27 1998-08-27 Semiconductor package and manufacturing method thereof Expired - Lifetime JP4215306B2 (en)

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