JP2000077542A - Semiconductor device and method of writing into rom thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a new semiconductor having advantages in improved speed of reading, in improved TAT, and in making the device minute and a method of writing to a ROM. SOLUTION: A logic part is constituted on a semiconductor substrate and a wiring part is constituted by a first wiring layer thereon, and a ROM part is constituted by second and third wiring layers thereon. If the second wiring layer 10 is in contact with the third wiring layer at a designated address, a current will pass through the contact and if they are not in contact with each other, a current will not pass, and this enables discrimination of '0' or '1'.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and its ROM writing method, and more particularly, to a mask ROM for writing a program during a manufacturing process.

[0002]

2. Description of the Related Art A conventional semiconductor memory device and its RO will be described below.
The M writing method, in particular, the configuration of a vertically stacked mask ROM that is generally widely used will be described.

FIG. 4 is a schematic partial plan view of a vertically stacked mask ROM using an ion implantation program system, and FIG. 5 is an equivalent circuit diagram of the mask ROM.

The source and drain diffusion layers of the MOS transistor 50 directly serve as the bit lines 51, and the word lines 52 are formed in a direction perpendicular to the bit lines 51. Therefore, the channel direction of the MOS transistor 50 forming each memory cell is aligned with the direction of the bit line 51. Normally, the threshold voltage (hereinafter abbreviated as Vth) of each MOS transistor 50 is set in advance to the enhancement type, and the selected MOS transistor 5
Only Vth of 0 is switched to the depletion type by the ion implantation method for programming. In FIG. 4,
Reference numeral 60 denotes an element isolation insulating film. In FIG. 5, reference numeral 61 denotes a row decoder, and 62 denotes a column decoder.

In order to read data from the memory cells, all the word lines 52 are previously set to the high level, the selected word line 52 is set to the low level, and the selected bit line 51 is set to the high level. I do.

At this time, if Vth of the selected memory cell is the depletion type, the current flowing through the selected bit line 51 remains flowing even if the word line 52 goes low, while if the Vth of the selected memory cell is the enhancement type, the current flows through the selected bit line. The current flowing through 51 is cut off.

Data is read out by the above method.

[0008]

However, in the above-described structure, the P-channel type MOS transistor is formed continuously on the semiconductor substrate, and after the transistor is formed, the ROM is written by implanting boron under the gate electrode. Therefore, as shown in FIG. 6, in order to create a transistor for ROM, a ROM section 72 must be created on the same semiconductor substrate 70 as the logic section 71 on the semiconductor substrate 70, and the chip size is And the ROM section 72.

Further, when producing chips having different ROM capacities, it is necessary to change all the layouts of the LSI and recreate all the mask patterns.

Further, as described above, for ion implantation after the formation of the gate electrode, boron which is easily implanted is used as an ion species. Therefore, the transistor becomes a P-channel type MOS transistor, the driving capability is low, and the reading speed is low. Inferior in terms of aspect.

Further, the TAT (turn around time) for the multilayer wiring process is deteriorated. Furthermore,
In order to improve the TAT, a special high-acceleration ion implantation apparatus and a special process capable of implanting ions from above the upper wiring are required.

In order to further increase the speed, ROM
There has been a problem that the area increases and the chip size also increases.

Accordingly, it is an object of the present invention to provide a novel semiconductor memory device which is advantageous for improving the reading speed, improving the TAT, and miniaturizing, and a ROM writing method thereof.

[0014]

Therefore, according to the present invention, a logic section 2 is formed on a semiconductor substrate 1, a wiring section 3 is formed on a first wiring layer thereon, and second and third wiring layers are formed thereon. Layers 4, 5
In which the ROM section 6 is constituted.
At the designated address, if a contact is connected between the second and third wiring layers 4 and 5, a current flows through the contact, and if the contact is not connected, the current is broken and no current flows. , "1" is determined.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a semiconductor memory device and a ROM writing method thereof according to the present invention will be described below with reference to the drawings.

FIG. 1 is a view for explaining the basic concept of the present invention. A logic section 2 is formed on a semiconductor substrate 1, a wiring section 3 is formed by a first wiring layer thereon, and a logic section 2 is formed thereon. Second
The ROM section 6 is constituted by the third wiring layers 4 and 5. As described above, according to the present invention, by making the logic unit 2 and the ROM unit 6 have a laminated structure, the chip size can be reduced, the TAT used for the multilayer wiring process can be improved, and the mask can be easily changed.

Hereinafter, the structure of the present invention will be described with reference to FIGS. 2 and 3 in which the present invention is applied to, for example, a three-layer structure process.

FIG. 2 is an equivalent circuit diagram of the mask ROM of the present invention, and FIG. 3 is a diagram showing a contact connection state of the ROM section.

In FIG. 2, reference numeral 10 denotes a second wiring layer formed on the semiconductor substrate in parallel in the X direction, and 11 denotes a third wiring layer also formed in parallel in the Y direction. It is configured.

The second wiring layer 10 is connected to a sense amplifier 12 for reading data.
Is connected to a subsequent circuit (not shown).

A power supply MOS transistor 14 is connected to the third wiring layer 11, and a precharge MOS transistor 15 is commonly connected.

As shown in FIG. 2, the second wiring layer 10 and the third wiring layer 11 are arranged in a matrix.
Indicates that the second wiring layer 10 and the third wiring layer 11 are contact-connected, and x indicates that the second wiring layer 10 and the third wiring layer 11 are not contact-connected. (See the diagram showing the contact connection state of the ROM section shown in FIG. 3).

Thus, the precharge MOS
After the transistor 15 is turned on and the charge of each third wiring layer 11 is extracted, the power supply MOS transistor 1
4 is turned on to supply a charge, a current flows through the contact 16 if contact is established between the second and third wiring layers 10 and 11 at the designated address, and if no contact is established, Since the wire is disconnected and no current flows, “0” and “1” can be determined.

As described above, in the present invention, by forming the logic section 2 and the ROM section 6 in a laminated structure, the chip size can be reduced, and even when chips having different ROM capacities are manufactured, the mask pattern can be formed. Need not be recreated.

Further, since the ROM section does not employ a transistor structure, the ROM section has a higher driving capability and a higher reading speed than the conventional transistor structure.

Further, even if the multilayer wiring process is performed, the TAT
Has no effect, and a special high-acceleration ion implantation apparatus and a special process are not required as in the related art.

In this embodiment, the present invention has been applied to the three-layer structure process and the contact connection between the second wiring layer and the third wiring layer has been described. In the present invention, it is only necessary to use two layers of wiring layers including a polysilicon wiring layer. In consideration of TAT, the R wiring is performed by using the final wiring layer and the wiring layer immediately before the final wiring layer.
If the OM configuration is performed, the TAT can be improved.

[0028]

According to the present invention, the writing of the ROM can be performed in two times.
Since “0” and “1” are determined based on whether or not the wiring layers in the hierarchy are connected by a contact, the driving capability is higher than in the conventional transistor structure, and the reading speed can be increased.

Further, if the ROM configuration is performed using the final wiring layer and the wiring layer immediately before the final wiring layer, the TAT can be improved.

Further, by forming the logic portion and the ROM portion in a laminated structure, the chip size can be reduced and the RO
Even when chips having different M capacities are formed, it is not necessary to re-create all mask patterns.

Further, even if the multi-layer wiring process is performed, the TAT
Has no effect, and a special high-acceleration ion implantation apparatus and a special process are not required as in the related art.

[Brief description of the drawings]

FIG. 1 shows a semiconductor memory device according to one embodiment of the present invention and its R
FIG. 3 is a diagram for explaining a basic concept of an OM writing method.

FIG. 2 is an equivalent circuit diagram of the semiconductor memory device according to one embodiment of the present invention;

FIG. 3 is a ROM of the semiconductor memory device according to the embodiment of the present invention;
FIG. 5 is a diagram showing a contact connection state of a part.

FIG. 4 is a schematic partial plan view of a vertically stacked mask ROM according to a conventional ion implantation program method.

FIG. 5 is an equivalent circuit diagram of a vertically stacked mask ROM according to a conventional ion implantation program method.

FIG. 6 is a diagram showing a configuration of a conventional semiconductor memory device.

Claims (2)

[Claims] A logic section is formed on a semiconductor substrate, and a ROM section is formed by contact-connecting a wiring layer of two layers including an upper wiring layer and an uppermost wiring layer formed thereon. Semiconductor storage device. 2. A ROM section is formed by forming a logic section on a semiconductor substrate, and contact-connecting a wiring layer of two layers, that is, an upper wiring layer and an uppermost wiring layer formed thereon, to form a ROM section. In the above, if there is a contact between the wiring layers of the two layers of the upper wiring layer and the uppermost wiring layer, a current flows through the contact, and if there is no contact, the current is disconnected and no current flows. Making a determination ".