JP2000066640A - Liquid crystal drive, and storage medium with program stored thereon - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of elements of a drive circuit and the cost for the test in performing a multiple gradation display by an active matrix type liquid crystal device. SOLUTION: First, second and third voltages are selected by gradation voltage selection circuits 7-10 from a plurality of gradation voltages generated in a gradation voltage generation circuit according to the high order bit of the image data. Time sharing circuits 11, 12 select the first or second voltage following the timing signals TM1-TM3 according to the low order bit of the image data. The selected voltage is applied to a liquid crystal from an operation amplifier 14 or 15 through an output circuit 13. The timing signal is set to be N times the time constant to be determined from an ON resistance value of the liquid crystal and an active element TFT.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a liquid crystal driving device suitable for use in displaying an active matrix type liquid crystal at multi-gradation and a storage medium storing a program.

[0002]

2. Description of the Related Art As a conventional liquid crystal driving device, for example, the authors S. Saito, K. Kitamura NEC Corp., kanagawa, J
apan Publication title Society for Information Display (SID) International symposium digest of technical papers
volume Date of issue 1995 Explanation page / line / drawing p257-p260 The one disclosed in Fig. 1 is known.

FIG. 15 shows a configuration of a liquid crystal driving device described in the above-mentioned document. This circuit is a liquid crystal drive device for 240 output 6-bit digital video data.

In FIG. 15, when a sampling pulse signal is input, video data is shifted by a shift register circuit 21.
6 bits and 3 outputs are sequentially stored in the data register 2
2 is stored. Next, when a latch signal is input, the data stored in the data register 22 is simultaneously transferred to the data latch circuit 23 and held.

According to the transferred video data, one gradation voltage of 64 values of V1 to V64 of the ROM decoder circuit 24 is selected, impedance is converted by an operational amplifier, and a predetermined voltage is applied to the liquid crystal. . The 64-level gray scale voltage can be obtained by dividing the voltage using a resistor of an 8-level gray scale voltage input from the outside. It is generally called the “resistor string method”.

The ROM decoder circuit 24 includes an enhancement transistor and a depletion transistor as described in the above-mentioned document.

[0007]

According to the conventional liquid crystal driving device described above, 6-bit (64 gradations) gray scale display can be realized without any problem. Problem arises.

[0008] The first problem is that the chip size increases in the case of manufacturing a semiconductor integrated circuit. The reason is that, in the resistor string method, as the number of gray scales increases, the number of gray scale selection circuit sections in particular doubles. The 64 grayscale driver requires 64 ROM decoders per output, but the 256 grayscale driver requires 256 quadruple ROM decoders, which increases the element area and chip size. is there.

[0009] The second problem is that the test time increases in the inspection process of the semiconductor integrated circuit. The reason is 6
There are 64 ROM decoders in the 4-gradation driver, and it is necessary to check the operation of all decoders. In the case of 256 gradations, it is necessary to confirm the operation of the 256 decoders.
This is because the test time is naturally quadrupled and the test cost increases.

An object of the present invention is to provide a gradation display of an active matrix liquid crystal such as a TFT liquid crystal.
A liquid crystal drive device that can reduce the number of elements and the element area of an 8-bit digital drive circuit, reduce the chip size of a semiconductor integrated circuit, and reduce the test cost to use an inexpensive semiconductor integrated circuit. And a storage medium storing the program.

[0011]

In order to achieve the above object, in a liquid crystal driving apparatus according to the present invention, a gray scale voltage generating means for generating a plurality of gray scale voltages, and A first selecting means for selecting a first voltage from among voltages generated by the gray scale voltage generating means, and a first voltage among the voltages generated by the gray scale voltage generating means depending on an upper bit of video data Second selection means for selecting the second voltage and third selection means for selecting the first voltage or the second voltage and applying the selected voltage to the liquid crystal in accordance with the lower bits of the video data are provided.

In the storage medium according to the present invention,
A process of generating a plurality of grayscale voltages, a process of selecting a first voltage from among the voltages generated by the grayscale voltage generation process in accordance with upper bits of video data, and a process of generating a plurality of grayscale voltages in accordance with upper bits of video data Selecting a second voltage different from the first voltage among the voltages generated by the grayscale voltage generating process, and selecting the first voltage or the second voltage according to the lower bits of the video data and applying the selected voltage to the liquid crystal. A program for executing the adding process is stored.

Further, in the liquid crystal driving device and the storage medium, the process of applying the selected voltage to the liquid crystal may be executed according to the lower bits of the video data and according to a timing signal input from the outside.

The time for applying the first voltage or the second voltage to the liquid crystal is determined by a time constant determined by the on-resistance of an active element for driving the liquid crystal and the capacitance of the liquid crystal, and time-division controlled by a timing signal. May be.

[0015]

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a configuration of an 8-bit digital input driver as a first embodiment of a liquid crystal driving device according to the present invention.

In FIG. 1, 1 is a shift register circuit,
2 is a buffer circuit for video data D00 to Dxx, 3 is a data register, 4 is a latch circuit, 5 is a timing control circuit, 6 is a gradation voltage generation circuit, 7, 8, 9, and 10 are gradation voltage selection circuits, 11 , 12 is a time division circuit, 13 is an output selection circuit, 14 and 15 are operational amplifiers, and 16 is a timing signal buffer circuit.

SP is a start pulse signal, CLK
Is a clock signal, STB is a latch signal, POL is a polarity signal, VX0 to 9 are gradation power supplies, and TM1 to 3 are timing signals.

The gradation voltage generating circuit 6 has ten gradation power supply voltage values VX0, VX1,.
By dividing the pressure of X9, the positive and negative polarities of 65 are obtained.
A grayscale voltage of × 2 is generated. FIG. 3 shows details of the gradation voltage generation circuit 6.

In FIG. 3, the gray scale voltage generating circuit 6 generates 6 positive and negative voltages, respectively.
It is composed of four voltage dividing resistors + R1 to + R64 and -R1 to -R64, and has 65 × 2 values (+ V0, + V4, + V8,...).
+ V248, +252, +256 and -V0, -V4,
-V8... -V248, -V252, -V256) are generated and output.

The above outputs are sent to 6-bit gradation voltage selection circuits 7, 8, 9, and 10. The gradation voltage selection circuit selects two adjacent voltage values. Gradation voltage selection circuits 7-1
4, 5, 6, and 7 show the detailed configuration of the “0”.

The 64 switches shown in FIGS.
It is composed of a ROM type decoder as shown in FIG. RO
When the M-type decoder outputs a higher voltage than the liquid crystal common voltage, it is composed of Pch enhancement type and depletion type transistors (corresponding to FIGS. 4 and 5).
Conversely, when outputting a lower voltage with respect to the liquid crystal common voltage,
It is composed of Nch enhancement type and depletion type transistors (corresponding to FIGS. 6 and 7).

The output voltages of the gradation selection circuits 7 and 8 are sent to a time division circuit 11, and the outputs of the gradation selection circuits 9 and 10 are sent to a time division circuit 12. The time division circuits 11 and 12 are circuits that select two voltages according to the upper 6 bits of the video data and select one of the voltages according to the timing signals TM1 to TM3 and the lower 2 bits of the video data. FIG.
FIG. 14 shows the configuration of the time division circuit, and FIG. 14 shows a timing chart of the operation.

Next, the operation of the gradation selection circuits 7 to 10 and the time division circuits 11 and 12 will be described with reference to the timing chart of FIG. As shown in the timing chart of FIG.
When the video data is 11111110 (top 11111
1, lower 10), the upper voltage of the positive polarity in the gradation selection circuit 7+
V256 is selected, and the gradation selection circuit 8 selects the lower voltage + V25.
Select 2.

Further, the two voltages are changed from + V256 to + V252 at four timings by the lower two bits of the video data and the time division circuit 11. Lower 11
In the case of, the selection of + V256 is continuously performed.
Select 252. Similarly, when the lower order is 01, T
+ V2 during the H period of the M2 signal (hereinafter abbreviated as TM2 (H))
52, and if the lower order is 00, + V252 is selected in the H period of the TM3 signal (hereinafter abbreviated as TM3 (H)).
The operation of the time division circuit 12 is performed in the same manner as described above.

The voltage selected by the time division circuit 11 or 12 is supplied to the operational amplifiers 14 and 15 through the output selection circuit 13.
And is applied to the source electrode of the TFT liquid crystal.

Next, "H" of the timing signals TM1 to TM3 is set.
How to set the period will be described. FIG. 11 shows an equivalent circuit diagram of the TFT liquid crystal. FIG. 12 shows an equivalent circuit when the TFT is on. Ron is an on-resistance when the H signal is input to the gate driver and the TFT is turned on. Cc is the total value of the capacitance of the liquid crystal itself and the capacitance such as the auxiliary capacitance.

TM1 (H) is a time constant τ = R determined by the ON resistance Ron of the TFT of the liquid crystal panel and the liquid crystal capacitance Cc.
0.288 times on × Cc, that is, TM1 (H) = 0.
It is set to be 288τ. This corresponds to the time to reach about 25% of the difference between the two voltages. Similarly, TM
When 2 (H) = 0.693τ, 50% of the voltage difference, TM3
When (H) = 1.386τ, TM1 to TM3 are set so as to be 0.75% of the voltage difference.

In FIG. 2, the video data is 111111
In the case of 10, since the lower data is 10, the liquid crystal (point a in FIG. 12) has +255 gradation voltage = + V256−0.25 ×
The voltage of {(+ V256) − (+ V252)} is held. Video data is 11111101 (lower data is 0
In the case of 1), +254 gradation voltage = + V256-0.5
× {(+ V256) − (+ V252)}, and +25 when the video data is 11111100 (lower-order data 00)
3 gradation voltages = + V256−0.75 × ｛(+ V256)
− (+ V252)} voltage is held. When the video data is 11111111 (lower data 11), that is, +
In the case of selecting the 256 gradation voltage, the output of + V256 may be continued as it is.

As described above, the liquid crystal is discharged or charged minutely after reaching a certain voltage value by the lower 2 bits of the video data and the timing signals TM1 to TM3. Can be held at a divided voltage value.

The combination of the upper and lower bits may be the upper 5 bits and the lower 3 bits.
8 can be controlled in the same manner.

FIG. 9 shows a 7-bit digital input driver according to a second embodiment of the present invention. Here, an example of upper 6 bits and lower 1 bit is shown. Note that FIG.
In the figure, the same reference numerals are given to parts corresponding to those in FIG.

In FIG. 9, when the lower data is 1, the initial voltage is continuously selected. When the lower data is 0, TM1 is selected.
By setting (H) = 0.5τ, the liquid crystal can hold an intermediate voltage between the two voltage differences. Also in this case, the combination of the upper and lower bits may be the upper 5 bits and the lower 2 bits, and the timing signals can be similarly controlled by three TM1 to TM3.

According to the liquid crystal driving device according to each of the above-described embodiments, first, two voltages (the first voltage and the second voltage) from a plurality of grayscale voltages are set in accordance with the upper bits of the digital video data.
Voltage) is selected. Furthermore, according to the timing signal input from the outside according to the lower bits of the video data,
Two voltages are applied to the liquid crystal in a time sharing manner. At this time, the timing signal is set to be N times the time constant determined by the on-resistance values of the liquid crystal and the active element such as the TFT.

First, the first voltage is applied to the liquid crystal source line for a sufficiently long time to set the liquid crystal main body to the first voltage. next,
Fine adjustment of the voltage is performed with the second voltage. The charge and discharge of the charge accumulated in the liquid crystal are minutely performed by the application time of the second voltage. Second
If the voltage is applied for a long time, the voltage will be stabilized at the second voltage.
The timing time is externally controlled so as to be a voltage between the first voltage and the second voltage.

Therefore, according to each embodiment, the number of elements can be reduced. That is, in the 8-bit resistor string method, the number of elements of the ROM decoder unit is 2 per output.
The number of elements of the ROM decoder unit controlled by the upper 6 bits is (2 × 6 × 64) by setting the upper 6 bits to the resistor string system and the lower 2 bits to the time division system for × 8 × 256 = 4096. × 2 = 1536, and the number of elements of 2560 can be reduced. The number of elements of the time division circuits 11 and 12 controlled by the lower two bits is at least 52 and a total of 2
The number is 612 and the number of 1484 elements can be reduced.

In the upper 5 bits and lower 3 bits, the upper 5 bits
The number of elements of the ROM decoder section controlled by bits is (2 ×
5 × 32) × 2 = 640, and the number of elements of the time division circuits 11 and 12 controlled by the lower 3 bits is at least 100, which is a total of 740, and the number of elements of 3356 can be reduced. Thus, the number of elements can be significantly reduced, and the chip size can be reduced.

Further, according to each embodiment, the test cost can be reduced. That is, 256 ROs for 8 bits
Since it is necessary to confirm the operation of the M decoder, it is necessary to perform a function test 256 times. 64 ROMs in upper 6 bits in resistor string system and lower 2 bits in time division system
Since the operation of the decoder only needs to be confirmed, a function test is performed 64 times. Since the confirmation of the time division method of the lower 2 bits only needs to be performed four times, the function test may be performed at least 68 times. If the upper 5 bits are of a resistor string type and the lower 3 bits are of a time-division type, 32 + 8 = 40 functional tests may be performed. Thus, the number of tests can be drastically reduced, and the test cost can be greatly reduced.

When the configuration shown in FIGS. 1 and 9 is realized by a computer system including a CPU, a memory, and the like, the memory constitutes a storage medium according to the present invention. The storage medium stores a program for executing the above-described processing. As the storage medium, a semiconductor memory, an optical disk, a magneto-optical disk, a magnetic medium, or the like can be used.

[0039]

As described above, according to the present invention,
2 from a plurality of gray scale voltages according to the upper bit of video data
Since one voltage is selected and one voltage is further selected from the two voltages according to the lower bit of the video data and applied to the liquid crystal, the number of elements and the test cost can be reduced. it can.

Further, by applying two voltages to the liquid crystal in a time-division manner in accordance with a timing signal, the charge and discharge of the liquid crystal are adjusted, and a value obtained by dividing the two voltage values is held in the liquid crystal. Can be.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an 8-bit digital driver according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of FIG.

FIG. 3 is a detailed configuration diagram of a grayscale voltage generation circuit.

FIG. 4 is a detailed configuration diagram of a gradation voltage selection circuit.

FIG. 5 is a detailed configuration diagram of a gradation voltage selection circuit.

FIG. 6 is a detailed configuration diagram of a gradation voltage selection circuit.

FIG. 7 is a detailed configuration diagram of a gradation voltage selection circuit.

FIG. 8 is a configuration diagram of a ROM decoder.

FIG. 9 is a circuit diagram illustrating a 7-bit digital driver according to a second embodiment of the present invention.

FIG. 10 is a timing chart showing the operation of FIG.

FIG. 11 is a configuration diagram of a TFT liquid crystal.

FIG. 12 is an equivalent circuit when a TFT is turned on.

FIG. 13 is a detailed configuration diagram of a time division circuit.

FIG. 14 is a timing chart showing the operation of the time division circuit.

FIG. 15 is a circuit diagram showing a conventional 6-bit digital liquid crystal driving device.

[Explanation of symbols]

 Reference Signs List 2 video data buffer circuit 6 gradation voltage generation circuit 7-10 gradation voltage selection circuit 11, 12 time division circuit 13 output selection circuit 16 timing signal buffer circuit D00-Dxx video data VX0-9 gradation power supply TM1-3 timing signal + V0,4,8 ... 256 Internal gradation voltage (positive polarity) -V0,4,8 ... 256 Internal gradation voltage (negative polarity) + R1-64, -R1-64 Resistance Ron TFT on resistance Cc Liquid crystal capacitance

Continued on the front page F-term (reference) 2H093 NC16 NC22 NC26 NC34 ND06 ND34 ND54 ND60 5C006 AA15 AA16 AA17 AC11 AC21 AF45 AF83 BB16 BC12 BC14 BF24 BF43 FA56 5C080 AA10 BB05 DD22 DD27 EE29 FF03 FF11 GG03 JJ03 02

Claims (6)

[Claims] 1. A grayscale voltage generating means for generating a plurality of grayscale voltages, and a first selection for selecting a first voltage from the voltages generated by the grayscale voltage generating means according to upper bits of video data Means, a second selecting means for selecting a second voltage different from the first voltage among voltages generated by the gradation voltage generating means in accordance with an upper bit of the video data, and a lower bit of the video data And a third selecting means for selecting the first voltage or the second voltage and applying the selected voltage to the liquid crystal in accordance with the following. 2. The liquid crystal driving device according to claim 1, wherein said third selecting means is controlled in accordance with lower bits of said video data and in accordance with a timing signal inputted from outside. 3. A time for applying the first voltage or the second voltage to the liquid crystal is determined by a time constant determined by an on-resistance of an active element for driving the liquid crystal and a capacitance of the liquid crystal, and the time constant is determined by the timing signal. 3. The liquid crystal driving device according to claim 2, wherein the one voltage and the second voltage are applied by time division control. 4. A process for generating a plurality of gray scale voltages, a process for selecting a first voltage among the generated voltages according to upper bits of video data, and a process for selecting higher voltages of the video data. Selecting a second voltage different from the first voltage among the generated voltages; and selecting the first voltage or the second voltage and applying the selected voltage to the liquid crystal according to lower bits of the video data. A storage medium storing a program for executing the processing. 5. The program according to claim 4, wherein the process of applying the selected voltage to the liquid crystal is executed in accordance with lower bits of the video data and in accordance with a timing signal input from the outside. A storage medium that stores the information. 6. A time for applying the first voltage or the second voltage to the liquid crystal is determined by a time constant determined by an on-resistance of an active element for driving the liquid crystal and a capacitance of the liquid crystal, and the time constant is determined by the timing signal. 6. The storage medium according to claim 5, wherein the one voltage and the second voltage are applied by time division control.