JP2000058719A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JP2000058719A
JP2000058719A JP10219218A JP21921898A JP2000058719A JP 2000058719 A JP2000058719 A JP 2000058719A JP 10219218 A JP10219218 A JP 10219218A JP 21921898 A JP21921898 A JP 21921898A JP 2000058719 A JP2000058719 A JP 2000058719A
Authority
JP
Japan
Prior art keywords
semiconductor chip
reinforcing member
sealing resin
semiconductor device
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10219218A
Other languages
Japanese (ja)
Inventor
Kazuya Ota
和也 太田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP10219218A priority Critical patent/JP2000058719A/en
Publication of JP2000058719A publication Critical patent/JP2000058719A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device and the device which can prevent the warping of a semiconductor chip resulting from the difference between the coefficients of thermal expansion of an intermediate and a sealing resin, by obtaining electrical connection reliability and a mechanical strength at the time of electrically connecting the semiconductor chip to a wiring board. SOLUTION: A semiconductor device is provided with a semiconductor chip 2 having an integrated circuit, a wiring board 20 having electrical wiring, an intermediate 1 which is arranged between the board 20 and the chip 2 and electrically connects the chip 2 to the board 20 when the chip 2 is mounted on and electrically connected to the board 20, and a sealing member 80 which protects the wiring portion of the chip 2.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、集積回路を有する
半導体チップを備えた半導体装置と半導体装置の製造方
法に関するものである。
[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having a semiconductor chip having an integrated circuit and a method of manufacturing the semiconductor device.

【0002】[0002]

【従来の技術】現在、多端子半導体パッケージはパッケ
ージの4側面から出・入力端子を引き出したQFP(Q
uad Flat Package)が主流である。近
年、電子機器の高性能化の要求から、LSI(大規模集
積回路)等の半導体チップの端子数は増大し、QFPは
巨大化せざるを得なくなっている。しかし同時に、電子
機器の軽薄短小化の要求もあり、QFPではその矛盾す
る要求に応えられなくなってきている。そこで多端子化
する半導体チップを高密度に実装し軽薄短小化を実現す
るために、従来のパッケージ技術に代って、半導体チッ
プをそのサイズとほぼ同等の大きさにしたパッケージ技
術であるCSP(Chip Size Packag
e)が採用され始めている。なかでもワイヤーボンディ
ング(Wire Bonding:WB)タイプのCS
Pは、従来のパッケージ技術を継承したままCSPが実
現できる方法で、比較的安価である。しかし、この方式
ではワイヤーがむき出しになっており、それを保護する
ために封止樹脂で全体を覆う必要がある。同時に、CS
Pは半導体チップと同サイズのパッケージを目指すた
め、インターポーザ(半導体チップとマザーボードの中
間物)の厚みはできる限り薄くしたいという要求があ
る。
2. Description of the Related Art Currently, a multi-terminal semiconductor package has a QFP (Q
uad Flat Package) is the mainstream. In recent years, the number of terminals of a semiconductor chip such as an LSI (Large Scale Integrated Circuit) has increased due to a demand for higher performance of electronic devices, and the QFP has to be enlarged. However, at the same time, there is a demand for lighter, thinner and smaller electronic devices, and QFPs cannot meet the contradictory demands. Therefore, in order to realize high-density mounting of a semiconductor chip with a large number of terminals and to realize light-weight and small size, instead of the conventional packaging technology, a CSP (packaging technology) in which the semiconductor chip is almost the same size as the semiconductor chip is used. Chip Size Packag
e) has begun to be adopted. Among them, wire bonding (WB) type CS
P is a method that can realize a CSP while inheriting the conventional packaging technology, and is relatively inexpensive. However, in this method, the wire is exposed, and it is necessary to cover the entire wire with a sealing resin in order to protect the wire. At the same time, CS
Since P aims at a package of the same size as the semiconductor chip, there is a demand that the thickness of the interposer (an intermediate between the semiconductor chip and the motherboard) be as small as possible.

【0003】図7は、従来の半導体装置の一例を示して
おり、配線基板1000に対してWBタイプのCSP1
002を電気的に接続する場合に、インターポーザ10
01を用いている。WBタイプのCSP1002のAu
ワイヤー1005は、配線電極1004に電気的に接続
されている。このAuワイヤー1005は、配線電極1
004とチップ電極1003を電気的に接続している。
このような場合に、半導体チップ1002のAuワイヤ
ー1005を保護するために、封止樹脂1008を用い
る。
FIG. 7 shows an example of a conventional semiconductor device, in which a WB type CSP 1 is mounted on a wiring board 1000.
002 is electrically connected to the interposer 10
01 is used. Au of WB type CSP1002
The wire 1005 is electrically connected to the wiring electrode 1004. The Au wire 1005 is connected to the wiring electrode 1
004 and the chip electrode 1003 are electrically connected.
In such a case, a sealing resin 1008 is used to protect the Au wires 1005 of the semiconductor chip 1002.

【0004】[0004]

【発明が解決しようとする課題】しかし、このようなW
BタイプのCSP1002がマザーボードのような配線
基板1000に対して搭載される際には、リフローはん
だ付け等の加熱工程において、全体を覆っている封止樹
脂1008と、薄くしたインターポーザ(中間物)10
01の間の熱膨張係数の差により、インターポーザ10
01に反りによる応力が発生する。インターポーザ10
01はガラスエポキシ基材等で作られており、インター
ポーザ1001のヤング率が低いと、CSP1002に
も反りが生じてしまい、はんだ接合部分の接触不良を起
こしてしまう。そこで本発明は上記課題を解消し、CS
Pを配線基板に対して電気的に接続する際に、電気的な
接続信頼性と機械的な強度を得て、中間物と封止樹脂間
の熱膨張係数差によるCSPの反りを防ぐことができる
半導体装置と半導体装置の製造方法を提供することを目
的としている。
However, such a W
When the B-type CSP 1002 is mounted on a wiring board 1000 such as a motherboard, in a heating step such as reflow soldering, the sealing resin 1008 covering the whole and the thin interposer (intermediate) 10
01, the interposer 10
01 generates a stress due to warpage. Interposer 10
Numeral 01 is made of a glass epoxy base material or the like, and if the Young's modulus of the interposer 1001 is low, the CSP 1002 will also be warped, resulting in poor contact at the solder joint. Therefore, the present invention solves the above-mentioned problems, and
When electrically connecting P to a wiring board, it is possible to obtain electrical connection reliability and mechanical strength to prevent the CSP from warping due to the difference in thermal expansion coefficient between the intermediate and the sealing resin. It is an object of the present invention to provide a semiconductor device that can be manufactured and a method for manufacturing the semiconductor device.

【0005】[0005]

【課題を解決するための手段】上記目的は、本発明にあ
っては、集積回路を有する半導体チップと、電気的配線
を有する配線基板と、半導体チップを配線基板に実装し
て電気的に接続する際に、配線基板と半導体チップの間
に配置されて配線基板と半導体チップを電気的に接続す
る中間物であって、機械的強度を確保するための補強部
材を有する中間物と、半導体チップの配線部分を保護す
るための封止部材と、を備えることを特徴とする半導体
装置により、達成される。
According to the present invention, there is provided a semiconductor chip having an integrated circuit, a wiring board having electrical wiring, and a semiconductor chip mounted on the wiring board to be electrically connected. An intermediate that is disposed between the wiring substrate and the semiconductor chip and electrically connects the wiring substrate and the semiconductor chip, the intermediate having a reinforcing member for ensuring mechanical strength; and And a sealing member for protecting the wiring portion.

【0006】本発明では、半導体チップは集積回路を有
している。配線基板は電気的な配線を有している。半導
体チップを配線基板に実装して電気的に接続する際に、
配線基板と半導体チップの間には中間物が配される。こ
の中間物は、配線基板と半導体チップを電気的に接続す
るものであって、機械的強度を確保するために補強部材
を有している。これにより、中間物と封止部材の熱膨張
率の差による中間物の反りを防ぐことができる。従っ
て、CSPのようなパッケージの反りを防ぐことができ
るとともに、CSPと配線基板間の電気的な接続信頼性
と機械的な強度を得ることができる。
In the present invention, the semiconductor chip has an integrated circuit. The wiring board has electric wiring. When a semiconductor chip is mounted on a wiring board and electrically connected,
An intermediate is provided between the wiring board and the semiconductor chip. This intermediate electrically connects the wiring board and the semiconductor chip, and has a reinforcing member to secure mechanical strength. This can prevent the intermediate from warping due to the difference in thermal expansion coefficient between the intermediate and the sealing member. Accordingly, it is possible to prevent the package from being warped, such as the CSP, and to obtain the electrical connection reliability and the mechanical strength between the CSP and the wiring board.

【0007】本発明において、好ましくは中間物の補強
部材は封止樹脂を成形する際の成形型である。これによ
り、中間物の補強部材が封止樹脂を形成する際の成形型
として用いることができるので、供給する封止樹脂の量
の制御や封止樹脂の形を確実に設定することができる。
封止樹脂の使用量の適正化を図ることができる。
In the present invention, preferably, the intermediate reinforcing member is a mold for molding the sealing resin. Accordingly, the intermediate reinforcing member can be used as a molding die when forming the sealing resin, so that the amount of the sealing resin to be supplied can be controlled and the shape of the sealing resin can be reliably set.
The use amount of the sealing resin can be optimized.

【0008】本発明において、好ましくは中間物の補強
部材は封止樹脂を成形する際の成形型であり、補強部材
は金属部材である。
In the present invention, the intermediate reinforcing member is preferably a mold for molding the sealing resin, and the reinforcing member is a metal member.

【0009】本発明において、好ましくは中間物の補強
部材は、中間物の一方の表面に設けられている。
In the present invention, preferably, the intermediate reinforcing member is provided on one surface of the intermediate.

【0010】本発明において、好ましくは中間物の補強
部材は、中間物の一方の表面の四隅部分に設けられてい
る。これにより、封止樹脂は中間物の一方の面の四隅部
分に配置されている補強部材により封止樹脂の量を制御
することができその形も所定の形に設定することができ
る。
In the present invention, preferably, the intermediate reinforcing members are provided at four corners of one surface of the intermediate. Thus, the amount of the sealing resin can be controlled by the reinforcing members arranged at the four corners of one surface of the intermediate, and the shape can be set to a predetermined shape.

【0011】本発明において、好ましくは中間物の補強
部材は、中間物の一方の表面の四隅部分に接着剤又は固
定具を用いて設けられている。
In the present invention, the intermediate reinforcing member is preferably provided at one of four corners of one surface of the intermediate using an adhesive or a fixing tool.

【0012】本発明において、好ましくは中間物の補強
部材は、中間物の内部に形成されている。
In the present invention, the intermediate reinforcing member is preferably formed inside the intermediate.

【0013】上記目的は、本発明にあっては、集積回路
を有する半導体チップを、電気的配線を有する配線基板
に対して実装して電気的に接続する際に、配線基板と半
導体チップの間に中間物を配置して配線基板と半導体チ
ップを電気的に接続する際に、中間物としては機械的強
度を確保するために補強部材を有するものを採用し、配
線部分を保護するために封止樹脂を形成する際に、補強
部材を成形型として用いて封止樹脂を成形することを特
徴とする半導体装置の製造方法により、達成される。
According to the present invention, when a semiconductor chip having an integrated circuit is mounted and electrically connected to a wiring board having electric wiring, the present invention provides When electrically connecting the wiring board and the semiconductor chip by arranging an intermediate material, a material having a reinforcing member is used as the intermediate material to secure mechanical strength, and a seal is used to protect the wiring part. This is achieved by a method of manufacturing a semiconductor device, wherein a sealing resin is molded using a reinforcing member as a molding die when forming a sealing resin.

【0014】本発明では、中間物と封止部材の熱膨張率
の差による中間物の反りを防ぐことができる。従って、
半導体チップの反りを防ぐことができるとともに、半導
体チップと配線基板間の電気的な接続信頼性と機械的な
強度を得ることができる。しかも、封止樹脂は補強部材
により確実に成形でき、封止樹脂の量も制御でき、封止
樹脂の使用量の適正化が図れる。
According to the present invention, it is possible to prevent the intermediate from warping due to the difference in the coefficient of thermal expansion between the intermediate and the sealing member. Therefore,
The warpage of the semiconductor chip can be prevented, and the electrical connection reliability and the mechanical strength between the semiconductor chip and the wiring board can be obtained. Moreover, the sealing resin can be reliably molded by the reinforcing member, the amount of the sealing resin can be controlled, and the amount of the sealing resin used can be optimized.

【0015】[0015]

【発明の実施の形態】以下、本発明の好適な実施の形態
を添付図面に基づいて詳細に説明する。なお、以下に述
べる実施の形態は、本発明の好適な具体例であるから、
技術的に好ましい種々の限定が付されているが、本発明
の範囲は、以下の説明において特に本発明を限定する旨
の記載がない限り、これらの形態に限られるものではな
い。
Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. Note that the embodiments described below are preferred specific examples of the present invention,
Although various technically preferable limits are given, the scope of the present invention is not limited to these modes unless otherwise specified in the following description.

【0016】図1と図2は、本発明の半導体装置の好ま
しい実施の形態を示している。この半導体装置10は、
いわゆるワイヤーボンディング(Wire Bondi
ng:WB)タイプのCSP(Chip Size P
ackage)のものである。半導体装置10は、概略
的には、マザーボードのような配線基板20、インター
ポーザ(中間物)1、補強部材6、半導体チップ2、封
止樹脂8等を有している。半導体チップ2は、集積回路
を有する半導体チップであり、たとえば上述したような
WBタイプのCSPである。半導体チップ2のチップ電
極3と、インターポーザ1の配線電極4の間には、たと
えばAu等で作られたワイヤー5が電気的に接続されて
いる。半導体チップ2は、インターポーザ1に対してた
とえば接着剤2Aにより接着して固定される。インター
ポーザ1は、絶縁材料、たとえばガラスエポキシ樹脂等
により作られたものであり、図1と図2の例では断面形
状が長方形状でかつ平面形状が長方形状または正方形状
のものである。
FIGS. 1 and 2 show a preferred embodiment of a semiconductor device according to the present invention. This semiconductor device 10
So-called wire bonding (Wire Bondi)
ng: WB (Type) CSP (Chip Size P)
package). The semiconductor device 10 roughly includes a wiring board 20 such as a motherboard, an interposer (intermediate) 1, a reinforcing member 6, a semiconductor chip 2, a sealing resin 8, and the like. The semiconductor chip 2 is a semiconductor chip having an integrated circuit, and is, for example, a WB-type CSP as described above. A wire 5 made of, for example, Au is electrically connected between the chip electrode 3 of the semiconductor chip 2 and the wiring electrode 4 of the interposer 1. The semiconductor chip 2 is fixed to the interposer 1 by bonding with, for example, an adhesive 2A. The interposer 1 is made of an insulating material, for example, a glass epoxy resin or the like, and has a rectangular cross section and a rectangular or square planar shape in the examples of FIGS.

【0017】インターポーザ1の一方の面1Aには、補
強部材6が接着剤7を介して固定されている。この補強
部材6は、たとえば機械的強度の優れた、金属あるいは
その他の材料で作られている。補強部材6を金属で作る
場合には、たとえばヤング率の大きな銅(Cu)やアル
ミニウム(Al)等の金属を採用することができる。図
1と図2の例では、補強部材6は正方形状でかつ枠状に
形成されている。従って補強部材6は、インターポーザ
1の一方の面の四隅付近に、強力な接着剤7により接着
されている。この強力な接着剤としては、たとえばポリ
クロロプレン等を採用することができる。補強部材6
は、あらかじめ金型あるいはメッキ等で作成した金属板
を採用することができる。
A reinforcing member 6 is fixed to one surface 1A of the interposer 1 with an adhesive 7 interposed therebetween. The reinforcing member 6 is made of, for example, metal or other material having excellent mechanical strength. When the reinforcing member 6 is made of a metal, for example, a metal such as copper (Cu) or aluminum (Al) having a large Young's modulus can be used. 1 and 2, the reinforcing member 6 is formed in a square shape and a frame shape. Therefore, the reinforcing member 6 is adhered to the vicinity of four corners on one surface of the interposer 1 by a strong adhesive 7. As the strong adhesive, for example, polychloroprene or the like can be adopted. Reinforcing member 6
Can adopt a metal plate prepared in advance by a mold or plating.

【0018】図3では、インターポーザ1の一方の面1
Aに対して枠型の補強部材6が接着剤7を介して固定さ
れている。このようにインターポーザ1の一方の面に補
強部材6を形成した後に、インターポーザ1の一方の面
1Aには、半導体チップ2が搭載されて、この半導体チ
ップ2のチップ電極(たとえばAl電極)3と、インタ
ーポーザ1の配線電極4がワイヤーボンディング法によ
りワイヤー5を用いて電気的に接続される。この配線電
極4は、たとえばCuの配線電極を用いることができ
る。
In FIG. 3, one surface 1 of the interposer 1 is shown.
A frame-shaped reinforcing member 6 is fixed to A through an adhesive 7. After the reinforcing member 6 is formed on one surface of the interposer 1 in this manner, the semiconductor chip 2 is mounted on one surface 1A of the interposer 1, and a chip electrode (for example, an Al electrode) 3 of the semiconductor chip 2 is formed. The wiring electrodes 4 of the interposer 1 are electrically connected using wires 5 by a wire bonding method. As the wiring electrode 4, for example, a Cu wiring electrode can be used.

【0019】その後、このままではむき出しになってい
る半導体チップ2及びその半導体チップ2のワイヤー5
は、封止樹脂8により封止することで外部から保護する
ようにしている。すなわち、図4に示すように、封止樹
脂供給手段30から封止樹脂が補強部材6とインターポ
ーザ1の一方の面1Aに形成される空間の中に供給され
る。この封止樹脂8としては、たとえば無溶剤型の液状
エポキシ封止材を採用することができる。
Thereafter, the semiconductor chip 2 which is exposed as it is and the wires 5 of the semiconductor chip 2 are exposed.
Is protected from the outside by being sealed with a sealing resin 8. That is, as shown in FIG. 4, the sealing resin is supplied from the sealing resin supply means 30 into the space formed on the reinforcing member 6 and one surface 1A of the interposer 1. As the sealing resin 8, for example, a solventless liquid epoxy sealing material can be used.

【0020】このようにして供給された封止樹脂8は、
リフロー炉等高温下に置かれた場合に広がる恐れがあ
る。さらに広がった封止樹脂8がリフロー時にインター
ポーザ1に反り応力を加えて、半導体チップ2の反りを
生み、先に述べたようなはんだ不良を起こす恐れがあ
る。そこで、本発明の実施の形態においては、この対策
のために次のような工夫をしている。すなわち、補強部
材6が、封止樹脂8を供給して成形する際の成形型とし
て機能していることである。従って補強部材6の大きさ
は、半導体チップ2及びワイヤー5と配線電極4を含む
領域よりも大きい容積で囲んでいる必要がある。このよ
うにすることで、成形された封止樹脂8が、半導体チッ
プ2、チップ電極3、ワイヤー5、配線電極4を確実に
覆うことができ、特にワイヤー5の保護を達成すること
ができる。このように補強部材6を、封止樹脂の成形時
のダムとしての役割を果たすことで、封止樹脂8を供給
する際の樹脂供給工程の生産性を上げることができ、高
温時の封止樹脂の流れ出しを防止しながら、封止樹脂8
により半導体チップ2やワイヤー5等を封じ込めること
ができる。
The sealing resin 8 thus supplied is:
It may spread when placed in high temperature such as a reflow furnace. Further, the expanded sealing resin 8 applies a warping stress to the interposer 1 at the time of reflow, causing a warpage of the semiconductor chip 2 and possibly causing a solder defect as described above. Therefore, in the embodiment of the present invention, the following measures are taken for this measure. That is, the reinforcing member 6 functions as a molding die when supplying and molding the sealing resin 8. Therefore, the size of the reinforcing member 6 needs to be surrounded by a larger volume than the area including the semiconductor chip 2 and the wires 5 and the wiring electrodes 4. By doing so, the molded sealing resin 8 can surely cover the semiconductor chip 2, the chip electrode 3, the wire 5, and the wiring electrode 4, and particularly, the protection of the wire 5 can be achieved. As described above, the reinforcing member 6 functions as a dam at the time of molding the sealing resin, so that the productivity of the resin supply step when supplying the sealing resin 8 can be increased, and the sealing at a high temperature can be performed. The sealing resin 8 is prevented while preventing the resin from flowing out.
Accordingly, the semiconductor chip 2, the wire 5, and the like can be sealed.

【0021】次に、補強部材6の別の実施の形態につい
て図5と図6を参照して説明する。図5の本発明の別の
実施の形態においては、補強部材6が、たとえばねじ9
のような固定手段により機械的にインターポーザ1の一
方の面1Aに対して固定することができる。図5(B)
に示すようにこのようなねじ(固定手段)9は、たとえ
ば基板1の四隅に配置することができる。図6の実施の
形態では、インターポーザ1を形成する場合に、たとえ
ばリソグラフィ法や切削機械等を用いて、除去部分1E
を除去することにより、結果として補強部材6を形成す
ることができる。このようにすれば、固定手段や接着剤
を用いることなく形成することができる。
Next, another embodiment of the reinforcing member 6 will be described with reference to FIGS. In another embodiment of the invention according to FIG.
The interposer 1 can be mechanically fixed to one surface 1A of the interposer 1 by such fixing means. FIG. 5 (B)
As shown in (1), such screws (fixing means) 9 can be arranged at four corners of the substrate 1, for example. In the embodiment shown in FIG. 6, when forming the interposer 1, the removed portion 1E is formed by using, for example, a lithography method or a cutting machine.
As a result, the reinforcing member 6 can be formed. According to this configuration, it can be formed without using fixing means or an adhesive.

【0022】上述した本発明の実施の形態においては、
次のようなメリットがある。 (1)インターポーザ1の補強部材6が封止樹脂8の量
を制御し、コストダウンが図れる。 (2)封止樹脂8の領域を中心部に制御することで、半
導体チップ2の周辺部分の封止樹脂8をなくすことがで
き、CSPをマザーボードに搭載し、リフローする際の
反り抑制に効果的に働く。 (3)封止樹脂8の流し込みのプロセスを簡略化でき、
半導体装置の生産性を向上させることができる。 (4)あらかじめ施したインターポーザ上の金属板によ
り、封止樹脂8を入れる領域を制御でき、成形効果が得
られ、規格化されたCSPを作るのが容易になる。 などの効果が得られる。
In the embodiment of the present invention described above,
There are the following merits. (1) The reinforcing member 6 of the interposer 1 controls the amount of the sealing resin 8, and the cost can be reduced. (2) By controlling the region of the sealing resin 8 at the center, the sealing resin 8 in the peripheral portion of the semiconductor chip 2 can be eliminated, and the CSP is mounted on the motherboard, which is effective in suppressing warpage during reflow. Work. (3) The process of pouring the sealing resin 8 can be simplified,
The productivity of the semiconductor device can be improved. (4) The area in which the sealing resin 8 is to be placed can be controlled by the metal plate on the interposer that has been applied in advance, a molding effect can be obtained, and it becomes easy to produce a standardized CSP. And the like.

【0023】本発明の実施の形態では、CSPのインタ
ーポーザ1に補強部材6を形成し、インターポーザ1の
機械的強度を向上することにより、CSPのはんだ付け
(リフロー)時におけるインターポーザ1と封止樹脂8
の熱膨張係数差による反り応力を原因としたはんだ接続
不良を抑えることができる。本発明の実施の形態では、
封止樹脂を効率よく中心部分に流し込むことにより、熱
膨張係数差によってインターポーザ1に働く力を中心部
分に集中させることで、従来に比べ、反り応力を抑える
ことができ、インターポーザ1の反りを抑えることがで
きる。
In the embodiment of the present invention, the reinforcing member 6 is formed on the interposer 1 of the CSP to improve the mechanical strength of the interposer 1 so that the interposer 1 and the sealing resin at the time of soldering (reflow) the CSP are formed. 8
Defective solder connection due to warpage stress due to the difference in thermal expansion coefficient of the solder. In the embodiment of the present invention,
By efficiently flowing the sealing resin into the central portion, the force acting on the interposer 1 due to the difference in thermal expansion coefficient is concentrated on the central portion, so that the warpage stress can be suppressed as compared with the conventional case, and the warpage of the interposer 1 can be suppressed. be able to.

【0024】本発明の実施の形態では、インターポーザ
1に形成した補強部材6をガイドとすることで、封止樹
脂流し込みのプロセスを効率的に行うことができ、生産
性を向上させ得る。本発明の実施の形態では、インター
ポーザ1に形成した補強部材6をダムとして用いるの
で、封止樹脂を節約できる。本発明の実施の形態では、
インターポーザ1に形成した補強部材6をダムとして用
いるので、封止樹脂を成型できる。半導体チップを実装
基板のような配線基板に搭載する際、半導体と実装基板
を接続するインターポーザに硬度の高い材料を補強部材
として貼り付けることにより、インターポーザの弾性強
度が上がりインターポーザの反りを抑え高い接続信頼性
を得るとともに、封止樹脂の効率的供給による高い生産
性を得る。
In the embodiment of the present invention, by using the reinforcing member 6 formed on the interposer 1 as a guide, the process of pouring the sealing resin can be performed efficiently, and the productivity can be improved. In the embodiment of the present invention, since the reinforcing member 6 formed on the interposer 1 is used as a dam, the sealing resin can be saved. In the embodiment of the present invention,
Since the reinforcing member 6 formed on the interposer 1 is used as a dam, a sealing resin can be molded. When a semiconductor chip is mounted on a wiring board such as a mounting board, a high-hardness material is applied as a reinforcing member to the interposer connecting the semiconductor and the mounting board, thereby increasing the elastic strength of the interposer and suppressing the warpage of the interposer and providing a high connection. Along with obtaining reliability, high productivity is obtained by efficient supply of the sealing resin.

【0025】補強部材は、好ましくはインターポーザの
一方の面のみに限らず周囲あるいは上述したようなイン
ターポーザの一方の面の周囲や、インターポーザの内部
に形成することも可能である。すなわちインターポーザ
の大きさに比べて補強部材をやや小さくすることで、そ
の補強部材の範囲内に封止樹脂を供給するのである。
The reinforcing member is preferably formed not only on one surface of the interposer but also around it, around one surface of the interposer as described above, or inside the interposer. That is, by making the reinforcing member slightly smaller than the size of the interposer, the sealing resin is supplied within the range of the reinforcing member.

【0026】[0026]

【発明の効果】以上説明したように、本発明によれば、
半導体チップを配線基板に対して電気的に接続する際
に、電気的な接続信頼性と機械的な強度を得て、中間物
と封止樹脂間の熱膨張係数差によるCSPの反りを防ぐ
ことができる。
As described above, according to the present invention,
To obtain electrical connection reliability and mechanical strength when electrically connecting a semiconductor chip to a wiring board to prevent CSP warpage due to the difference in thermal expansion coefficient between the intermediate and the sealing resin. Can be.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体装置の好ましい実施の形態を示
す断面図。
FIG. 1 is a sectional view showing a preferred embodiment of a semiconductor device of the present invention.

【図2】図1の半導体装置の平面図。FIG. 2 is a plan view of the semiconductor device of FIG. 1;

【図3】インターポーザ(中間物)に対して補強部材を
接着剤により固定している状態を示す図。
FIG. 3 is a diagram showing a state in which a reinforcing member is fixed to an interposer (intermediate) with an adhesive.

【図4】インターポーザの補強部材の中に対して封止樹
脂を供給する例を示す図。
FIG. 4 is a diagram illustrating an example in which a sealing resin is supplied into a reinforcing member of the interposer.

【図5】本発明の半導体基板の別の実施の形態を示す
図。
FIG. 5 is a diagram showing another embodiment of the semiconductor substrate of the present invention.

【図6】本発明の半導体装置のさらに別の実施の形態を
示す図。
FIG. 6 is a diagram showing still another embodiment of the semiconductor device of the present invention.

【図7】従来の半導体装置を示す図。FIG. 7 illustrates a conventional semiconductor device.

【符号の説明】 1・・・インターポーザ(中間物)、2・・・半導体チ
ップ、3・・・チップ電極、4・・・配線電極、5・・
・ワイヤー、6・・・補強部材、7・・・接着剤、8・
・・封止樹脂(封止部材)、20・・・配線基板、30
・・・封止樹脂の供給手段
[Description of Signs] 1 ... Interposer (intermediate), 2 ... Semiconductor chip, 3 ... Chip electrode, 4 ... Wiring electrode, 5 ...
・ Wire, 6 ・ ・ ・ Reinforcing member, 7 ・ ・ ・ Adhesive, 8 ・
..Sealing resin (sealing member), 20... Wiring board, 30
... Supplying means for sealing resin

Claims (9)

【特許請求の範囲】[Claims] 【請求項1】 集積回路を有する半導体チップと、 電気的配線を有する配線基板と、 半導体チップを配線基板に実装して電気的に接続する際
に、配線基板と半導体チップの間に配置されて配線基板
と半導体チップを電気的に接続する中間物であって、機
械的強度を確保するための補強部材を有する中間物と、 半導体チップの配線部分を保護するための封止部材と、
を備えることを特徴とする半導体装置。
A semiconductor chip having an integrated circuit; a wiring board having electrical wiring; and a semiconductor chip mounted on the wiring board and electrically connected to the wiring board when the semiconductor chip is mounted on the wiring board. An intermediate for electrically connecting the wiring board and the semiconductor chip, the intermediate having a reinforcing member for ensuring mechanical strength, a sealing member for protecting a wiring portion of the semiconductor chip,
A semiconductor device comprising:
【請求項2】 中間物の補強部材は封止樹脂を成形する
際の成形型である請求項1に記載の半導体装置。
2. The semiconductor device according to claim 1, wherein the intermediate reinforcing member is a mold for molding the sealing resin.
【請求項3】 中間物の補強部材は封止樹脂を成形する
際の成形型であり、補強部材は金属部材である請求項1
に記載の半導体装置。
3. The reinforcing member as an intermediate is a mold for molding the sealing resin, and the reinforcing member is a metal member.
3. The semiconductor device according to claim 1.
【請求項4】 中間物の補強部材は、中間物の一方の表
面に設けられている請求項1に記載の半導体装置。
4. The semiconductor device according to claim 1, wherein the intermediate reinforcing member is provided on one surface of the intermediate.
【請求項5】 中間物の補強部材は、中間物の一方の表
面の四隅部分に設けられている請求項4に記載の半導体
装置。
5. The semiconductor device according to claim 4, wherein the intermediate reinforcing members are provided at four corners of one surface of the intermediate.
【請求項6】 中間物の補強部材は、中間物の一方の表
面の四隅部分に接着剤又は固定具を用いて設けられてい
る請求項5に記載の半導体装置。
6. The semiconductor device according to claim 5, wherein the intermediate reinforcing members are provided at four corners of one surface of the intermediate using an adhesive or a fixing tool.
【請求項7】 中間物の補強部材は、中間物の内部に形
成されている請求項1に記載の半導体装置。
7. The semiconductor device according to claim 1, wherein the intermediate reinforcing member is formed inside the intermediate.
【請求項8】 集積回路を有する半導体チップを、電気
的配線を有する配線基板に対して実装して電気的に接続
する際に、 配線基板と半導体チップの間に中間物を配置して配線基
板と半導体チップを電気的に接続する際に、中間物とし
ては機械的強度を確保するために補強部材を有するもの
を採用し、 配線部分を保護するために封止樹脂を形成する際に、補
強部材を成形型として用いて封止樹脂を成形することを
特徴とする半導体装置の製造方法。
8. When a semiconductor chip having an integrated circuit is mounted and electrically connected to a wiring board having electric wiring, an intermediate is arranged between the wiring board and the semiconductor chip to form a wiring board. When electrically connecting the semiconductor chip to the semiconductor chip, an intermediate product that has a reinforcing member to ensure mechanical strength is adopted.When forming a sealing resin to protect the wiring, A method for manufacturing a semiconductor device, comprising molding a sealing resin using a member as a mold.
【請求項9】 中間物の補強部材は、中間物の一方の表
面の四隅部分に設けられている請求項8に記載の半導体
装置の製造方法。
9. The method according to claim 8, wherein the intermediate reinforcing members are provided at four corners of one surface of the intermediate.
JP10219218A 1998-08-03 1998-08-03 Semiconductor device and its manufacture Pending JP2000058719A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10219218A JP2000058719A (en) 1998-08-03 1998-08-03 Semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10219218A JP2000058719A (en) 1998-08-03 1998-08-03 Semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JP2000058719A true JP2000058719A (en) 2000-02-25

Family

ID=16732062

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10219218A Pending JP2000058719A (en) 1998-08-03 1998-08-03 Semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JP2000058719A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20120010616A (en) * 2010-07-21 2012-02-06 삼성전자주식회사 Stack package, semiconductor package and method of manufacturing the stack package

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20120010616A (en) * 2010-07-21 2012-02-06 삼성전자주식회사 Stack package, semiconductor package and method of manufacturing the stack package
KR101678539B1 (en) * 2010-07-21 2016-11-23 삼성전자 주식회사 Stack package, semiconductor package and method of manufacturing the stack package

Similar Documents

Publication Publication Date Title
US7268414B2 (en) Semiconductor package having solder joint of improved reliability
US7615871B2 (en) Method and apparatus for attaching microelectronic substrates and support members
JPH08306853A (en) Semiconductor device, manufacture thereof and manufacture of lead frame
WO2004004005A1 (en) Semiconductor device and its manufacturing method
JP2000031343A (en) Semiconductor device
JPH10242385A (en) Power hybrid integrated-circuit device
JP3226244B2 (en) Resin-sealed semiconductor device
JPH11345900A (en) Semiconductor device
JP2000058719A (en) Semiconductor device and its manufacture
US8878070B2 (en) Wiring board and method of manufacturing a semiconductor device
JP2009231296A (en) Heat radiation type multiple hole semiconductor package
JP3495566B2 (en) Semiconductor device
JP3182378B2 (en) Semiconductor device and hybrid integrated circuit device
KR100258351B1 (en) Semiconductor package
KR100195507B1 (en) Slim type semiconductor chip package device
JPH10214934A (en) Semiconductor device and its manufacture
JPH08181165A (en) Semiconductor integrated circuit
JPH11260963A (en) Semiconductor device, and its manufacture
JP2000232198A (en) Semiconductor integrated circuit device and its manufacture
JP2004179300A (en) Semiconductor device and its manufacturing method
JPH06232199A (en) Packaging structure for flip chip ic
JPH0831986A (en) Semiconductor device having heatsink
KR100525452B1 (en) Semiconductor package & PCB mounted with the same
JP2003218290A (en) Resin-sealing semiconductor device
JP2004327912A (en) Semiconductor package and semiconductor device