JP2000058657A - Design method and design equipment of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent increase in wiring capacitance by judging whether a flattened pattern can be arranged in positions of all through holes, arranging the flattened pattern in the position capable of arrangement according to the judgment, and registering the final arrangement coordinate of the flattened pattern. SOLUTION: An arrangement judging part 8 of a program processing part 5 judges whether a flattened pattern can be arranged in the positions of all through holes, according to the rule of a wiring condition file 3, in the order of priority of a layout position file 2. When the flattened pattern can not be arranged by the judging process, a pattern layout part 9 judges whether the flattened pattern can be arranged in the next position, and the flattened part is arranged in the position capable of layout. A coordinate registering part 10 executes sequentially the layout to the positions of all through holes, and registers the final layout coordinate of the flattened pattern in design data base.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device design technique, and more particularly to an automatic generation of a flattening pattern.
The present invention relates to a technique which is effective when applied to a semiconductor device designing method and a designing apparatus suitable for a method of arranging the flattening pattern using a bit map.

[0002]

2. Description of the Related Art For example, as a technique studied by the present inventor, in recent LSI manufacturing techniques, with the miniaturization of LSIs and the increase in the number of wiring layers, the yield of through holes has been reduced due to wiring steps. Stopping is an important issue. Improving the yield of through-holes only by devising the process increases the complexity of the process, and on the contrary, may lower the yield and increase the cost. on the other hand,
As one of means for securing the yield of the through hole irrespective of the process, a method of arranging a metal pattern of the same material as the wiring, that is, a flattening pattern, in the underlying wiring layer of the through hole can be considered.

A design technique for arranging such a flattening pattern is disclosed in, for example, November 30, 1984.
Techniques described in documents such as “LSI Handbook” published by Ohm Co., Ltd., edited by the Institute of Electronics, Communication and Communication Engineers, Inc., P193-P217.

[0004]

By the way, in the technique of arranging the flattening pattern as described above, the yield of through holes can be secured by arranging the flattening pattern as shown in FIG. Fig. 13 (a) ~
FIG. 1C shows an example of a three-layer structure including a first metal wiring layer M1, a second metal wiring layer M2, and a third metal wiring layer M3.
3A shows a sectional view before the flattening pattern P is arranged, and FIG. 13B shows a sectional view after the flattening pattern P is arranged. In addition,
TH * is a through hole.

As apparent from FIG. 13, in FIG. 13 (a) before the arrangement of the flattening pattern P, the through hole T due to the difference in the interlayer film thickness due to the wiring step due to the difference in the wiring interval.
The H depth variation and the residual organic HSG film used for flattening the wiring step at the etched portion of the through hole TH occur. On the other hand, as shown in FIG. 13B, if a flattening pattern is arranged on the underlying wiring layer of the through hole TH, a wiring step which causes a decrease in the yield of the through hole TH is eliminated, and the yield of the through hole TH is secured. Becomes possible.

Further, since the flattening pattern is made of the same material as the wiring pattern, the layout of the through holes in the underlying wiring layer is restricted by design rules. Specifically, only the minimum flattening pattern necessary for eliminating the wiring level difference is arranged, the extra wiring capacity is not increased, and a layout error with other wiring due to the flattening pattern arrangement is avoided. It is necessary to consider it, and even in the same process, rules for arranging the planarization pattern may be different.

For example, as a method of arranging a flattening pattern, a method of arranging flattening patterns at equal intervals in an unwired area and a method of using a layout editor to apply a flattening pattern fixed to the arrangement coordinates of through holes in an underlying wiring layer are used. And deleting the flattening pattern that violates the layout rule by design rule check. In the former method, flatness is ensured, but the parasitic capacitance increases. In the latter method, there is only one type of flattening pattern arrangement rule. Conceivable.

Therefore, an object of the present invention is to arrange only a minimum flattening pattern necessary for eliminating the wiring step,
In consideration of the two points of not increasing the extra wiring capacity and avoiding layout errors with other wiring due to the flattening pattern arrangement, refer to only the through hole arrangement part,
By executing multiple placement rules while recognizing the width of the wiring including the placed flattening pattern, the increase in parasitic capacitance is suppressed, and the flatness right under the through-hole is secured, thus reducing processing time and versatility. It is an object of the present invention to provide a method and an apparatus for designing a semiconductor device capable of realizing the securing.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the method for designing a semiconductor device according to the present invention is applied to a design method for automatically generating a flattening pattern to be arranged in an underlying wiring layer of a through hole. (DA grid), the first step of converting the arrangement coordinates of the through-holes to the coordinates on the DA grid based on the layout data, and inputting the underlying wiring layer and setting a flag indicating the information of the wiring pattern on the DA grid. A second step of erecting, a third step of determining whether a flattening pattern can be arranged in accordance with the rules of the arrangement condition file in the priority order of the arrangement position file with respect to the arrangement position of the through-hole, and a case where the flattening pattern cannot be arranged. Determines whether the flattening pattern can be arranged at the next position, and arranges the flattening pattern at the position where the flattening pattern can be arranged. The third step and the fourth step is performed in sequence with respect to the arrangement position of Lumpur, a fifth step of registering the location coordinates of the final planarization pattern, and has a.

Specifically, it has the following steps.

(1) The entire surface of the chip is divided by a DA grid, layout data read from the design database is converted into flags representing information on wiring patterns, and the flags are set on each DA grid point.

(2) A flattening pattern arrangement candidate point is searched for the arrangement coordinates of each through-hole based on the arrangement position rules registered in the flattening pattern arrangement rule library. Next, a flattening pattern arrangement determination grid composed of grid points used for flattening pattern arrangement determination is set for each arrangement candidate point.

(3) The flag based on the placement condition rule registered in the flattening pattern placement rule library is compared with the flag in the placement determination grid. If the flattening pattern can be arranged in all the judgment grids, the coordinates are stored, and the process proceeds to the coordinates of the next through hole. If there is at least one non-arrangeable flattening pattern, the process returns to (2) and the arrangement determination grid is set again. However, if all the placement rules have been exhausted, the process moves to the next through hole.

(4) When the determination of the flattening pattern arrangement is completed for the coordinates of all the through holes, the stored flattening pattern arrangement coordinates are registered in the design database.

In the above process, the arrangement position file is a file in which the priorities of the flattening pattern arrangement for securing the flattening just below the through holes are defined and described.
It is registered in the flattening pattern placement rule library, and the priority order of the flattening pattern placement is determined in consideration of the number of flattening patterns to be placed. The arrangement is performed in the order of arrangement at the diagonal corner.

The layout condition file describes a layout rule in which a flattening pattern must not be placed or a layout rule to be placed. The layout condition file is registered in a flattening pattern placement rule library. The layout rules that must not be placed are as follows: when the flattening pattern causes a short circuit with the underlying wiring, when it causes angular contact with the underlying wiring, when it overlaps with the placement prohibited area, when there is a minute gap between it and the underlying wiring. Is what you do.

Further, a semiconductor device design apparatus according to the present invention includes a design database for storing layout data and registering layout coordinates of a flattening pattern, and a flattening pattern layout for ensuring flatness immediately below a through hole. A layout pattern library for registering a layout position file describing the layout priorities and layout rules in which the flattening pattern must not be placed or layout rules desired to be placed, and a DA grid for the chip , And the layout coordinates of the through-holes based on the layout data of the design database
A first means for converting the coordinates on the A grid, a second means for inputting the underlying wiring layer and setting a flag on the DA grid, and a layout condition file for the layout positions of the through holes in the priority order of the layout position file A third means for determining whether or not the flattening pattern can be arranged according to the rule of the above, and if the flattening pattern cannot be arranged, it is determined whether or not the flattening pattern can be arranged at the next position. There is provided a fourth means for arranging, and a fifth means for sequentially executing the arrangement of all the through holes and registering the arrangement coordinates of the final flattening pattern in a design database.

According to the method and apparatus for designing a semiconductor device, a plurality of placement rules can be executed while referring to only the placement portion of the through hole and recognizing the width of the wiring including the placed flattening pattern. Therefore, the processing time can be reduced, and versatility can be ensured. At this time, only the minimum flattening pattern necessary for eliminating the wiring step is arranged, and it is possible to avoid a layout error with other wiring due to the flattening pattern arrangement without increasing extra wiring capacitance.

[0021]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a schematic configuration diagram showing an apparatus for designing a semiconductor device according to an embodiment of the present invention. FIG. 2 is a flowchart showing a method of designing a semiconductor device in the embodiment.
Is an explanatory diagram showing an arrangement position file, FIG. 4 is an explanatory diagram showing a flag, FIG. 5 is an explanatory diagram showing an arrangement condition file, and FIGS.
FIG. 12 is an explanatory diagram showing processing of the flattening pattern arrangement design method.

First, a schematic configuration of a semiconductor device design apparatus according to the present embodiment will be described.

The semiconductor device designing apparatus according to the present embodiment
For example, a design apparatus including a work station or the like that automatically generates a flattening pattern to be arranged on the underlying wiring layer of the through hole is provided. The design database 1 stores layout data and registers the arrangement coordinates of the flattening pattern.
And an arrangement position file 2 in which the priorities of the arrangement of the flattening patterns for securing the flatness immediately below the through holes are defined and described, and a layout rule in which the flattening patterns are not to be arranged or a layout rule to be arranged is described. It comprises a flattening pattern arrangement rule library 4 for registering the arrangement condition file 3 and a program processing unit 5 by software.

The program processing unit 5 divides the chip by a DA lattice, converts the arrangement coordinates of the through holes into coordinates on the DA lattice based on the layout data of the design database 1, and inputs the underlying wiring layer. Then, a flag setting unit 7 for setting a flag on the DA grid, and a placement determining unit for determining whether a flattening pattern can be placed in accordance with the rules of the placement condition file 3 in the priority order of the placement position file 2 with respect to the placement positions of the through holes. 8. If the flattening pattern cannot be arranged, it is determined whether or not the flattening pattern can be arranged at the next position, and the pattern arranging section 9 for arranging the flattening pattern at the position where the flattening pattern can be arranged. And a coordinate registration unit 10 for sequentially executing the arrangement coordinates of the flattening pattern in the design database.

Next, the operation of this embodiment will be described with reference to FIG.
3 to FIG. 12, a flat pattern arrangement design method in a semiconductor device design method will be described with reference to FIGS.

1. Prior to the flattening pattern arrangement processing, the designer creates an arrangement position file 2 of an arrangement position rule in which the priorities of the flattening pattern arrangement for securing the flattening immediately under the through-hole are defined and described (step 20).
1). The designer uses the GUI to specify the position of the flattening pattern to be arranged when the through hole is the center on the DA grid. The designation is converted into a layout position file 2 represented by “0” or “1”. The arrangement position file 2 is registered in the flattening pattern arrangement rule library 4.

For example, as shown in FIG. 3, the order of priority for specifying the placement of the flattening pattern is determined by taking into account the number of flattening patterns P from one to four as shown in FIG. When the pattern P is arranged directly below the through hole TH, as shown in (b), on the left and right of the through hole TH, as shown in (c), when it is arranged above and below the through hole TH, as shown in (d), In the case of being arranged at the diagonal corner of the through hole TH. The corresponding position specification files are (e), (f), (g), and (h), respectively. In addition,
The priority order of the layout specification of the flattening pattern P is also conscious of the underlying wiring direction.

2. Prior to the flattening pattern arrangement processing, the designer creates an arrangement condition file 3 of an arrangement condition rule in which a layout rule in which the flattening pattern P must not be arranged or a layout rule to be arranged is described (step 202). The designer uses the GUI on the DA grid,
The flattening pattern P cannot be arranged (or can be arranged)
Specify the case. The designation is converted into an arrangement condition file 3 represented by various flags as shown in FIG. This arrangement condition file 3 is converted into a flattening pattern arrangement rule library 4
Register with.

For example, a layout rule in which the flattening pattern P must not be arranged is as shown in FIG. 5A. When the flattening pattern P is arranged as shown in FIG. A case where the placement of the flattening pattern P causes angular contact with the underlying wiring is prohibited. The corresponding flag-specified files are (c),
(d), (e), (f), (g), (h).

3. In the flattening pattern arranging process, the layout data after the completion of the design of the design database 1 and the arrangement rule library of the arrangement position file 2 and the arrangement condition file 3 are input, and the following for each through-hole layer where the flattening pattern P is to be arranged. Repeat steps.

(1) The chip is divided by a DA lattice, and the arrangement coordinates of the through holes TH are converted into coordinates on the DA lattice based on the layout data of the design database 1 (step 203). For example, in FIG. 6, (a, b),
(C, d), (e, f), (g, h) are through holes T
Represents the location of H.

(2) Input the underlying wiring layer and set the flag shown in FIG. 4 on the DA grid (step 204). For example, the case of FIG. 6 is as shown in FIG. That is, "1", "2", and "3" flags are set on the DA grid of the underlying wiring of the through-hole TH, and the placement prohibited D
A flag “4” is set on the A grid.

(3). In the process of arranging the flattening pattern P, Y
(A, b) → (c, d) → (e, f) →
As shown in (g, h), processing of the arrangement position of the through hole TH is performed in order from the lower left.

(4) It is determined whether or not the flattening pattern P can be arranged according to the rules of the arrangement condition file 3 in the priority order of the arrangement position file 2 (step 205). For example,
In the example of FIG. 3, since the arrangement immediately below the through hole TH has the highest priority, whether or not the flattening pattern P can be arranged at (a, b) is compared with the condition of the arrangement condition file 3.
Since the arrangement condition is described by a 3 × 3 grid, a 3 × 3 grid centered on (a, b) is extracted as a location to be checked as shown in FIG. Since the extracted portion corresponds to the error case in FIG. 5 (g), the flattening pattern P cannot be arranged.

(5) In the placement position file 2, if the flattening pattern P cannot be placed immediately below the through hole TH,
It is required to arrange the flattening pattern P at the positions A and B in FIG. So, for example, as shown in FIG.
The same determination as in (4) above is made for the locations where A and B are checked. Since neither A nor B satisfies the error condition of FIG. 5, the flattening pattern P is arranged (step 206).

(6) The positions (c,
d), (e, f), and (g, h), also (a, b)
The processes (4) and (5) are performed in the same manner as described above. However, the determination is performed in consideration of the arrangement of the flattening pattern P. That is, in FIG. 7, the flattening pattern P is located immediately below (c, d).
Can be arranged, but because the flattening pattern P is arranged on A and B, the flag indicating the actual underlying wiring state changes as shown by the black frame in FIG. 10 and cannot be arranged. This is because it corresponds to FIG. 5 (f).

In (e, f), the flattening pattern P can be arranged immediately below, but the normal flattening pattern P cannot be arranged. This is because, when the arrangement is performed, a minute gap is generated as shown in FIG. 11B, and the yield is reduced due to the peeling of the resist. In order to observe the process rule when laying out a large-width wiring, the minute gap is such that the width of the minute gap protruding from the DA lattice becomes smaller than that of the normal wiring as shown in FIG. This is because it is designed to have the same width as the normal wiring in consideration of contact with the wiring. In the placement process of the flattening pattern P, the placement is performed by adding a minimum embedding pattern as shown in FIG.

Finally, in the case of (g, h), no arrangement can be performed for any arrangement of the flattening pattern P because the arrangement comes into contact with the arrangement prohibited area.

From the above, the final arrangement of the flattening pattern P is, for example, as shown in FIG. In the layout processing of the flattening pattern P, the layout coordinates of the flattening pattern P may be added to the input design data, registered in the design database 1, and further output as needed (step 207).

Therefore, according to the semiconductor device designing apparatus of the present embodiment, a partitioning flag is set on the entire surface of the chip by the DA lattice, the arrangement determination grid of the planarization pattern P is set, and the arrangement determination of the planarization pattern P is performed. By performing the respective design steps of registering the coordinates of the flattening pattern P and performing the plurality of layout rules while referring to only the through hole TH and recognizing the width of the underlying wiring, the minimum flatness is achieved. The layout error with other wiring due to the placement of the flattening pattern P can be avoided without increasing the extra wiring capacity by arranging only the patterned pattern P. Therefore, in the automatic generation of the flattening pattern P, the processing time can be reduced and the versatility can be ensured while suppressing the increase in the parasitic capacitance and securing the flatness directly below the through hole TH.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications may be made without departing from the gist of the invention. It goes without saying that it is possible.

For example, the priority order of the layout designation of the flattening pattern described in the layout position file is not limited to the case shown in FIG. 3, and the flattening pattern is assigned to each of the triangular points around the through hole. As in the case of arrangement, it is necessary to be aware of an example of arrangement of three flattening patterns.

[0044]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) The chip is divided by a DA grid, the layout coordinates of the through holes are converted into coordinates on the DA grid based on the layout data, the underlying wiring layer is input, a flag is set on the DA grid, and the through-hole is set. A determination is made as to whether or not a flattening pattern can be arranged in accordance with the rules of the arrangement condition in the priority order of the arrangement positions with respect to the hole arrangement position. And place the flattening pattern at a position where it can be placed, and execute it sequentially for all the through-hole placement positions, and register the placement coordinates of the final flattening pattern so that only the placement part of the through-hole is By referencing and recognizing the width of the wiring including the placed flattening pattern, multiple placement rules can be executed, so only the minimum flattening pattern necessary to eliminate wiring steps And it is possible to avoid a layout error with other wiring due to the flattening pattern arrangement without increasing extra wiring capacitance.

(2) According to the above (1), in the automatic generation of the flattening pattern, the processing time is reduced and the versatility is ensured while suppressing the increase in the parasitic capacitance and securing the flatness immediately below the through hole. It is possible to do.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing an apparatus for designing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a flowchart showing a method for designing a semiconductor device in one embodiment of the present invention.

FIGS. 3A to 3H are explanatory diagrams showing an arrangement position file in one embodiment of the present invention.

FIG. 4 is an explanatory diagram showing a flag in one embodiment of the present invention.

FIGS. 5A to 5H are explanatory diagrams showing an arrangement condition file in one embodiment of the present invention.

FIG. 6 is an explanatory diagram showing through holes and underlying wiring in one embodiment of the present invention.

FIG. 7 is an explanatory diagram showing a state in which a base wiring is converted into a flag in one embodiment of the present invention.

FIG. 8 is an explanatory diagram illustrating determination of a flattening pattern according to the embodiment of the present invention.

FIG. 9 is an explanatory diagram showing another determination of the flattening pattern in the embodiment of the present invention.

FIG. 10 is an explanatory diagram showing the status of a flag for a through hole in one embodiment of the present invention.

FIGS. 11A to 11C are explanatory diagrams illustrating another determination of a flattening pattern in the embodiment of the present invention.

FIG. 12 is an explanatory diagram showing a layout after a flattening pattern is arranged in one embodiment of the present invention.

FIGS. 13A to 13C are schematic views showing cross sections before and after the arrangement of a flattening pattern on the premise of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 design database 2 placement position file 3 placement condition file 4 flattening pattern placement rule library 5 program processing unit 6 coordinate conversion unit 7 flag setting unit 8 placement determination unit 9 pattern placement unit 10 coordinate registration unit P flattening pattern TH through hole

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Toshifumi Asanuma 1 Horiyamashita, Hadano-shi, Kanagawa F-term in Hitachi Information Technology Co., Ltd. 5B046 AA08 BA05 CA00 5F033 CA09 DA01 DA31 FA03 5F064 DD14 DD26 DD50 EE02 EE09 EE12 EE27 EE43 HH11 HH12

Claims (6)

[Claims] 1. A method of designing a semiconductor device, which automatically generates a flattening pattern to be arranged in a base wiring layer of a through-hole, wherein a chip is divided by a DA lattice, and layout coordinates of the through-hole are determined based on layout data. A first step of converting to upper coordinates, a second step of inputting a base wiring layer and setting a flag on a DA grid, and a rule of an arrangement condition file in a priority order of an arrangement position file with respect to an arrangement position of a through hole. A third step of determining whether or not a flattening pattern can be arranged according to the above. If the flattening pattern cannot be arranged, it is determined whether or not the flattening pattern can be arranged at the next position, and the flattening pattern is arranged at a position where it can be arranged. A fourth step, and the third step for arranging all the through holes;
And a fourth step of sequentially executing the step and the fourth step, and registering the final arrangement coordinates of the planarization pattern. 2. The method for designing a semiconductor device according to claim 1, wherein the arrangement position file defines and describes priorities of planarization pattern arrangements for securing planarization immediately below the through holes. And a method for designing a semiconductor device, wherein the method is registered in a flattening pattern arrangement rule library. 3. The method for designing a semiconductor device according to claim 2, wherein the priority order of the flattening patterns is determined by considering the number of the flattening patterns and arranging them immediately below the through holes. A method of designing a semiconductor device, wherein the method is arranged in the following order: when arranging right and left of the through hole, when arranging above and below the through hole, and when arranging it at a diagonal corner of the through hole. 4. The method for designing a semiconductor device according to claim 1, wherein the layout condition file describes a layout rule in which a flattening pattern is not to be arranged or a layout rule to be arranged. A method for designing a semiconductor device, wherein the method is registered in a pattern arrangement rule library. 5. The method for designing a semiconductor device according to claim 4, wherein the layout rule in which the flattening pattern must not be arranged is such that when the flattening pattern causes a short circuit with the underlying wiring, the flattening pattern is not formed. Cause angular contact with the underlying wiring, when the flattening pattern overlaps the placement prohibited area, or when a minute gap occurs between the flattening pattern and the underlying wiring. Method. 6. A design device for a semiconductor device, which automatically generates a flattening pattern to be arranged in an underlying wiring layer of a through hole, comprising: a design database for storing layout data and registering the layout coordinates of the flattening pattern; An arrangement position file that defines and describes the priorities of the flattening pattern arrangements for securing the flattening just below the through-holes, and an arrangement condition file that describes the layout rules that should not place the flattening patterns or the layout rules that you want to arrange A first flattening pattern arrangement rule library for registering a chip, a first means for separating chips by a DA lattice, and converting the arrangement coordinates of through holes into coordinates on the DA lattice based on the layout data of the design database; The second means for inputting and setting a flag on the DA grid, A third means for determining whether or not a flattening pattern can be arranged according to the rules of the arrangement condition file in order of priority of the arrangement position file; A fourth means for determining whether or not the through-holes can be arranged, and arranging the flattening patterns at the positions where the through-holes can be arranged; 5th to register with
Means for designing a semiconductor device.