JP2000056875A - Electronic device system and control method for electronic device system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a facsimile communication device of simple constitution which suppresses radiation noise even when electronic circuits operating with clock signals of the same frequency are present in the same system. SOLUTION: The electronic device system including the electric circuit parts of the same constitution operating with the clock signals of the same frequency delays the phases of the clock signals by delaying the source clock signal generated in an oscillator 9 by a delay circuit 10, and supplies the clock signals to the electronic circuit parts (TWINS-A6 and TWINS-B7) of the same constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an electronic device system including a plurality of electronic circuit units operating with clock signals of the same frequency, and a method of controlling the electronic device system.

[0002]

2. Description of the Related Art In a conventional facsimile apparatus, there is an apparatus having an external interface to which an optional board or the like can be connected. By connecting the optional board to this external interface, a line different from a line in which only the facsimile apparatus itself can communicate is used. Some have a configuration that allows the addition of a function that allows communication over the line.

Generally, in such a facsimile machine,
In addition to facsimile communication, it was possible to control recording using its own printing mechanism and reading of a document image using a reading mechanism. Further, in the case of a facsimile apparatus having an optional board, it was possible to control communication on another line.

A system control unit for controlling such a facsimile apparatus and a system of an option board has almost the same configuration, and is composed of a system IC of the same specification and a CPU of the same specification. For the exchange of information such as image data between the two, there is one IC of the same specification for bidirectional communication on the system side of the facsimile apparatus and one on the system side of the option board.

[0005] Two-way communication between the two devices has been performed according to the so-called Vicentronics specification conforming to IEEE 1284, which is an international recommendation. For this reason, an oscillation circuit for operating each IC is connected to the system IC, the CPU, and the IC for performing bidirectional communication.

That is, in the communication system, there are three groups of three types of ICs in which there are two sets of oscillation circuits of the same frequency for operating ICs of the same specification.

[0007]

However, in the conventional example described above, since a plurality of oscillation circuits of the same frequency exist in the communication system, radiation noise of the same frequency emitted from the oscillation circuit is superimposed. There has been a problem that radiated noise of the frequency emitted from the communication system increases.

In addition, the oscillations of the plurality of same frequency oscillation circuits are asynchronous, and when the phase difference between the plurality of same frequency oscillation circuits is accidentally reduced, the same specification operating by the oscillation of the oscillation circuits is used. The operation of the IC is also in the form of timing, and depending on the operation of the IC, the IC or
The timing of the generation of the transient current flowing to the IC output, for example, the timing of the generation of the transient current flowing when the output changes from the “H” level to the “L” level, matches the timing of the radiated noise. There has been a problem that the peak value also becomes large.

Further, considering the cost of the communication system,
Since there are two oscillation circuits with the same frequency, the configuration is complicated and this is a factor that increases costs. This was incompatible with the intended device design.

The use of a large number of components leads to a decrease in reliability, and the consumption of resources for producing the components and the adverse effect on the environment are increased. Therefore, considering the global environment, it is not preferable. It was a different thing.

[0011]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and has, for example, the following arrangement as one means for achieving the above objects.

That is, an electronic device system including a plurality of electronic circuit units operating with clock signals of the same frequency, wherein a clock generating means for generating the clock signal;
Delay means for delaying the original clock signal generated by the clock generation means, and delaying the original clock signal by the delay means to shift the phase of the clock signal and supply it to each electronic circuit unit. I do.

[0013] For example, the plurality of electronic circuit sections are each configured by a semiconductor integrated circuit having the same configuration.

Further, for example, when the external interface means and an external device connected to the external interface means have the same electronic circuit part as the electronic circuit part provided in the own apparatus, the clock signal delayed by the delay means is provided. And supply means for supplying the external device to the external device.

Further, for example, the electronic device system is characterized in that it is an optional board connected to an information processing device having external interface means.

An electronic apparatus system connected to an information processing apparatus having external interface means,
A clock receiving unit for receiving an operation clock signal of an electronic circuit unit provided in the information processing apparatus; an electronic circuit unit having the same configuration as the electronic circuit unit of the information processing apparatus; and a clock signal received by the clock receiving unit being delayed by a predetermined time. A delay unit that supplies the clock signal delayed by the delay unit to the electronic circuit unit to operate the electronic circuit unit with a clock signal having a phase different from that of the information processing device. .

An electronic device system comprising an electronic device main body having an external interface and an external device connected to the electronic device main body via the external interface, wherein the electronic device main body provided in the electronic device main body operates. A first system control unit to be performed, a second system control unit that operates its own device provided in the external device,
A first interface unit on the electronic device main body side and a second interface unit on the external device side provided between the first system control unit and the second system control unit; Provided in each of the interface means, an electronic circuit unit of the same configuration operating with a clock of the same frequency for performing bidirectional communication between the first system control unit and the second system control unit; A clock generation unit for generating an operation clock of the circuit unit; and a delay unit for delaying a clock signal generated by the clock generation unit, wherein the first and second interface units supply to the respective electronic circuit units. The delay amount of the delay means is made different so that the clocks do not have the same phase.

An electronic device system comprising an electronic device main body having an external interface and an external device connected to the electronic device main body via the external interface, wherein the electronic device main body provided in the electronic device main body operates. A first system control unit to be operated, a second system control unit that operates its own device provided in the external device, and each of the first system control unit and the second system control unit, An electronic circuit unit having the same configuration that operates with a clock of the same frequency for operating the first system control unit and the second system control unit, a clock generation unit that generates an operation clock of the electronic circuit unit, A clock generation unit for generating a clock signal; and a delay unit for delaying the clock signal, wherein the first and second system control units are respectively provided. Supplying operation clock to the electronic circuit unit and wherein varying the delay amount of said delay means so as not to the same phase that.

[0019] For example, the electronic circuit section is a CPU circuit for controlling each device.

Further, for example, the electronic device main body is a facsimile communication device, and the external device is an optional board connected to the facsimile communication device. Alternatively, the first system control unit performs transmission image reading or copy image reading control in a facsimile communication device and reception image recording or copy image recording control, and the second system control unit performs the facsimile communication on an option board. It is characterized in that communication control is performed via a line different from a line connected to the communication device.

Further, for example, the delay means is formed by an integrating circuit formed by a resistance component of a wiring pattern on a mounting substrate and a capacitance component generated between the wiring pattern and a ground pattern on the mounting substrate. It is characterized by. Alternatively, the delay means is constituted by an inverter digital circuit.
Alternatively, the delay means is constituted by an inductance component generated on a mounting board.

[0022]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a position invention according to the present invention.

[First Embodiment] FIG. 1 is a block diagram showing a schematic configuration of a communication control and option board part of a facsimile apparatus according to an embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes a facsimile apparatus main body which is an electronic apparatus according to the embodiment, and reference numeral 20 denotes an option board (option board) connected to the facsimile apparatus main body 1, and a connection line of the facsimile apparatus main body 1 L
1 is connected to another line L2 and controls another communication.
100 is a public network, 200 is a public network 100
Is another facsimile machine that can be connected to

In the facsimile apparatus body 1, 2 is R
The CPU-A controls the overall control of the apparatus 1 in accordance with the control procedure stored in the OM 54. 3 is an option board 20
External interface A that controls the interface between
(I / FA) 4 is a FUNK-A which is a system IC for performing facsimile communication control under the control of the CPU 1.

In the option board 20, reference numeral 5 denotes an external interface B (I / FB) for controlling an interface with the facsimile apparatus main body 1, and an I / F cable 80.
Is connected to the facsimile apparatus main body 1 via the. 6
Is an international recommendation called IEEE1284,
TWINS-A is an IC for performing data communication of a so-called Vicentronics interface.

Reference numeral 7 denotes TWINS-B, which is the same IC as TWINS-A6. Reference numeral 8 denotes a CPU that controls the entire board 20 according to a control procedure stored in the ROM 68.
-B. 9 is an oscillation circuit for generating an operation clock signal of a predetermined frequency, 10 is a delay circuit, and 11 is a system IC for performing facsimile communication control under the control of the CPU-B8.
FUNK-B.

The clock generated by the oscillation circuit 9 is TW
The clock signal supplied to INS-A6 and delayed by the delay circuit 10 is supplied to TWINS-B7. As a result, TWINS-A6 and TWI operating at the same frequency
NS-B7 is supplied with a clock signal shifted in phase,
The operation is performed by the clock signal having the shifted phase.

Next, the facsimile apparatus body 1 described above
FIG. 2 shows the detailed configuration of FIG. FIG. 2 is a block diagram showing a detailed configuration of the facsimile apparatus main body 1, and shows a configuration of a communication unit, a document reading unit, and a recording unit.

In the facsimile apparatus main body 1 shown in FIG. 2, reference numeral 40 denotes a first control unit including the CPU-A2 and FUNK-A4 shown in FIG. The first control unit 40 controls each component shown in FIG.

That is, a document reading section 41 which includes a document conveying motor 42 and reads a transmitted document and converts the read document into image data.
A network control unit (NCU) 43 for connecting a telephone line to a facsimile; a modulation / demodulation unit (modem) 44 for performing communication; an operation panel 45 for allowing a user to instruct an operation command to each unit of the apparatus; A first drive system 49 including a first sensor 48 for detecting a state and a reading motor for conveying a document is controlled.

A read image processing unit 50 for controlling access to a memory 51 for storing various data and processing image data read by the document reading unit 41, and reading read image data or a received encoded image. It controls a scaling unit 55 that scales the image data obtained by decoding the decoded image data or the image data obtained by decoding the image data stored in the coded memory.

Further, an encoder 56 for encoding the read image data and re-encoding the received image data, and decoding the received image data and decoding the read and encoded image data. And a recording unit 30 for printing a received image or a copied image.

The operation panel 45 has a display 46 for displaying the status of the facsimile to the user, and keys 47 for the user to instruct the facsimile to perform various operations.

The memory 51 includes an image memory 52 for storing received image data and the like, a system RAM (or system memory) 53 that is backed up by a battery or the like even when a commercial power supply is cut off due to a power failure and the data is not destroyed,
A ROM 54 for storing information for determining the specifications of the facsimile, as well as storing the control procedure of -B8.

Another detailed configuration of the option board 20 shown in FIG. 1 will be described with reference to FIG. FIG. 3 is a block diagram showing a detailed configuration of the option board shown in FIG.

In FIG. 3, reference numeral 60 denotes a CPU-B8 and a FUNK-B1 shown in FIG.
1 is a second control unit including the first control unit 1. The second control unit 60 controls each component shown in FIG.

That is, an encoder 61 for encoding the image data read by the facsimile apparatus main unit 1 and for re-encoding the received image data, decoding the received image data, and reading the code by the main unit. And a network control unit (NCU) 63 for connecting a telephone line to a facsimile.
And a modulation / demodulation device (modem) 64 for performing communication.

The access control of the memory 53 for storing various data is performed, and the image data read by the facsimile apparatus main body 1, the image data obtained by decoding the received encoded image data, or the facsimile apparatus main body 1 And controls the scaling unit 69 for scaling the image data obtained by decoding the image data stored in the memory in which the image data read in step 2 is encoded.

The memory 65 includes an image memory 66 for storing received image data and the like, a system RAM (or system memory) 67 that is backed up by a power supply or the like even when the commercial power supply is cut off due to a power failure and the data is not destroyed,
A ROM 68 for storing the control procedure of -B8 and determining the specifications of the option board.

This embodiment comprises the facsimile apparatus main body 1, the option board 20, and a communication system including the above-described components.

In the present embodiment, by providing the above-described configuration, clocks are supplied from one oscillation circuit to a plurality of ICs, and the phases of the plurality of clocks are shifted by a delay circuit to thereby reduce radiation noise. And the cost of the apparatus can be reduced.

That is, two identical ICs operating with clocks of the same frequency, TWINSA / B, are included in the system, and an oscillator 9 for generating the clock and a delay circuit 10 at a stage subsequent to the oscillator 9 are provided. By shifting the phases of the clocks supplied to the plurality of identical ICs by the delay circuit 10, the radiation noise can be reduced and the cost of the apparatus can be reduced.

A communication system including a facsimile machine main body 1 having an external interface and an option board 20 connected to the facsimile machine main body 1 has the following features.
The facsimile machine body 1 includes a first control unit 40 for operating the facsimile machine,
Contains a second control unit 60 for operating the option board, which is different from the first control unit 20, and an interface between the first control unit 20 and the second control unit 60 includes
An oscillator 9 for generating two clocks having the same frequency and operating at the same frequency for performing bidirectional communication between the first controller 20 and the second controller 60; 10 and the phase of the clock generated by the oscillator 9 supplied to the two same ICs,
, The radiation noise and the cost of the apparatus can be reduced.

[Second Embodiment] In the first embodiment described above, the option board 20 is provided with the oscillator 9, but the option board 20 is not necessarily provided with the oscillator 9. The configuration may be such that an operation clock signal is received from the facsimile machine body 1. The second embodiment according to the present invention thus configured
An embodiment of the present invention will be described with reference to FIG.

FIG. 4 is a block diagram showing a schematic configuration of a communication control and option board portion of the facsimile apparatus according to the second embodiment of the present invention. In FIG. 4, the same components as those in the first embodiment shown in FIG. 1 described above are denoted by the same reference numerals, and detailed description thereof will be omitted. In FIG. 4, only the communication control of the facsimile apparatus and the option board portion are shown, and the public line network and the like are omitted.

The configuration different from the configuration shown in FIG. 1 is the configuration of the interface between the facsimile apparatus main body 1 and the option board 20.
The point is that the I / FA 3 and the I / F 5 are arranged between the WINS-B7.

As a result, the clock signal from the oscillator 9 is supplied to the delay circuit 1 via the I / F3, the cable 80, and the I / F5.
Sent to 0.

As described above, according to the second embodiment, the clock signal generated in the facsimile apparatus main body 1 is converted into an IC (TWINS) on the facsimile apparatus main body 1 side.
-A6) and the same IC (TWINS-B7) with the same IC (TWINS-B7) and the optional circuit 20 containing the delay circuit 10 and the phase shifted by the delay circuit 10.
By supplying to the device, radiation noise can be reduced and the cost of the device can be reduced.

[Third Embodiment] The third embodiment according to the present invention
An embodiment of the present invention will be described with reference to FIG. FIG.
FIG. 7 is a block diagram showing a schematic configuration of a communication control and option board portion of a facsimile apparatus according to a third embodiment of the present invention. 5, the same components as those in the first embodiment shown in FIG. 1 described above are denoted by the same reference numerals, and detailed description will be omitted. In FIG. 5, only the communication control of the facsimile apparatus and the option board portion are shown, and the public line network and the like are omitted.

In the third embodiment shown in FIG. 5, a clock signal for driving the CPU-A2 and the CPU-B8 is provided on the facsimile apparatus body 1 side, and an oscillator 9 and a delay circuit 10 are provided. Is a point.

As a result, the clock signal from the oscillator 9 is directly supplied to the CPU-A2, delayed by the delay circuit 10 and supplied to the CPU-B8 via the I / F3, the cable 80, and the I / F5. .

As described above, according to the third embodiment, the facsimile apparatus is a communication system including the facsimile apparatus main body 1 having an external interface and the option board 20 connected to the facsimile apparatus main body 1. , And a first control unit 40 shown in FIG.
A second control unit 6 for operating the option board, which is different from the
0 and the same frequency clock for performing bidirectional communication between the first control unit 40 and the second control unit 60 at the interface between the first control unit 40 and the second control unit 60. An oscillator 9 having two identical ICs operating and generating an operation clock, and a delay circuit 10 included in the facsimile apparatus body 1, and a phase of a clock signal generated by the oscillator 9 being shifted by the delay circuit 10 By supplying to the 10 side, radiation noise can be reduced and the cost of the apparatus can be reduced.

[Fourth Embodiment] A fourth embodiment of the present invention will be described with reference to FIG. FIG. 6 is a diagram showing a configuration example of the clock signal delay means of the option board 20 according to the fourth embodiment of the present invention. In the fourth embodiment shown in FIG. 6, a bending pattern and a bending pattern for generating a resistance component indicated by reference numeral 101 are provided on an option substrate 20 as delay means for a clock signal from the oscillation circuit 9. A ground pattern (ground pattern), for example, 102 is provided near 101.

As a result, a stray capacitance (stray capacity) is generated between the bent pattern 101 and the ground pattern 102 on the option board 20.
Resistance component of bent pattern 101 and ground pattern 10
The equivalent circuit shown in FIG. 7 exists due to the stray capacity (stray capacity) generated between the circuit 2 and FIG.

FIG. 7 is a diagram showing an equivalent circuit of the clock delay means shown in FIG. 6 in the fourth embodiment.

Both patterns 101 and 102 shown in FIG.
The phase of the clock signal can also be made different by configuring the delay means with the RC integration circuit formed by. FIG. 8 shows an example of the delay timing by the delay means in the fourth embodiment. FIG. 8 is a diagram for explaining the principle of delay of the clock signal by the equivalent circuit shown in FIG.

In FIG. 8, Vi is the output waveform of the oscillation circuit 9 when the clock Vi arrives at the bending pattern 101, Vo is the output waveform of the RC integration circuit constituting the delay means, and Vx is the IC input with Vo. It is a clock waveform after passing through a gate circuit inside the IC.

In the example of FIG. 8, Vo after passing through the delay circuit
Is gated by a hysteresis loop (Schmitt trigger circuit), and the clock Vx transmitted to the internal circuit as the operation clock of the IC is delayed with respect to Vi.

As described above, also in the fourth embodiment, the radiation noise can be reduced and the cost of the apparatus can be reduced by using only simple components.

[Fifth Embodiment] The fifth embodiment according to the present invention
An embodiment of the present invention will be described with reference to FIG. FIG.
FIG. 15 is a diagram showing a configuration example of a delay circuit of an option board 20 according to a fifth embodiment of the present invention. In the fifth embodiment shown in FIG. 9, a NOT circuit (inverter circuit) 103 is mounted as delay means for a clock signal from the oscillation circuit 9.

As described above, in the fifth embodiment, N
The phase is rotated by 180 degrees by the OT circuit 103, and the operation timing is controlled so as not to be the same.

As described above, according to the fifth embodiment, since the delay circuit is constituted by the inverter circuit 103 for inverting a digital signal, a simple circuit can be realized.
Radiation noise can be reduced and the cost of the device can be reduced.

[Sixth Embodiment] In the above-described fifth embodiment shown in FIG. 9, NO is used as the delay means.
The T circuit (inverter circuit) 103 was mounted. However, the present invention is not limited to the above examples, and TW
This inverter circuit may be built in an IC constituting the INS-B7.

An embodiment of the sixth invention according to the present invention, in which an inverter circuit is incorporated in an IC constituting the TWINS-B7 to prevent operation at the same timing by correcting an operation clock signal, is shown in FIG. This will be described with reference to FIG. FIG. 10 is a diagram showing a state in which an inverter circuit is built in TWINS-B according to the sixth embodiment of the present invention. In the sixth embodiment shown in FIG. 10, the NOT circuit 103 is used as a delay unit for the clock signal from the oscillation circuit 9 so as to constitute the TWINS-B7.
C has two terminals, namely, a terminal for using a clock signal supplied from the oscillation circuit 9 as a clock through the NOT circuit 103 and a terminal for using the clock signal as a clock without passing through the NOT circuit 103 as it is.

As described above, in the sixth embodiment, N
The phase is rotated by 180 degrees by the OT circuit 103, and the operation timing is controlled so as not to be the same.

As described above, according to the sixth embodiment, since the delay circuit is constituted by the inverter circuit 103 for inverting a digital signal, a simple circuit can be realized.
Radiation noise can be reduced and the cost of the device can be reduced.

[Seventh Embodiment] A seventh embodiment according to the present invention.
An embodiment of the present invention will be described with reference to FIG. FIG. 11 is a diagram showing a configuration example of the clock signal delay means of the option board 20 according to the seventh embodiment of the present invention. In the sixth embodiment shown in FIG.
As means for delaying the clock signal from the oscillation circuit 9, the oscillation circuit 9 on the option board 20 and the pattern shown in FIG.

In FIG. 11, a portion indicated by a solid line is a conductor pattern disposed on the front surface of the substrate, and a portion indicated by a chain line is a conductor pattern disposed on the back surface of the substrate. It is used as a conductor pattern connecting between TWINS-B7.

In the sixth embodiment, as shown in FIG. 11, a delay circuit is formed by inductance components on a substrate.

As described above, also in the seventh embodiment, the radiation noise can be reduced and the cost of the device can be reduced with a simple configuration.

[Eighth Embodiment] In the second embodiment shown in FIG. 4, the TWINS-A6 and the TWI
The phase of the operation clock signal of the NS-B7 is shifted, thereby reducing radiation noise and reducing the cost of the device.

However, the present invention is not limited to the above-described example, and the FU which can be constituted by ICs having the same structure.
The operation clock signals to be supplied to the NK-A4 and the FUNK-B11 may be different from each other to reduce radiation noise and reduce the cost of the device. And the second shown in FIG.
As in the embodiment, the oscillator 9 can be provided on the facsimile apparatus main body side.

An oscillator 9 is provided on the facsimile apparatus main body 1 side, and an eighth embodiment of the present invention according to the present invention in which the phases of operation clock signals supplied to FUNK-A4 and FUNK-B11 are shifted is shown in FIG. This will be described with reference to FIG. FIG. 12 is a block diagram showing a schematic configuration of a communication control and option board portion of a facsimile apparatus according to an eighth embodiment of the present invention.

Referring to FIG. 12, the first
The same reference numerals are given to the same configurations as those of the embodiment and the second embodiment shown in FIG. 4, and the detailed description is omitted. In FIG. 12, only the communication control of the facsimile machine and the option board portion are shown, and the public line network and the like are omitted.

1 and 4 are different from those of FIGS. 1 and 4 in that a clock signal from an oscillator 9 provided on the facsimile apparatus main body 1 side is supplied to the FUNK-A4 and the I / FA
(3) The signal is sent to the delay circuit 10 of the option board 20 via the I / FB 5, where the signal is delayed and then supplied to the FUNK-B11.

As a result, the clock signal from the oscillator 9 is supplied to the delay circuit 1 via the I / F3, the cable 80, and the I / F5.
0 and supplied to FUNK-B11. And
Both TWINS-A6 and TWINS-B7 are arranged on the option board 20 side.

As described above, according to the eighth embodiment, the clock signal generated in the facsimile apparatus main body 1 is converted to the IC (FUNK-
A4) The same IC (FUNK-B11) as in (A4) and the option board 20 containing the delay circuit 10 are sent to the delay circuit 1
By supplying the same IC (FUNK-B11) with the phase shifted by 0, radiation noise can be reduced and the cost of the device can be reduced.

[Ninth Embodiment] The ninth embodiment shown in FIG.
In the embodiment, the FUNK-A4 and the FUNK
Although the phase of the operation clock signal supplied to -B11 is shifted to reduce radiation noise and reduce the cost of the device, both TWINS-A6 and TWINS-B7 are arranged on the option board 20 side.

However, the present invention is not limited to the above example, and the TW is similar to that of the second embodiment shown in FIG.
INS-A6 is attached to the facsimile machine body 1 side, TWIN
The SB 7 may be provided on the option board 20 side. An embodiment of the ninth invention according to the present invention thus constituted will be described below with reference to FIG. FIG. 13 is a block diagram showing a schematic configuration of a communication control and option board portion of a facsimile apparatus according to a ninth embodiment of the present invention.

In FIG. 13, the TWINS-A6 is provided on the facsimile apparatus main body 1 side and the TWINS-B7 is provided on the option board 20 side similarly to the second embodiment shown in FIG. 4 is different from the configuration of FIG. 4 in that one of the clock signals from the oscillator 9 is supplied to the FUNK-A4 and sent to the delay circuit 10 of the option board 20 via the I / FA3 and I / FB5. FU
This is the point of supply to NK-B11.

As a result, the clock signal from the oscillator 9 is supplied to the delay circuit 1 via the I / F3, the cable 80, and the I / F5.
0 and supplied to FUNK-B11.

As described above, according to the ninth embodiment, the clock signal generated in the facsimile apparatus main body 1 is converted to the IC (FUNK-
A4) The same IC (FUNK-B11) as in (A4) and the option board 20 containing the delay circuit 10 are sent to the delay circuit 1
By supplying the same IC (FUNK-B11) with the phase shifted by 0, radiation noise can be reduced and the cost of the device can be reduced.

[Tenth Embodiment] In the fourth embodiment described above, the stray capacitance (straight capacity) generated between the resistance component of the bent pattern 101 on the option substrate 20 and the ground pattern 102 ), A delay circuit is formed, and the clock signal delayed by this delay circuit is supplied to the TWINS-B11.

However, the present invention is not limited to the above example, and the signal delayed by the same delay circuit as that of the fourth embodiment shown in FIG. 6 is not TWINS-B11 but
FUNK like the eighth and ninth embodiments described above.
-B11.

The tenth embodiment according to the present invention thus constituted will be described below with reference to FIG.
FIG. 14 is a block diagram showing a schematic configuration of a communication control and option board portion of a facsimile apparatus according to a tenth embodiment of the present invention.

In FIG. 14, the clock signal delayed in the fourth embodiment shown in FIG.
It was supplied to S-B11, but is being supplied to FUNK-B11. Also in the tenth embodiment, a stray capacitance (stray capacity) is provided between the bent pattern 101 and the ground pattern 102 on the option board 20.
And an equivalent circuit shown in FIG. 7 exists due to stray capacitance (stray capacity) generated between the resistance component of the bent pattern 101 and the ground pattern 102.

As a result, both patterns 101 shown in FIG.
The phase of the clock signal can also be made different by configuring the delay means with the RC integration circuit formed at 102. Also in the tenth embodiment, the delay is performed at the delay timing shown in FIG.

As described above, also in the tenth embodiment, the radiation noise can be reduced and the cost of the apparatus can be reduced by using only simple components.

[Eleventh Embodiment] In the above-described fifth embodiment, a delay circuit is formed by a NOT circuit (inverter circuit) 103 as shown in FIG. TWINS-B
11 had been supplied.

However, the present invention is not limited to the above example, and the signal delayed by the same delay circuit as in the fifth embodiment shown in FIG.
As in the eighth to tenth embodiments, the FUN
It may be supplied to KB11.

An eleventh embodiment according to the present invention having the above-described structure will be described below with reference to FIG.
FIG. 15 is a diagram showing a configuration example of the delay circuit of the option board 20 according to the eleventh embodiment of the present invention.

As described above, in the eleventh embodiment,
The phase is rotated by 180 degrees by the NOT circuit 103, and the operation timing is controlled so as not to be the same.

As described above, according to the eleventh embodiment, since the delay circuit is constituted by the inverter circuit 103 for inverting the digital signal, the radiation noise can be reduced and the cost of the device can be reduced with a simple circuit. Down can be achieved.

[Twelfth Embodiment] FIG.
In the eleventh embodiment shown in (1), the NOT circuit (inverter circuit) 103 is mounted as the delay means. However, the present invention is not limited to the above example, and the inverter circuit may be built in an IC constituting the FUNK-B11.

FIG. 17 shows an embodiment of the twelfth invention according to the present invention in which an inverter circuit is incorporated in an IC constituting the FUNK-B11, and an operation clock signal is corrected to prevent operation at the same timing. 16 will be described. FIG. 16 is a diagram showing a state in which an inverter circuit is incorporated in the FUNK-B11 according to the twelfth embodiment of the present invention. In the twelfth embodiment shown in FIG. 16, a NOT circuit 103 is incorporated in an IC constituting the FUNK-B11 as a means for delaying a clock signal from the oscillation circuit 9, and a clock signal supplied from the oscillation circuit 9 is provided. Is used as a clock through the NOT circuit 103 and a terminal used as a clock without passing through the NOT circuit 103 as it is.

As described above, in the twelfth embodiment,
The phase is rotated by 180 degrees by the NOT circuit 103, and the operation timing is controlled so as not to be the same.

As described above, according to the twelfth embodiment, since the delay circuit is constituted by the inverter circuit 103 for inverting the digital signal, the radiation noise can be reduced and the cost of the device can be reduced with a simple circuit. Down can be achieved.

[Thirteenth Embodiment] FIG.
In the ninth embodiment shown in FIG.
And the phase of the operation clock signal supplied to the FUNK-B11 is shifted, thereby reducing radiation noise and reducing the cost of the apparatus.

However, the present invention is not limited to the above example. The phase of the clock signal supplied to the CPU A2 of the facsimile apparatus main body 1 and the phase of the clock signal supplied to the CPU B8 of the option board 20 are shifted to reduce radiation noise and reduce the cost of the apparatus. You may achieve down.

The thirteenth embodiment of the present invention thus constituted will be described below with reference to FIG.
FIG. 17 is a block diagram showing a schematic configuration of a communication control and option board portion of a facsimile apparatus according to a thirteenth embodiment of the present invention.

In FIG. 17, a configuration different from the configuration of the ninth embodiment shown in FIG. 12 is that one of the clock signals from the oscillator 9 is supplied to the CPU A2 and the I / O
This is that the signal is sent to the delay circuit 10 of the option board 20 via the FA 3 and the I / FB 5, and is supplied to the CPU B 8 after being delayed here.

As described above, according to the thirteenth embodiment, the clock signal generated in the facsimile apparatus main body 1 is converted into an IC (CPU
2) By sending the same IC (CPUB8) and the option board 20 containing the delay circuit 10 to the optional substrate 20 containing the delay circuit 10 and shifting the phase by the delay circuit 10 and supplying the same to the same IC (CPUB8), the radiation noise can be reduced and Cost reduction can be achieved.

[Fourteenth Embodiment] In the thirteenth embodiment shown in FIG. 17, both TWINS-A6 and TWINS-B7 are disposed on the option board 20 side. However, the present invention is not limited to the above example, and is similar to the ninth embodiment shown in FIG.
NS-A6 is attached to the facsimile machine body 1 side, TWINS
-B7 may be provided on the option board 20 side. The fourteenth embodiment of the present invention thus configured will be described below with reference to FIG. FIG. 18 is a block diagram showing a schematic configuration of a communication control and option board portion of a facsimile apparatus according to a fourteenth embodiment of the present invention.

In FIG. 18, the TWINS-A6 is provided on the facsimile apparatus body 1 side and the TWINS-B7 is provided on the option board 20 side similarly to the ninth embodiment shown in FIG. 13 is different from the configuration in FIG. 13 in that one of the clock signals from the oscillator 9 is supplied to the CPU A2 and sent to the delay circuit 10 of the option board 20 via the I / FA3 and the I / FB5, where the signal is delayed. After C
This is the point supplied to PUB8.

As described above, according to the fourteenth embodiment, the clock signal generated in the facsimile apparatus main body 1 is converted into an IC (CPUA) on the facsimile apparatus main body 1 side.
2) By sending the same IC (CPUB8) and the option board 20 containing the delay circuit 10 to the optional substrate 20 containing the delay circuit 10 and shifting the phase by the delay circuit 10 and supplying the same to the same IC (CPUB8), the radiation noise can be reduced and Cost reduction can be achieved.

[Fifteenth Embodiment] In the above-described fourth embodiment shown in FIG.
A delay circuit is formed by the stray capacitance (stray capacity) generated between the resistance component of the bent pattern 101 on the zero and the ground pattern 102, and the clock signal delayed by the delay circuit is supplied to the TWINS-B11. Was.

However, the present invention is not limited to the above example, and the signal delayed by the same delay circuit as that of the fourth embodiment shown in FIG. 6 is not TWINS-B11.
As in the thirteenth and fourteenth embodiments, the CP
The signal before the delay may be supplied to the UB8 and the signal before the delay may be supplied to the CPUA2.

The fifteenth embodiment of the present invention thus constituted will be described below with reference to FIG.
FIG. 19 is a block diagram showing a schematic configuration of a communication control and option board portion of a facsimile apparatus according to a fifteenth embodiment of the present invention.

In FIG. 19, the clock signal delayed in the fourth embodiment shown in FIG.
Although the signal was supplied to the SB-B11, the signal was supplied to the CPUB8 instead of the TWINS-B11, and the signal before delay was supplied to the CPUA.
2 Also in the fifteenth embodiment,
A stray capacitance (straight capacity) is generated between the bent pattern 101 and the ground pattern 102 on the option substrate 20, and a stray capacitance (straight capacity) generated between the resistance component of the bent pattern 101 and the ground pattern 102. (City), the equivalent circuit shown in FIG. 7 exists.

As a result, both patterns 101 shown in FIG.
The phase of the clock signal can also be made different by configuring the delay means with the RC integration circuit formed at 102. Also in the fifteenth embodiment, the delay is performed at the delay timing shown in FIG.

As described above, also in the fifteenth embodiment, the radiation noise can be reduced and the cost of the apparatus can be reduced with only simple components.

[Sixteenth Embodiment] In the above-described fifth embodiment, a NOT circuit (inverter circuit) 103 forms a delay circuit as shown in FIG. TWINS-B
11 had been supplied.

However, the present invention is not limited to the above example, and the signal delayed by the same delay circuit as in the fifth embodiment shown in FIG. 9 is not TWINS-B11 but
As in the thirteenth to fifteenth embodiments, the CP
The signal before the delay may be supplied to the UB8 and the signal before the delay may be supplied to the CPUA2.

An embodiment of the sixteenth invention according to the present invention thus constituted will be described below with reference to FIG.
FIG. 20 is a diagram showing a configuration example of the delay circuit according to the sixteenth embodiment of the present invention.

As described above, in the sixteenth embodiment,
The phase is rotated by 180 degrees by the NOT circuit 103, and the operation timing is controlled so as not to be the same.

As described above, according to the sixteenth embodiment, since the delay circuit is constituted by the inverter circuit 103 for inverting a digital signal, the radiation noise can be reduced and the cost of the apparatus can be reduced with a simple circuit. Down can be achieved.

[Seventeenth Embodiment] FIG.
In the sixteenth embodiment shown in (1), a NOT circuit (inverter circuit) 103 is mounted as delay means. However, the present invention is not limited to the above example, and the inverter circuit may be built in an IC constituting the CPU B8.

Referring to FIG. 21, a seventeenth embodiment of the present invention in which an inverter circuit is incorporated in CPU B8 to prevent operation at the same timing by correcting an operation clock signal will be described with reference to FIG. I do. FIG. 21 is a diagram showing a state in which an inverter circuit is incorporated in CPUB8 according to the seventeenth embodiment of the present invention. In the seventeenth embodiment shown in FIG. 21, a NOT circuit 103 is incorporated in an IC constituting the CPUB8 as a means for delaying a clock signal from the oscillation circuit 9, and the oscillation circuit 9
A terminal that uses the clock signal supplied from the NOT circuit 103 as a clock through the NOT circuit 103 and the NOT circuit 1
It contains two terminals, one that is used as a clock without passing through 03.

As described above, in the seventeenth embodiment,
The phase is rotated by 180 degrees by the NOT circuit 103, and the operation timing is controlled so as not to be the same.

As described above, according to the seventeenth embodiment, since the delay circuit is constituted by the inverter circuit 103 for inverting a digital signal, the radiation noise can be reduced and the cost of the device can be reduced with a simple circuit. Down can be achieved.

[Other Embodiments] Even if the present invention is applied to a system constituted by a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), an apparatus comprising one device (For example, a copying machine, a facsimile machine, etc.).

Further, an object of the present invention is to supply a storage medium storing a program code of software for realizing the functions of the above-described embodiments to a system or an apparatus, and to provide a computer (or CPU) of the system or the apparatus.
And MPU) read and execute the program code stored in the storage medium.

[0124]

As described above, according to the present invention, in an electronic device system including a plurality of electronic circuit sections operating with clock signals of the same frequency, an original clock generated by clock generating means for generating a clock signal is used. By delaying the signal by the delay means and shifting the phase of the clock signal to supply it to each electronic circuit section, it is possible to reduce the radiation noise and reduce the cost of the device with a simple and inexpensive configuration.

[0125]

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a communication control and option board portion of a facsimile apparatus according to an embodiment of the present invention;

FIG. 2 is a block diagram showing a detailed configuration of a facsimile apparatus main body shown in FIG.

FIG. 3 is a block diagram showing a detailed configuration of an option board shown in FIG. 1;

FIG. 4 is a block diagram showing a schematic configuration of a communication control and option board portion of the facsimile apparatus according to the second embodiment of the present invention;

FIG. 5 is a block diagram showing a schematic configuration of a communication control and option board portion of the facsimile apparatus according to the third embodiment of the present invention;

FIG. 6 is a diagram illustrating a configuration example of a clock signal delay unit of an option board according to a fourth embodiment of the present invention;

FIG. 7 is a diagram showing an equivalent circuit of the clock delay unit shown in FIG. 6 in the fourth embodiment.

FIG. 8 is a diagram for explaining the principle of delay of a clock signal by the equivalent circuit shown in FIG. 7;

FIG. 9 is a diagram showing a configuration example of a delay circuit of an option board according to a fifth embodiment of the present invention;

FIG. 10 is a graph showing T of the sixth embodiment of the present invention;
It is a figure showing the state where an inverter circuit was built in WINS-B.

FIG. 11 is a diagram showing a configuration example of a clock signal delay unit of an option board according to a seventh embodiment of the present invention;

FIG. 12 is a block diagram showing a schematic configuration of a communication control and option board portion of a facsimile apparatus according to an eighth embodiment of the present invention;

FIG. 13 is a block diagram showing a schematic configuration of a communication control and option board portion of a facsimile apparatus according to a ninth embodiment of the present invention;

FIG. 14 is a block diagram showing a schematic configuration of a communication control and option board portion of a facsimile apparatus according to a tenth embodiment of the present invention.

FIG. 15 is a diagram illustrating a configuration example of a delay circuit of an option board according to an eleventh embodiment of the present invention;

FIG. 16 is a diagram showing a state in which an inverter circuit is incorporated in FUNK-B according to the twelfth embodiment of the present invention.

FIG. 17 is a block diagram showing a schematic configuration of a communication control and option board portion of a facsimile apparatus according to a thirteenth embodiment of the present invention;

FIG. 18 is a block diagram showing a schematic configuration of a communication control and option board portion of a facsimile apparatus according to a fourteenth embodiment of the present invention.

FIG. 19 is a block diagram showing a schematic configuration of a communication control and option board portion of a facsimile apparatus according to a fifteenth embodiment of the present invention.

FIG. 20 is a diagram illustrating a configuration example of a delay circuit according to a sixteenth embodiment of the present invention;

FIG. 21 is a diagram showing a state in which an inverter circuit is incorporated in CPUB8 according to the seventeenth embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Facsimile apparatus main body 2 CPU-A 3 External interface A (I / FA) 4 FUNK-A 5 External interface B (I / FB) 6 TWINS-A 7 TWINS-B 8 CPU-B 9 Oscillator (oscillation circuit) 10 Delay Circuit 11 FUNK-B 20 Optional board (option board) 30 Recording unit 40 First control unit 41 Document reading unit 42 Document transport motor 43 Network control unit (NCU) 44 Modulation / demodulation unit (modem) 45 Operation panel 46 Display 47 Key 48 First sensor 49 First drive system 50 Read image processing unit 51, 65 Memory 52, 66 Image memory 53, 67 System RAM (system memory) 54, 68 ROM 55, 69 Magnification processing unit 56, 61 57, 62 Decoder 60 Second control unit 63 Network controller (NC ) 64 modulator demodulator (modem) 80 I / F cable 100 public network 103 inverter circuit (NOT circuit) 200 another facsimile machine

Claims (24)

[Claims] 1. An electronic device system including a plurality of electronic circuit units operating with clock signals of the same frequency, comprising: a clock generation unit for generating the clock signal; and an original clock signal generated by the clock generation unit. An electronic device system, comprising: delay means for delaying, and delaying the original clock signal by the delay means to shift the phase of the clock signal and supply the shifted clock signal to each electronic circuit unit. 2. The electronic device system according to claim 1, wherein the plurality of electronic circuit units are each configured by a semiconductor integrated circuit having the same configuration. Further, when the external interface means and an external device connected to the external interface means have the same electronic circuit part as the electronic circuit part provided in the own apparatus, the clock signal delayed by the delay means is provided. The electronic device system according to claim 1, further comprising a supply unit configured to supply the external device. 4. The electronic device system according to claim 1, wherein the electronic device system is an optional board connected to an information processing device having an external interface. 5. An electronic device system connected to an information processing device having external interface means, comprising: a clock receiving unit for receiving an operation clock signal of an electronic circuit unit included in the information processing device; An electronic circuit unit having the same configuration as the circuit unit; and a delay unit for delaying the clock signal received by the clock receiving unit by a predetermined time, and supplying the clock signal delayed by the delay unit to the electronic circuit unit. An electronic device system, wherein the electronic circuit unit is operated by a clock signal having a phase different from that of the information processing device. 6. An electronic device system comprising: an electronic device main body having an external interface; and an external device connected to the electronic device main body via the external interface, wherein the electronic device main body provided in the electronic device main body operates. A first system control unit to operate, a second system control unit to operate its own device provided in the external device, and the electronic device provided between the first system control unit and the second system control unit First interface means on the main body side and second interface means on the external device side; the first system control unit and the second system control provided in each of the first and second interface means An electronic circuit unit having the same configuration that operates with a clock of the same frequency for performing bidirectional communication between the units, and an operation of the electronic circuit unit. And a clock generating means for generating a clock,
The first and second interface units each include a delay unit for delaying the clock signal generated by the clock generation unit and a delay unit for delaying the delay unit so that operation clocks supplied to the respective electronic circuit units do not have the same phase. An electronic device system characterized by different amounts. 7. An electronic device system comprising an electronic device main body having an external interface, and an external device connected to the electronic device main body via the external interface, wherein the electronic device main body provided in the electronic device main body operates. A first system control unit to be operated, a second system control unit that operates its own device provided in the external device, and the first system control unit and the second system control unit, each of which is provided in the second system control unit. An electronic circuit unit having the same configuration that operates with a clock of the same frequency for operating the first system control unit and the second system control unit, a clock generation unit that generates an operation clock of the electronic circuit unit, And a delay unit for delaying the clock signal generated by the clock generation unit, wherein the first and second system control units have respective Electronics system, characterized in that the supply operation clocks to the electronic circuit unit to vary the delay amount of said delay means so as not to the same phase. 8. The electronic device system according to claim 7, wherein the electronic circuit unit is a CPU circuit that controls each device. 9. The electronic device according to claim 6, wherein the electronic device main body is a facsimile communication device, and the external device is an option board connected to the facsimile communication device. Electronic device system. 10. The first system control unit controls transmission image reading or copy image reading control and reception image recording or copy image recording control in a facsimile communication device, and the second system control unit includes an option board. 10. A communication control via a line different from a line connected to the facsimile communication device in the above.
An electronic device system according to claim 1. 11. The delay means is formed by an integration circuit formed by a resistance component of a wiring pattern on a mounting board and a capacitance component generated between the wiring pattern and a ground pattern on the mounting board. The electronic device system according to any one of claims 1 to 10, wherein 12. The electronic device system according to claim 1, wherein said delay means is constituted by an inverter digital circuit. 13. The electronic device system according to claim 1, wherein the delay unit is configured by an inductance component generated on a mounting board. 14. An electronic circuit comprising: a plurality of electronic circuit units operating with clock signals of the same frequency; clock generating means for generating said clock signal; and delay means for delaying an original clock signal generated by said clock generating means. A method for controlling an electronic device system, comprising: delaying the original clock signal by the delay means to shift the phase of the clock signal to supply the shifted clock signal to each electronic circuit unit. 15. The control method for an electronic device system according to claim 14, wherein each of the plurality of electronic circuit units is configured by a semiconductor integrated circuit having the same configuration. 16. The electronic device system is connectable to an external device via an external interface unit. When the external device has the same electronic circuit unit as that of the own device, the electronic device system uses the delay unit. 16. The control method according to claim 14, wherein a delayed clock signal is supplied to the external device. 17. A clock receiving means for receiving an operation clock signal of an electronic circuit provided in the information processing apparatus, an electronic circuit having the same configuration as the electronic circuit of the information processing apparatus, and a clock received by the clock receiving means. A delay means for delaying a signal for a predetermined time, wherein the control method is for controlling an electronic device system connected to an information processing apparatus having an external interface means, wherein the clock signal delayed by the delay means is supplied to the electronic circuit unit. And controlling the electronic circuit unit with a clock signal having a phase different from that of the information processing apparatus. 18. An electronic device main body having a first system control unit and an external interface for operating its own device, and a second system control unit for operating its own device, wherein said electronic device main unit is provided via said external interface. An electronic device system comprising an external device connected to the
A first interface unit on the electronic device main body side and a second interface unit on the external device side provided between the first system control unit and the second system control unit; Provided in each of the interface means, an electronic circuit unit of the same configuration operating with a clock of the same frequency for performing bidirectional communication between the first system control unit and the second system control unit; A control method of an electronic device system, comprising: a clock generation unit that generates an operation clock of a circuit unit; and a delay unit that delays a clock signal generated by the clock generation unit, wherein each of the first and second interface units includes: It is characterized in that the delay amounts of the delay means are made different so that the operation clocks supplied to the electronic circuit section included in the delay means do not have the same phase. A method of controlling an electronic device system. 19. An electronic device main unit having a first system control unit for operating the own device and an external interface, and a second system control unit connected to the electronic device main unit via the external interface and operating the own device. An external device comprising: a clock of the same frequency for operating the first system control unit and the second system control unit in each of the first system control unit and the second system control unit A control circuit for an electronic device system, comprising: an electronic circuit unit having the same configuration that operates on the same; a clock generation unit that generates an operation clock of the electronic circuit unit; and a delay unit that delays a clock signal generated by the clock generation unit. The first and second system control units determine that the operation clocks supplied to the respective electronic circuit units have the same phase. Method of controlling an electronic system for causing unusually different delay amount of said delay means. 20. The method according to claim 19, wherein said electronic circuit section is a CPU circuit for controlling each device. 21. The electronic device according to claim 18, wherein the electronic device main body is a facsimile communication device, and the external device is an option board connected to the facsimile communication device. A control method for an electronic device system. 22. The first system control section controls transmission image reading or copy image reading control and reception image recording or copy image recording control in a facsimile communication apparatus, and the second system control section includes an option board. 3. A communication control via a line different from a line connected to the facsimile communication device in the step (a).
2. The control method for an electronic device system according to claim 1. 23. A computer-readable recording medium for storing a control procedure for realizing each function described in each of claims 1 to 22. 24. A computer program sequence for realizing each function described in each of claims 1 to 22.